Abstract: A transistor having a source region and a drain region which are separately formed in a substrate, a trench which is defined in the substrate between the source region and the drain region, and a gate electrode which is formed in the trench. The gate electrode includes a first electrode buried over a bottom of the trench; a second electrode formed over the first electrode; and a liner electrode having an interface part which is positioned between the first electrode and the second electrode and a side part, which is positioned on sidewalls of the second electrode and overlaps with the source region and the drain region.

Abstract: A method of fabricating a semiconductor device may include forming isolation structures that include openings, over a substrate; forming sacrificial spacers on sidewalls of the openings; forming, on the sacrificial spacers, first conductive patterns that are recessed in the openings; removing the sacrificial spacers, and defining air gaps; forming a liner layer that caps the first conductive patterns and the air gaps; forming second conductive patterns through silicidation of the liner layer; and forming third conductive patterns over the second conductive patterns.

Abstract: A method of fabricating a semiconductor device may include forming isolation structures that include openings, over a substrate; forming sacrificial spacers on sidewalls of the openings; forming, on the sacrificial spacers, first conductive patterns that are recessed in the openings; removing the sacrificial spacers, and defining air gaps; forming a liner layer that caps the first conductive patterns and the air gaps; forming second conductive patterns through silicidation of the liner layer; and forming third conductive patterns over the second conductive patterns.

Abstract: A semiconductor device with an isolation layer buried in a trench includes an interface layer formed on the surface of the trench, a buffer layer formed in the interface layer at a bottom corner of the trench, a liner layer formed over the interface layer, and a gap-fill layer gap-filling the trench over the liner layer. The trench includes a micro-trench formed at the bottom corner thereof, and the buffer layer fills the micro-trench.

Abstract: A method of fabricating a semiconductor device may include forming isolation structures that include openings, over a substrate; forming sacrificial spacers on sidewalks of the openings; forming, on the sacrificial spacers, first conductive patterns that are recessed in the openings; removing the sacrificial spacers, and defining air gaps; forming a liner layer that caps the first conductive patterns and the air gaps; forming second conductive patterns through silicidation of the liner layer; and forming third conductive patterns over the second conductive patterns.

Abstract: Methods of manufacturing a semiconductor device are provided. The method includes forming an isolation region in a substrate to define active regions extending in a single direction and being spaced apart from each other by the isolation region, forming a conductive layer in the isolation region and the active regions, etching the conductive layer to form bit line trenches extending in a first direction that is non-perpendicular to the single direction, forming bit line patterns in respective ones of the bit line trenches, etching the conductive layer to form a plurality of plug trenches two dimensionally arrayed along the first direction and a second direction perpendicular to the first direction, and filling the plug trenches with an insulation material to define conductive plug patterns in portions of the active regions. Related semiconductor devices are also provided.

Abstract: A semiconductor device includes a first capacitor in a trench of a semiconductor substrate and an active pillar disposed on the semiconductor substrate opposite the first capacitor. The active pillar includes first region, first channel region, second region, second channel region and third region, sequentially stacked. A pillar connection pattern electrically connects the first capacitor to a first source region. A first gate electrode is disposed on a sidewall of the first channel region. A common drain region is disposed in the second region, and a common bit line is disposed on a sidewall of the common drain region. A second gate electrode is disposed on a sidewall of the second channel region, and a second source region is disposed in the third region. A second capacitor is disposed on a top surface of the second source region opposite the second channel region.

Abstract: A semiconductor device with an isolation layer buried in a trench includes an interface layer formed on the surface of the trench, a buffer layer formed in the interface layer at a bottom corner of the trench, a liner layer formed over the interface layer, and a gap-fill layer gap-filling the trench over the liner layer. The trench includes a micro-trench formed at the bottom corner thereof, and the buffer layer fills the micro-trench.

Abstract: A method for fabricating a semiconductor device includes forming a pad nitride layer that exposes an isolation region over a cell region of a semiconductor substrate; forming a trench in the isolation region of the semiconductor substrate; forming an isolation layer within the trench; etching an active region of the semiconductor substrate by a certain depth to form a recessed isolation region; etching the isolation layer by a certain depth to form a recessed isolation region; depositing a gate metal layer in the recessed active region and the recessed isolation region to form a gate of a cell transistor; forming an insulation layer over an upper portion of the gate; removing the pad nitride layer to expose a region of the semiconductor substrate to be formed with a contact plug; and depositing a conductive layer in the region of the semiconductor substrate to form a contact plug.

Abstract: A semiconductor device with an isolation layer buried in a trench includes an interface layer formed on the surface of the trench, a buffer layer formed in the interface layer at a bottom corner of the trench, a liner layer formed over the interface layer, and a gap-fill layer gap-filling the trench over the liner layer. The trench includes a micro-trench formed at the bottom corner thereof, and the buffer layer fills the micro-trench.

Abstract: A semiconductor device is fabricated by, inter alia, forming a sacrificial liner on an active portion of a semiconductor substrate, oxidizing the sacrificial liner to transform the sacrificial liner into a gate dielectric layer, and forming a gate on the gate dielectric layer.

Abstract: A semiconductor device includes a first capacitor in a trench of a semiconductor substrate and an active pillar disposed on the semiconductor substrate opposite the first capacitor. The active pillar includes first region, first channel region, second region, second channel region and third region, sequentially stacked. A pillar connection pattern electrically connects the first capacitor to a first source region. A first gate electrode is disposed on a sidewall of the first channel region. A common drain region is disposed in the second region, and a common bit line is disposed on a sidewall of the common drain region. A second gate electrode is disposed on a sidewall of the second channel region, and a second source region is disposed in the third region. A second capacitor is disposed on a top surface of the second source region opposite the second channel region.

Abstract: A semiconductor device with an isolation layer buried in a trench includes an interface layer formed on the surface of the trench, a buffer layer formed in the interface layer at a bottom corner of the trench, a liner layer formed over the interface layer, and a gap-fill layer gap-filling the trench over the liner layer. The trench includes a micro-trench formed at the bottom corner thereof, and the buffer layer fills the micro-trench.

Abstract: A method for fabricating a semiconductor device includes forming a pad nitride layer that exposes an isolation region over a cell region of a semiconductor substrate; forming a trench in the isolation region of the semiconductor substrate; forming an isolation layer within the trench; etching an active region of the semiconductor substrate by a certain depth to form a recessed isolation region; etching the isolation layer by a certain depth to form a recessed isolation region; depositing a gate metal layer in the recessed active region and the recessed isolation region to form a gate of a cell transistor; forming an insulation layer over an upper portion of the gate; removing the pad nitride layer to expose a region of the semiconductor substrate to be formed with a contact plug; and depositing a conductive layer in the region of the semiconductor substrate to form a contact plug.

Abstract: A semiconductor device includes a step-type recess pattern formed in a substrate, a gate electrode buried in the recess pattern and having a gap disposed between the gate electrode and upper sidewalls of the recess pattern, an insulation layer filling the gap, and a source and drain region formed in a portion of the substrate at two sides of the recess pattern. The semiconductor device is able to secure a required data retention time by suppressing the increase of leakage current caused by the reduction of a design rule.

Abstract: Methods of manufacturing a semiconductor device are provided. The method includes forming an isolation region in a substrate to define active regions extending in a single direction and being spaced apart from each other by the isolation region, forming a conductive layer in the isolation region and the active regions, etching the conductive layer to form bit line trenches extending in a first direction that is non-perpendicular to the single direction, forming bit line patterns in respective ones of the bit line trenches, etching the conductive layer to form a plurality of plug trenches two dimensionally arrayed along the first direction and a second direction perpendicular to the first direction, and filling the plug trenches with an insulation material to define conductive plug patterns in portions of the active regions. Related semiconductor devices are also provided.

Abstract: A method for fabricating a semiconductor device includes forming a pad nitride layer that exposes an isolation region over a cell region of a semiconductor substrate; forming a trench in the isolation region of the semiconductor substrate; forming an isolation layer within the trench; etching an active region of the semiconductor substrate by a certain depth to form a recessed isolation region; etching the isolation layer by a certain depth to form a recessed isolation region; depositing a gate metal layer in the recessed active region and the recessed isolation region to form a gate of a cell transistor; forming an insulation layer over an upper portion of the gate; removing the pad nitride layer to expose a region of the semiconductor substrate to be formed with a contact plug; and depositing a conductive layer in the region of the semiconductor substrate to form a contact plug.

Abstract: A semiconductor device includes a step-type recess pattern formed in a substrate, a gate electrode buried in the recess pattern and having a gap disposed between the gate electrode and upper sidewalls of the recess pattern, an insulation layer filling the gap, and a source and drain region formed in a portion of the substrate at two sides of the recess pattern. The semiconductor device is able to secure a required data retention time by suppressing the increase of leakage current caused by the reduction of a design rule.

Abstract: A semiconductor device includes a substrate with a recess pattern, a gate electrode filling the recess pattern, a threshold voltage adjusting layer formed in the substrate under the recess pattern, a source/drain region formed in the substrate on both sides of the gate electrode and a gate insulation layer, with the recess pattern being disposed between the gate electrode and the substrate, wherein the thickness of the gate insulation layer formed in a region adjacent to the source/drain region is greater than the thickness of the gate insulation layer formed in a region adjacent to the threshold voltage adjusting layer.

Abstract: Disclosed are a semiconductor device with a metal gate and a method of manufacturing the same.