Abstract: A method for fabricating an isolation layer in a semiconductor device, comprising: forming a trench in a semiconductor substrate; forming a flowable insulation layer on the trench and the semiconductor substrate; converting the flowable insulation layer to a silicon oxide layer by implementing a curing process comprising continuously heating the flowable insulation layer; and forming an isolation layer by planarizing the silicon oxide layer.

Abstract: A semiconductor device includes a substrate with a recess pattern, a gate electrode filling the recess pattern, a threshold voltage adjusting layer formed in the substrate under the recess pattern, a source/drain region formed in the substrate on both sides of the gate electrode and a gate insulation layer, with the recess pattern being disposed between the gate electrode and the substrate, wherein the thickness of the gate insulation layer formed in a region adjacent to the source/drain region is greater than the thickness of the gate insulation layer formed in a region adjacent to the threshold voltage adjusting layer.

Abstract: A semiconductor device includes a step-type recess pattern formed in a substrate, a gate electrode buried in the recess pattern and having a gap disposed between the gate electrode and upper sidewalls of the recess pattern, an insulation layer filling the gap, and a source and drain region formed in a portion of the substrate at two sides of the recess pattern. The semiconductor device is able to secure a required data retention time by suppressing the increase of leakage current caused by the reduction of a design rule.

Abstract: A semiconductor device having a recessed channel and a method for manufacturing the same. The semiconductor device comprises a semiconductor substrate formed with an isolation layer defining an active region including a channel region and a junction region, a recessed trench including a top trench formed within the channel region of the semiconductor substrate and a bottom trench formed from a bottom surface of the top trench with a width narrower than the top trench, and a gate stack overlapping the recessed trench and extending across the active region.

Abstract: Disclosed are a semiconductor device with a metal gate and a method of manufacturing the same.

Abstract: A landing plug contact in a semiconductor memory device is fabricated by: forming gate spacer layers at sides of the gate stacks to define a first contact hole and a second contact hole, where a landing plug contact will be formed between the gate spacer layers of the first contact hole and no landing plug contact is formed in the second contact hole; forming a conductive layer to fill at least the first and second contact holes; forming a hard mask pattern over the conductive layer to expose the conductive layer filling the second contact hole; removing the conductive layer filling the second contact hole by an etching process; forming an insulation layer to fill at least the second contact hole where the conductive layer is removed; and forming a landing plug contact within the contact hole by performing a planarization process on the insulation layer and the conductive layer.

Abstract: Disclosed are a semiconductor device with a metal gate and a method of manufacturing the same.

Abstract: Provided is a method for manufacturing a semiconductor device having a 4F2 transistor. In the method, a gate stack is formed on a semiconductor substrate. A first interlayer dielectric including a contact hole which includes a first region and second regions Spacer layers are formed on both sides of the gate stack and a portion of the second region. Landing plugs are formed on the contact hole, a portion of the semiconductor substrate exposed by a thickness of the spacer layer, and a lateral side of the trench. A second interlayer dielectric is formed to separate the landing plug. The bit line contact plug is connected to a first portion of the landing plug that extends to the lateral side of the trench. The bit line stack is connected to the bit line contact plug. The storage node contact plug is connected to the first portion and a second portion of the landing plug located at a corresponding position in a diagonal direction.

Abstract: A method for fabricating an isolation layer in a semiconductor device, comprising: forming a trench in a semiconductor substrate; forming a flowable insulation layer on the trench and the semiconductor substrate; converting the flowable insulation layer to a silicon oxide layer by implementing a curing process comprising continuously heating the flowable insulation layer; and forming an isolation layer by planarizing the silicon oxide layer.

Abstract: A method for manufacturing a semiconductor device having a bulb-type recessed channel including: forming a trench that defines an active region including a channel region having a sidewall and a junction region in a semiconductor substrate; forming a device isolation layer that buries the trench, and forming a sidewall pattern that covers the sidewall of the channel region; forming a bulb-type trench by overlapping with the channel region in the semiconductor substrate, and forming a bottom protrusion having a predetermined space parted from the device isolation layer by removing the sidewall pattern; and forming a gate stack that overlaps with the bulb-type trench and the bottom protrusion.

Abstract: A semiconductor device having a recessed channel and a method for manufacturing the same. The semiconductor device comprises a semiconductor substrate formed with an isolation layer defining an active region including a channel region and a junction region, a recessed trench including a top trench formed within the channel region of the semiconductor substrate and a bottom trench formed from a bottom surface of the top trench with a width narrower than the top trench, and a gate stack overlapping the recessed trench and extending across the active region.

Abstract: Provided are a semiconductor device with a channel of a FIN structure and a method for manufacturing the same. In the method, a device isolation layer defining an active region is formed on a semiconductor substrate. A recess trench with a first width is formed in the active region, and a trench with a second width larger than the first width is formed in the device isolation layer. The trench formed in the device isolation layer is filled with a capping layer. A cleaning process is performed on the recess trench to form a bottom protrusion of a FIN structure including a protrusion and a sidewall. Gate stacks filling the recess trench are formed. A landing plug, which is divided by the capping layer filling the trench, is formed between the gate stacks.

Abstract: A semiconductor device includes a substrate with a recess pattern, a gate electrode filling the recess pattern, a threshold voltage adjusting layer formed in the substrate under the recess pattern, a source/drain region formed in the substrate on both sides of the gate electrode and a gate insulation layer, with the recess pattern being disposed between the gate electrode and the substrate, wherein the thickness of the gate insulation layer formed in a region adjacent to the source/drain region is greater than the thickness of the gate insulation layer formed in a region adjacent to the threshold voltage adjusting layer.

Abstract: In manufacturing a PMOS transistor, a semiconductor substrate having an active region and a field region is formed with a hard mask layer, which covers a center portion of the active region on the substrate in a lengthwise direction of a channel. The hard mask layer exposes the center portion of the active region in a widthwise direction of the channel and covers both edges of the substrate and the field region adjacent to the both edges. The substrate is etched to a predetermined depth using the hard mask layer as an etching barrier. The hard mask layer is then removed. A gate covering the center portion of the active region is formed on the lengthwise direction of the channel. Source and drain regions are formed at both edges of the gate.

Abstract: A method for forming a semiconductor device having recess channel includes forming a hard mask film pattern for exposing first regions for forming the trenches on a semiconductor substrate; forming first trenches by a first etching process using the hard mask film pattern as a mask, and removing the hard mask film pattern; forming a barrier film on the semiconductor substrate including the first trenches; forming an ion implantation mask film for exposing the first trenches on the barrier film; forming an ion implantation region in the semiconductor substrate below the first trenches using the ion implantation mask film and the barrier film; forming bulb-shaped second trenches by a second etching process using the ion implantation mask film and the barrier film as a mask, so that bulb-type trenches for recess channels, each including the first trench and the second trench, are formed; and removing the ion implantation mask film and the barrier film.

Abstract: A semiconductor device having a recessed channel and a method for manufacturing the same. The semiconductor device comprises a semiconductor substrate formed with an isolation layer defining an active region including a channel region and a junction region, a recessed trench including a top trench formed within the channel region of the semiconductor substrate and a bottom trench formed from a bottom surface of the top trench with a width narrower than the top trench, and a gate stack overlapping the recessed trench and extending across the active region.

Abstract: A method for forming fine patterns in a semiconductor device includes forming a first mask layer over an etch target layer, forming a first pattern over the first mask layer, reducing a size of the first pattern, forming a first spacer on a side face of the first pattern, removing the first pattern and patterning the first mask layer using the first spacer as a mask and removing the first spacer. The method also includes oxidating a surface of the patterned first mask layer, forming the first mask layer with reduced size by removing the oxidated portion over the surface of the first mask layer, forming a second spacer on a side wall of the first mask layer and removing the first mask layer, and patterning the etch target layer using the second spacer as a mask.

Abstract: A method for fabricating a semiconductor device includes forming a pad nitride layer that exposes an isolation region over a cell region of a semiconductor substrate; forming a trench in the isolation region of the semiconductor substrate; forming an isolation layer within the trench; etching an active region of the semiconductor substrate by a certain depth to form a recessed isolation region; etching the isolation layer by a certain depth to form a recessed isolation region; depositing a gate metal layer in the recessed active region and the recessed isolation region to form a gate of a cell transistor; forming an insulation layer over an upper portion of the gate; removing the pad nitride layer to expose a region of the semiconductor substrate to be formed with a contact plug; and depositing a conductive layer in the region of the semiconductor substrate to form a contact plug.

Abstract: A method for fabricating a semiconductor device having a recess channel includes forming an isolation layer that delimits an active region over a semiconductor substrate; exposing a region to be formed with a bulb recess trench over the semiconductor substrate; forming an upper trench by etching the exposed portion of the semiconductor substrate; forming, on a side wall of the upper trench, a silicon nitride barrier layer that exposes a bottom face of the upper trench but blocks a side wall of the upper trench; forming a lower trench of a bulb type by etching the exposed bottom face of the upper trench using the etch barrier layer as an etch mask, to form the bulb recess trench including the upper trench and the lower trench; forming a fin-structured bottom protrusion part including an upper face and a side face by etching the isolation layer so that the isolation layer has a surface lower than the bottom face of the lower trench; and forming a gate stack overlapped with the bulb recess trench and the bottom

Abstract: A semiconductor device includes a step-type recess pattern formed in a substrate, a gate electrode buried in the recess pattern and having a gap disposed between the gate electrode and upper sidewalls of the recess pattern, an insulation layer filling the gap, and a source and drain region formed in a portion of the substrate at two sides of the recess pattern. The semiconductor device is able to secure a required data retention time by suppressing the increase of leakage current caused by the reduction of a design rule.