Patents by Inventor Jin Yul Lee

Jin Yul Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090278183
    Abstract: Provided are a semiconductor device with a channel of a FIN structure and a method for manufacturing the same. In the method, a device isolation layer defining an active region is formed on a semiconductor substrate. A recess trench with a first width is formed in the active region, and a trench with a second width larger than the first width is formed in the device isolation layer. The trench formed in the device isolation layer is filled with a capping layer. A cleaning process is performed on the recess trench to form a bottom protrusion of a FIN structure including a protrusion and a sidewall. Gate stacks filling the recess trench are formed. A landing plug, which is divided by the capping layer filling the trench, is formed between the gate stacks.
    Type: Application
    Filed: June 27, 2008
    Publication date: November 12, 2009
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventor: Jin Yul Lee
  • Publication number: 20090170261
    Abstract: Provided is a method for manufacturing a semiconductor device having a 4F2 transistor. In the method, a gate stack is formed on a semiconductor substrate. A first interlayer dielectric including a contact hole which includes a first region and second regions Spacer layers are formed on both sides of the gate stack and a portion of the second region. Landing plugs are formed on the contact hole, a portion of the semiconductor substrate exposed by a thickness of the spacer layer, and a lateral side of the trench. A second interlayer dielectric is formed to separate the landing plug. The bit line contact plug is connected to a first portion of the landing plug that extends to the lateral side of the trench. The bit line stack is connected to the bit line contact plug. The storage node contact plug is connected to the first portion and a second portion of the landing plug located at a corresponding position in a diagonal direction.
    Type: Application
    Filed: May 8, 2008
    Publication date: July 2, 2009
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventor: Jin Yul Lee
  • Publication number: 20090146243
    Abstract: A semiconductor device having a recessed channel and a method for manufacturing the same. The semiconductor device comprises a semiconductor substrate formed with an isolation layer defining an active region including a channel region and a junction region, a recessed trench including a top trench formed within the channel region of the semiconductor substrate and a bottom trench formed from a bottom surface of the top trench with a width narrower than the top trench, and a gate stack overlapping the recessed trench and extending across the active region.
    Type: Application
    Filed: May 15, 2008
    Publication date: June 11, 2009
    Applicant: XYNIX SEMICONDUCTOR INC.
    Inventor: Jin Yul Lee
  • Publication number: 20090072280
    Abstract: In manufacturing a PMOS transistor, a semiconductor substrate having an active region and a field region is formed with a hard mask layer, which covers a center portion of the active region on the substrate in a lengthwise direction of a channel. The hard mask layer exposes the center portion of the active region in a widthwise direction of the channel and covers both edges of the substrate and the field region adjacent to the both edges. The substrate is etched to a predetermined depth using the hard mask layer as an etching barrier. The hard mask layer is then removed. A gate covering the center portion of the active region is formed on the lengthwise direction of the channel. Source and drain regions are formed at both edges of the gate.
    Type: Application
    Filed: November 17, 2008
    Publication date: March 19, 2009
    Inventor: Jin Yul LEE
  • Patent number: 7468301
    Abstract: In manufacturing a PMOS transistor, a semiconductor substrate having an active region and a field region is formed with a hard mask layer, which covers a center portion of the active region on the substrate in a lengthwise direction of a channel. The hard mask layer exposes the center portion of the active region in a widthwise direction of the channel and covers both edges of the substrate and the field region adjacent to the both edges. The substrate is etched to a predetermined depth using the hard mask layer as an etching barrier. The hard mask layer is then removed. A gate covering the center portion of the active region is formed on the lengthwise direction of the channel. Source and drain regions are formed at both edges of the gate.
    Type: Grant
    Filed: December 12, 2005
    Date of Patent: December 23, 2008
    Assignee: Hynix Semiconductor Inc.
    Inventor: Jin Yul Lee
  • Publication number: 20080160700
    Abstract: A method for manufacturing a semiconductor device having a bulb-type recessed channel including: forming a trench that defines an active region including a channel region having a sidewall and a junction region in a semiconductor substrate; forming a device isolation layer that buries the trench, and forming a sidewall pattern that covers the sidewall of the channel region; forming a bulb-type trench by overlapping with the channel region in the semiconductor substrate, and forming a bottom protrusion having a predetermined space parted from the device isolation layer by removing the sidewall pattern; and forming a gate stack that overlaps with the bulb-type trench and the bottom protrusion.
    Type: Application
    Filed: June 11, 2007
    Publication date: July 3, 2008
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventor: Jin Yul Lee
  • Publication number: 20070155101
    Abstract: A method for forming a semiconductor device having recess channel includes forming a hard mask film pattern for exposing first regions for forming the trenches on a semiconductor substrate; forming first trenches by a first etching process using the hard mask film pattern as a mask, and removing the hard mask film pattern; forming a barrier film on the semiconductor substrate including the first trenches; forming an ion implantation mask film for exposing the first trenches on the barrier film; forming an ion implantation region in the semiconductor substrate below the first trenches using the ion implantation mask film and the barrier film; forming bulb-shaped second trenches by a second etching process using the ion implantation mask film and the barrier film as a mask, so that bulb-type trenches for recess channels, each including the first trench and the second trench, are formed; and removing the ion implantation mask film and the barrier film.
    Type: Application
    Filed: October 11, 2006
    Publication date: July 5, 2007
    Applicant: Hynix Semiconductor, Inc.
    Inventors: Jin Yul Lee, Min Ho Ha, Seon Yong Cha
  • Publication number: 20070004127
    Abstract: In fabricating a transistor having the round corner recess channel structure, a buffer layer and a hard mask layer are formed in the active area of a semiconductor substrate. The buffer layer and the hard mask layer are etched so as to expose a predetermined channel region of the active area in the substrate. The predetermined channel region is wet etched to undercut the buffer layer below the hard mask layer. The exposed area of the substrate is etched by using the hard mask layer as an etching barrier so as to form a recess. The hard mask layer is removed. Light etch treatment is performed to round out the top corner of the recess. The buffer layer is then removed.
    Type: Application
    Filed: December 14, 2005
    Publication date: January 4, 2007
    Inventor: Jin Yul Lee