Patents by Inventor Jin Zhao

Jin Zhao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250067647
    Abstract: Provided are an imaging method and system for residual stress of a basin insulator and a method for preparing a test block. The imaging method includes cutting and preparing a standard industrial sample of a basin insulator and testing the acoustoelastic coefficient of the standard industrial sample; then obtaining the residual stress data of the basin insulator and obtaining the spatial point sound velocity distribution of the basin insulator; finally, obtaining a stress distribution cloud map of the basin insulator by calculation of the attribute value and the coordinate data of a to-be-measured location, and performing reliability verification based on the residual stress data.
    Type: Application
    Filed: October 8, 2023
    Publication date: February 27, 2025
    Inventors: Jin HE, Chun HE, Songyuan LI, Qinghua TANG, Chi ZHANG, Rong CHEN, Qi ZHAO, Jin LI, Xiaobo SONG, Yue HAN, Meng CAO, Lin LI, Suya LI, Yanwei DONG, Zhengzheng MENG
  • Publication number: 20250070912
    Abstract: Methods, apparatus, and systems that relate to rate matching scheme design for polar coding, PAC coding, or other pre-transformed polar coding are described. One example method includes determining, by a first node, an output bit sequence having E bits based on an input bit sequence having K bits, wherein the output bit sequence is determined by 1) performing a polar transform with H components and 2) performing either no pre-transform or at least two pre-transform operations; wherein the polar transform is based on H polar matrices G(N0), G(N1), . . . , G(NH?1), wherein H, K and E are integers greater than 1, wherein a polar matrix G(Ni) is of size Ni. The method also includes transmitting, by the first node, a signal including the output bit sequence to a second node.
    Type: Application
    Filed: November 1, 2024
    Publication date: February 27, 2025
    Inventors: Chulong LIANG, Wei ZHAO, Jin XU, Liguang LI, Guanghui YU, Jian KANG, Qiang FU
  • Publication number: 20250062433
    Abstract: The present application relates to a silicone oil-based immersion coolant for an electronic component. The silicone oil-based immersion coolant for an electronic component includes a base oil and an additive. The base oil includes a low-viscosity silicone oil. The additive includes a silicone oil diluent and a thermally conductive inorganic filler. The viscosity of the low-viscosity silicone oil is less than or equal to 1000 cSt. The thermally conductive inorganic filler is an insulating filler. Based on the mass of the immersion coolant, a mass percentage content of the base oil is in a range from 70% to 85%, a mass percentage content of the silicone oil diluent is in a range from 10% to 20%, and a mass percentage content of the thermally conductive inorganic filler is in a range from 5% to 10%.
    Type: Application
    Filed: November 17, 2023
    Publication date: February 20, 2025
    Applicant: CSG PWR GEN. (GUANGDONG) ENRGY. STR. TCH. CO. LTD
    Inventors: Bangjin LIU, Zhiqiang WANG, Chao DONG, Jin WANG, Yueli ZHOU, Jiasheng WU, Cheng PENG, Min ZHANG, Bin WU, Linwei WANG, Qihua LIN, Xiaodong ZHENG, Zheng WENG, Shaohua ZHAO, Lunsen ZOU, Guobin ZHONG, Fei YU, Jia LUO, Xuan LIU, Kaiqi XU, Chao WANG
  • Publication number: 20250062779
    Abstract: Methods, apparatus, and systems that relate to rate matching scheme design for polar coding, PAC coding, or other pre-transformed polar coding are disclosed. In one example aspect, a method for digital communication includes determining, by a first node, an output bit sequence having E bits based on an input bit sequence having K bits, wherein the output bit sequence is determined by performing a polar transform with H components and a pre-transform; wherein the polar transform is based on H polar matrices G(N0), G(N1), . . . , G(NH?0), wherein E, K, H are integers greater than 1, wherein a polar matrix G(N0) is of size Ni. The method also includes transmitting, by the first node, a signal including the output bit sequence to a second node.
    Type: Application
    Filed: October 31, 2024
    Publication date: February 20, 2025
    Inventors: Chulong LIANG, Wei ZHAO, Jin XU, Liguang LI, Guanghui YU, Jian KANG, Qiang FU
  • Patent number: 12226988
    Abstract: A sticking machine able to automatically remove films on either side of a sheet to be pasted to a workpiece includes a sheet supply component, a sheet selection component, a drive component, a first film-removing component, a second film-removing component, a carrier, and a transmission line. The sheet supply component stores sheets. The sheet selection component applies suction to the sheet. The first film-removing component tears off a first film, the second film-removing component tears off a second film on the reverse side. The transmission line carries the workpiece to the carrier. The sticking machine is fed by the sheet supply component, and after removal of the first film, the sheet selection component lays the sheet on the surface of the workpiece, then the second film-removing component tears off the second film, realizing automatic sticking of the sheet on the workpiece, improving the processing efficiency and accuracy.
    Type: Grant
    Filed: October 30, 2020
    Date of Patent: February 18, 2025
    Assignees: FU DING ELECTRONICAL TECHNOLOGY (JIASHAN) CO., LTD., FUZHUN PRECISION TOOLING (JIASHAN) CO., LTD.
    Inventors: Zhen-Lin Zhao, Min Liu, Wen-Jin Xia, Wei-Wei Wu, Wei-Ping Li, Huo-Zhong Wu
  • Publication number: 20250055595
    Abstract: Methods, apparatus, and systems that relate to Polarization-Adjusted Convolutional (PAC) coding with variable lengths are disclosed. In one example aspect, a method for digital communication includes determining, by a first node, an output bit sequence having E bits based on an input bit sequence having K bits. The output bit sequence is determined based on a transform that is applied prior to applying a Polar transform having a size of N. The transform is based on at least one index set that is a subset of a set of bit indices. The set of bit indices comprises all non-negative integers that are less than N and wherein K<N and K<E. The method also includes transmitting, by the first node, a signal including the output bit sequence to a second node.
    Type: Application
    Filed: October 24, 2024
    Publication date: February 13, 2025
    Inventors: Chulong LIANG, Jin XU, Wei ZHAO, Liguang LI, Guanghui YU, Jian KANG, Qiang FU
  • Patent number: 12222850
    Abstract: An information handling system executes test cases against a code that includes a set of functions, wherein the execution is performed at least twice using a different trace switch value. The system also identifies trace logs associated with each test case, and maps each test case to one or more functions based on the association of the trace logs with each test case.
    Type: Grant
    Filed: May 10, 2022
    Date of Patent: February 11, 2025
    Assignee: Dell Products L.P.
    Inventors: Qin Zhang, Jin Qin, Jinghui Zhang, Shuyu Zhao, Xiaoxuan Dong
  • Publication number: 20250048615
    Abstract: A 3D stacked semiconductor device, a manufacturing method therefor, and an electronic equipment are disclosed. The 3D stacked semiconductor device includes a plurality of transistors distributed in different layers and stacked along a direction perpendicular to a base substrate; a word line penetrating through the transistors of the different layers; and a plurality of protective layers corresponding to the plurality of transistors respectively; wherein each transistor includes a semiconductor layer surrounding a side wall of the word line, a gate insulation layer disposed between the side wall of the word line and the semiconductor layer, a plurality of semiconductor layers of the plurality of transistors are disposed at intervals in a direction in which the word line extends; each of the protective layers respectively surrounds and covers an outer side wall of a corresponding semiconductor layer, and two adjacent protective layers are disconnected from each other.
    Type: Application
    Filed: June 8, 2023
    Publication date: February 6, 2025
    Applicant: BEIJING SUPERSTRING ACADEMY OF MEMORY TECHNOLOGY
    Inventors: Xuezheng Ai, Xiangsheng Wang, Guilei Wang, Jin Dai, Chao Zhao, Wenhua Gui
  • Publication number: 20250042973
    Abstract: Recombinant protein of GPER is provided. The recombinant protein has the biological activity of G protein-coupled estrogen receptor.
    Type: Application
    Filed: July 30, 2024
    Publication date: February 6, 2025
    Applicant: Wuhan University
    Inventors: Jin XIANG, Ying ZHAO, Miaomiao QI, Jing REN, Yujie YAN
  • Publication number: 20250048561
    Abstract: A field programmable solder BeTA (FPSBGA) module may be utilized to assemble PCB/Substrate in any stack-up configuration. The local field programmable soldering BGA includes control system provides the necessary feedback for effective control of thermal profiles. The FPSBGA enables a control component (110) to cause the execution of the temperature application component (120) to cause a non-uniform application of specified temperature parameters to the substrate.
    Type: Application
    Filed: August 15, 2022
    Publication date: February 6, 2025
    Inventors: Vijaykumar KRITHIVASAN, Jin ZHAO, Jianjun LI
  • Publication number: 20250046674
    Abstract: A module comprising: a module substrate; a system-on-chip die coupled to the module substrate; a thermal interface material layer coupled to the system-on-chip die; a stiffener structure positioned around the system-on-chip die and coupled to the module substrate; and a lid having a first portion coupled to the thermal interface material layer, a second portion coupled to the stiffener structure and a recessed region formed around the first portion and having a reduced thickness relative to the first portion and the second portion.
    Type: Application
    Filed: August 3, 2023
    Publication date: February 6, 2025
    Inventors: Suk-Kyu Ryu, Wei Hu, Jie-Hua Zhao, Myung Jin Yim
  • Patent number: 12216974
    Abstract: A multi-scale prediction method for an ablation behavior of a hypersonic aircraft heat resistant structure, includes inputting hypersonic inflow far field boundary conditions into a macro CFD solver to perform numerical simulation of the external flow field of a hypersonic aircraft; extracting the mass fraction and temperature distribution of wall surface components; obtaining an msd.txt file and an atomic path file recording the mean square displacement data through a micro RMD solver; obtaining the ratio of mass loss rate to material density, namely, the ablation retreating rate using the MSD method and Fick's law; inputting it into a CFD solver for performing grid reconstruction and transient calculation to obtain the transient variation in the external flow field of a hypersonic aircraft along the ablation retreating of the aircraft wall surface.
    Type: Grant
    Filed: May 31, 2023
    Date of Patent: February 4, 2025
    Inventors: Zhifan Ye, Jin Zhao, Zhihui Li, Dongsheng Wen, Guice Yao
  • Patent number: 12206064
    Abstract: Methods are provided for producing a biaxially oriented nanoporous UHMWPE membrane. The method can include combining a petroleum jelly, an ultra-high-molecular-weight polyethylene (UHMWPE), and an antioxidant, forming a suspension, feeding the suspension into an extruder to produce a gel filament, pressing the gel filament to form a gel film, subjecting the gel film to an annealing temperature, and extracting the petroleum jelly from the gel film.
    Type: Grant
    Filed: November 15, 2017
    Date of Patent: January 21, 2025
    Assignee: The Hong Kong University of Science and Technology
    Inventors: Ping Gao, Tianshou Zhao, Runlai Li, Lin Zeng, Jin Li, Qiao Gu
  • Publication number: 20250021015
    Abstract: An etch bias direction is determined based on a curvature of a contour in a substrate pattern. The etch bias direction is configured to be used to enhance an accuracy of a semiconductor patterning process relative to prior patterning processes. In some embodiments, a representation of the substrate pattern is received, which includes the contour in the substrate pattern. The curvature of the contour of the substrate pattern is determined, and an etch bias direction is determined based on the curvature by considering curvatures of adjacent contour portions. A simulation model is used to determine an etch effect based on the etch bias direction for an etching process on the substrate pattern.
    Type: Application
    Filed: October 26, 2022
    Publication date: January 16, 2025
    Applicant: ASML NETHERLANDS B.V.
    Inventors: Jin CHENG, Feng CHEN, Leiwu ZHENG, Yongfa FAN, Yen-Wen LU, Jen-Shiang WANG, Ziyang MA, Dianwen ZHU, Xi CHEN, Yu ZHAO
  • Patent number: 12197330
    Abstract: The present disclosure provides a data storage system, including data cache module, data processing module, and a persistent memory. The data cache module includes an on-chip mapping data cache and an on-chip counter cache, where the mapping data cache is configured to cache mapping data, and when the free space of the mapping data cache is less than a preset threshold, the least recently used mapping data cache line will be evicted from the cache and written back to the persistent memory. The data processing module encrypts/decrypts persistent memory data by using their counters, and accesses the persistent memory blocks indicated by their corresponding mapping data. The persistent memory comprises the first and second storage regions for the latest checkpoint data and modified working data in the current checkpoint interval respectively.
    Type: Grant
    Filed: September 19, 2023
    Date of Patent: January 14, 2025
    Assignees: ZHEJIANG LAB, Huazhong University of Science and Technology
    Inventors: Zhan Zhang, Yu Zhang, Jin Zhao, Haifei Wu
  • Patent number: 12196855
    Abstract: The present disclosure provides a distance detection device. The distance detection device includes a light source configured to emit pulse light beams sequentially; and a scanning module including a first optical module, a second optical module, and drivers. The first optical module and the second optical module are sequentially positioned on an optical path of the light beams emitted by the light source, the drivers drive the first optical module and the second optical module to move to sequentially project the light beams emitted by the light source to different directions and form a strip-shaped scanning range after being emitted from the scanning module.
    Type: Grant
    Filed: March 29, 2021
    Date of Patent: January 14, 2025
    Assignee: SZ DJI TECHNOLOGY CO., LTD.
    Inventors: Huai Huang, Jin Zhao, Xiaoping Hong
  • Publication number: 20250008158
    Abstract: A size of a transform block is identified. A transform type for the transform block is identified. The transform type includes a horizontal transform type and a vertical transform type. Identifying the transform type includes determining whether the size of the transform block is below a predefined block size; and, in response to determining that the size is below the predefined block size, selecting a default transform type for each of the horizontal transform type and the vertical transform type. The transform type is then applied to the transform block. The default transform type can be the discrete cosine transform (DCT).
    Type: Application
    Filed: June 25, 2024
    Publication date: January 2, 2025
    Inventors: Jin Zhao, In Suk Chong
  • Publication number: 20240385449
    Abstract: An optical combiner and a display device are provided. The optical combiner includes a light-transmitting structure and a waveguide structure in the light-transmitting structure. The waveguide structure includes a first dielectric layer, a waveguide plate, and a second dielectric layer arranged in sequence. The waveguide plate includes a coupling-out region, wherein the refractive index of the first dielectric layer and the refractive index of the second dielectric layer are both less than the refractive index of the waveguide plate. Since the refractive index of the first dielectric layer and the refractive index of the second dielectric layer are both less than the refractive index of the waveguide plate, light beams propagating in the waveguide plate undergo totally reflection during propagation and cannot be refracted into the first dielectric layer and the second dielectric layer.
    Type: Application
    Filed: July 30, 2024
    Publication date: November 21, 2024
    Applicant: ZHUHAI MOJIE TECHNOLOGY CO., LTD.
    Inventors: Jian GUAN, Xing ZHOU, Fuyang LAN, Song XU, Jin ZHAO
  • Publication number: 20240385437
    Abstract: A stacked grating and an AR display device are provided. The stacked grating includes at least two grating layers stacked from bottom to top sequentially. Grating grooves are arranged in each of the grating layers in a distribution pattern. The distribution patterns of the grating grooves in a horizontal direction are distinct from each other for each two adjacent ones of the grating layers, and the distribution patterns of the grating grooves of two grating layers arranged with one grating layer between them in the horizontal direction are the same. As such, the stacked grating is equivalent to a bulk grating, and the transmission/reflection selectivity of grating diffraction is improved, thus reducing privacy disclosure and increasing the energy utilization rate.
    Type: Application
    Filed: July 30, 2024
    Publication date: November 21, 2024
    Applicant: ZHUHAI MOJIE TECHNOLOGY CO., LTD.
    Inventors: Chendi SHAO, Fuyang LAN, Jin ZHAO
  • Publication number: 20240370070
    Abstract: Aspects of this disclosure relate to power delivery to chips in an array. An array of power conversion paths can be positioned vertically relative to the chips of the array. A power conversion path can convert a high voltage, low current signal to a low voltage, high current. The power conversion path can include a first power conversion stage and a second power conversion stage. The power conversion path can be implemented in a power supply module, for example.
    Type: Application
    Filed: August 15, 2022
    Publication date: November 7, 2024
    Inventors: Jin Zhao, Shishuang Sun, Yang Sun, Vijaykumar Krithivasan, William Chang, Jianjun Li