Patents by Inventor Jinbang Tang

Jinbang Tang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250096165
    Abstract: A wafer-scale die packaging device is fabricated by providing a high-k glass carrier substrate having a ceramic region which includes a defined waveguide area and extends to a defined die attach area, and then forming, on a first glass carrier substrate surface, a differential waveguide launcher having a pair of signal lines connected to a radiating element that is positioned adjacent to an air cavity and surrounded by a patterned array of conductors disposed over the ceramic region in a waveguide conductor ring. After attaching a die to the glass carrier substrate to make electrical connection to the differential waveguide launcher, a molding compound is formed to cover the die, differential waveguide launcher, and air cavity, and an array of conductors is formed in the molding compound to define a first waveguide interface perimeter surrounding a first waveguide interface interior.
    Type: Application
    Filed: November 18, 2024
    Publication date: March 20, 2025
    Inventor: Jinbang Tang
  • Patent number: 12176307
    Abstract: A wafer-scale die packaging device is fabricated by providing a high-k glass carrier substrate having a ceramic region which includes a defined waveguide area and extends to a defined die attach area, and then forming, on a first glass carrier substrate surface, a differential waveguide launcher having a pair of signal lines connected to a radiating element that is positioned adjacent to an air cavity and surrounded by a patterned array of conductors disposed over the ceramic region in a waveguide conductor ring. After attaching a die to the glass carrier substrate to make electrical connection to the differential waveguide launcher, a molding compound is formed to cover the die, differential waveguide launcher, and air cavity, and an array of conductors is formed in the molding compound to define a first waveguide interface perimeter surrounding a first waveguide interface interior.
    Type: Grant
    Filed: December 3, 2021
    Date of Patent: December 24, 2024
    Assignee: NXP USA, Inc.
    Inventor: Jinbang Tang
  • Publication number: 20240243529
    Abstract: An electrical connector port disposed within a mobile device such as a smart phone is provided with a wireless antenna coupled to the electrical connector port which. A housing of the connector port, together with the antenna, defines a directional antenna gain pattern enabling the wireless antenna to be used for directional communication between the mobile device and another device.
    Type: Application
    Filed: January 12, 2023
    Publication date: July 18, 2024
    Inventor: Jinbang Tang
  • Patent number: 12027485
    Abstract: A method of forming a packaged semiconductor device includes attaching a backside surface of a semiconductor die to a major surface of a package substrate. A first conductive connector is formed over a portion of an active surface of the semiconductor die and a portion of the major surface of the package substrate. A first conductive connection between a first bond pad of the semiconductor die and a first substrate pad of the package substrate is formed by way of the first conductive connector. A bond wire connects a second bond pad of the semiconductor die to a second substrate pad of the package substrate. The first bond pad located between the second bond pad and an edge of the semiconductor die.
    Type: Grant
    Filed: August 29, 2022
    Date of Patent: July 2, 2024
    Assignee: NXP USA, Inc.
    Inventor: Jinbang Tang
  • Patent number: 11862584
    Abstract: A wafer-scale die packaging device is fabricated by providing a high-k glass carrier substrate having a ceramic region which includes a defined waveguide area and extends to a defined die attach area, and then forming, on a first glass carrier substrate surface, a differential waveguide launcher having a pair of signal lines connected to a radiating element that is positioned adjacent to an air cavity and surrounded by a patterned array of conductors disposed over the ceramic region in a waveguide conductor ring. After attaching a die to the glass carrier substrate to make electrical connection to the differential waveguide launcher, a molding compound is formed to cover the die, differential waveguide launcher, and air cavity, and an array of conductors is formed in the molding compound to define a first waveguide interface perimeter surrounding a first waveguide interface interior.
    Type: Grant
    Filed: December 29, 2021
    Date of Patent: January 2, 2024
    Assignee: NXP USA, INC.
    Inventor: Jinbang Tang
  • Publication number: 20230207498
    Abstract: A wafer-scale die packaging device is fabricated by providing a high-k glass carrier substrate having a ceramic region which includes a defined waveguide area and extends to a defined die attach area, and then forming, on a first glass carrier substrate surface, a differential waveguide launcher having a pair of signal lines connected to a radiating element that is positioned adjacent to an air cavity and surrounded by a patterned array of conductors disposed over the ceramic region in a waveguide conductor ring. After attaching a die to the glass carrier substrate to make electrical connection to the differential waveguide launcher, a molding compound is formed to cover the die, differential waveguide launcher, and air cavity, and an array of conductors is formed in the molding compound to define a first waveguide interface perimeter surrounding a first waveguide interface interior.
    Type: Application
    Filed: December 29, 2021
    Publication date: June 29, 2023
    Applicant: NXP USA, Inc.
    Inventor: Jinbang Tang
  • Publication number: 20230178500
    Abstract: A wafer-scale die packaging device is fabricated by providing a high-k glass carrier substrate having a ceramic region which includes a defined waveguide area and extends to a defined die attach area, and then forming, on a first glass carrier substrate surface, a differential waveguide launcher having a pair of signal lines connected to a radiating element that is positioned adjacent to an air cavity and surrounded by a patterned array of conductors disposed over the ceramic region in a waveguide conductor ring. After attaching a die to the glass carrier substrate to make electrical connection to the differential waveguide launcher, a molding compound is formed to cover the die, differential waveguide launcher, and air cavity, and an array of conductors is formed in the molding compound to define a first waveguide interface perimeter surrounding a first waveguide interface interior.
    Type: Application
    Filed: December 3, 2021
    Publication date: June 8, 2023
    Applicant: NXP USA, Inc.
    Inventor: Jinbang Tang
  • Patent number: 11557565
    Abstract: A method of forming a semiconductor device includes attaching a semiconductor die to a flag of a leadframe and forming a conductive connector over a portion of the semiconductor die and a portion of the flag. A conductive connection between a first bond pad of the semiconductor die and the flag is formed by way of the conductive connector. A second bond pad of the semiconductor die is connected to a conductive lead of the plurality by way of a bond wire.
    Type: Grant
    Filed: October 6, 2020
    Date of Patent: January 17, 2023
    Assignee: NXP USA, INC.
    Inventor: Jinbang Tang
  • Publication number: 20220415844
    Abstract: A method of forming a packaged semiconductor device includes attaching a backside surface of a semiconductor die to a major surface of a package substrate. A first conductive connector is formed over a portion of an active surface of the semiconductor die and a portion of the major surface of the package substrate. A first conductive connection between a first bond pad of the semiconductor die and a first substrate pad of the package substrate is formed by way of the first conductive connector. A bond wire connects a second bond pad of the semiconductor die to a second substrate pad of the package substrate. The first bond pad located between the second bond pad and an edge of the semiconductor die.
    Type: Application
    Filed: August 29, 2022
    Publication date: December 29, 2022
    Inventor: Jinbang Tang
  • Patent number: 11502054
    Abstract: A method of forming a packaged semiconductor device includes attaching a backside surface of a semiconductor die to a major surface of a package substrate. A first conductive connector is formed over a portion of an active surface of the semiconductor die and a portion of the major surface of the package substrate. A first conductive connection between a first bond pad of the semiconductor die and a first substrate pad of the package substrate is formed by way of the first conductive connector. A bond wire connects a second bond pad of the semiconductor die to a second substrate pad of the package substrate. The first bond pad located between the second bond pad and an edge of the semiconductor die.
    Type: Grant
    Filed: November 11, 2020
    Date of Patent: November 15, 2022
    Assignee: NXP USA, INC.
    Inventor: Jinbang Tang
  • Patent number: 11462505
    Abstract: A method of forming a packaged semiconductor device includes attaching a backside surface of a semiconductor die to a major surface of a package substrate. A first conductive connector is formed over a portion of an active surface of the semiconductor die and a portion of the major surface of the package substrate. A first conductive connection between a first bond pad of the semiconductor die and a first substrate pad of the package substrate is formed by way of the first conductive connector. A bond wire connects a second bond pad of the semiconductor die to a second substrate pad of the package substrate. The first bond pad located between the second bond pad and an edge of the semiconductor die.
    Type: Grant
    Filed: November 11, 2020
    Date of Patent: October 4, 2022
    Assignee: NXP USA, INC.
    Inventor: Jinbang Tang
  • Patent number: 11427464
    Abstract: Embodiments of a packaged electronic device and method of fabricating such a device are provided, where the packaged electronic device includes: a pressure sensor die having a diaphragm on a front side; an encapsulant material that encapsulates the pressure sensor die, wherein the front side of the pressure sensor die is exposed at a first major surface of the encapsulant material; an interconnect structure formed over the front side of the pressure sensor die and the first major surface of the encapsulant material, wherein an opening through the interconnect structure is generally aligned to the diaphragm; and a cap attached to an outer dielectric layer of the interconnect structure, the cap having a vent hole generally aligned with the opening through the interconnect structure.
    Type: Grant
    Filed: September 28, 2020
    Date of Patent: August 30, 2022
    Assignee: NXP USA, Inc.
    Inventors: Weng Foong Yap, Jinbang Tang, Sandeep Shantaram
  • Publication number: 20220149000
    Abstract: A method of forming a packaged semiconductor device includes attaching a backside surface of a semiconductor die to a major surface of a package substrate. A first conductive connector is formed over a portion of an active surface of the semiconductor die and a portion of the major surface of the package substrate. A first conductive connection between a first bond pad of the semiconductor die and a first substrate pad of the package substrate is formed by way of the first conductive connector. A bond wire connects a second bond pad of the semiconductor die to a second substrate pad of the package substrate. The first bond pad located between the second bond pad and an edge of the semiconductor die.
    Type: Application
    Filed: November 11, 2020
    Publication date: May 12, 2022
    Inventor: Jinbang Tang
  • Publication number: 20220108973
    Abstract: A method of forming a semiconductor device includes attaching a semiconductor die to a flag of a leadframe and forming a conductive connector over a portion of the semiconductor die and a portion of the flag. A conductive connection between a first bond pad of the semiconductor die and the flag is formed by way of the conductive connector. A second bond pad of the semiconductor die is connected to a conductive lead of the plurality by way of a bond wire.
    Type: Application
    Filed: October 6, 2020
    Publication date: April 7, 2022
    Inventor: Jinbang Tang
  • Patent number: 11121467
    Abstract: A semiconductor device package is provided that incorporates an antenna structure within the package through use of three-dimensional additive manufacturing processes. Embodiments can provide semiconductor device packages that are thinner than traditional device packages by depositing specific metal and dielectric layers within the package in desired positions with precision that cannot be provided by other manufacturing techniques. Further, embodiments can provide antenna geometries and orientations that cannot be provided by other manufacturing techniques.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: September 14, 2021
    Assignee: NXP USA, INC.
    Inventors: Jinbang Tang, Zhiwei Gong, Betty Hill-Shan Yeung, Michael B. Vincent
  • Patent number: 11101542
    Abstract: A semiconductor device package having at least one integrated circuit (IC) die, at least two antennas oriented in at least two different directions, and a combiner/divider structure connecting the at least two antennas to the at least one IC die and configured to combine/divide signals transmitted between the at least two antennas and the at least one IC die. The package may be fabricated using an additive manufacturing process (i.e., 3D printing). In certain embodiments, the package is an integrated radio package having a multi-directional antenna array.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: August 24, 2021
    Assignee: NXP USA, INC.
    Inventor: Jinbang Tang
  • Publication number: 20210159584
    Abstract: A semiconductor device package having at least one integrated circuit (IC) die, at least two antennas oriented in at least two different directions, and a combiner/divider structure connecting the at least two antennas to the at least one IC die and configured to combine/divide signals transmitted between the at least two antennas and the at least one IC die. The package may be fabricated using an additive manufacturing process (i.e., 3D printing). In certain embodiments, the package is an integrated radio package having a multi-directional antenna array.
    Type: Application
    Filed: November 26, 2019
    Publication date: May 27, 2021
    Inventor: Jinbang Tang
  • Publication number: 20210009405
    Abstract: Embodiments of a packaged electronic device and method of fabricating such a device are provided, where the packaged electronic device includes: a pressure sensor die having a diaphragm on a front side; an encapsulant material that encapsulates the pressure sensor die, wherein the front side of the pressure sensor die is exposed at a first major surface of the encapsulant material; an interconnect structure formed over the front side of the pressure sensor die and the first major surface of the encapsulant material, wherein an opening through the interconnect structure is generally aligned to the diaphragm; and a cap attached to an outer dielectric layer of the interconnect structure, the cap having a vent hole generally aligned with the opening through the interconnect structure.
    Type: Application
    Filed: September 28, 2020
    Publication date: January 14, 2021
    Inventors: Weng Foong Yap, Jinbang Tang, Sandeep Shantaram
  • Publication number: 20200403314
    Abstract: A semiconductor device package is provided that incorporates an antenna structure within the package through use of three-dimensional additive manufacturing processes. Embodiments can provide semiconductor device packages that are thinner than traditional device packages by depositing specific metal and dielectric layers within the package in desired positions with precision that cannot be provided by other manufacturing techniques. Further, embodiments can provide antenna geometries and orientations that cannot be provided by other manufacturing techniques.
    Type: Application
    Filed: June 24, 2019
    Publication date: December 24, 2020
    Applicant: NXP USA, Inc.
    Inventors: Jinbang Tang, Zhiwei Gong, Betty Hill-Shan Yeung, Michael B. Vincent
  • Patent number: 10822224
    Abstract: Embodiments of a packaged electronic device and method of fabricating such a device are provided, where the packaged electronic device includes: a pressure sensor die having a diaphragm on a front side; an encapsulant material that encapsulates the pressure sensor die, wherein the front side of the pressure sensor die is exposed at a first major surface of the encapsulant material; an interconnect structure formed over the front side of the pressure sensor die and the first major surface of the encapsulant material, wherein an opening through the interconnect structure is generally aligned to the diaphragm; and a cap attached to an outer dielectric layer of the interconnect structure, the cap having a vent hole generally aligned with the opening through the interconnect structure.
    Type: Grant
    Filed: October 18, 2017
    Date of Patent: November 3, 2020
    Assignee: NXP USA, Inc.
    Inventors: Weng Foong Yap, Jinbang Tang, Sandeep Shantaram