Patents by Inventor Jinbang Tang
Jinbang Tang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11862584Abstract: A wafer-scale die packaging device is fabricated by providing a high-k glass carrier substrate having a ceramic region which includes a defined waveguide area and extends to a defined die attach area, and then forming, on a first glass carrier substrate surface, a differential waveguide launcher having a pair of signal lines connected to a radiating element that is positioned adjacent to an air cavity and surrounded by a patterned array of conductors disposed over the ceramic region in a waveguide conductor ring. After attaching a die to the glass carrier substrate to make electrical connection to the differential waveguide launcher, a molding compound is formed to cover the die, differential waveguide launcher, and air cavity, and an array of conductors is formed in the molding compound to define a first waveguide interface perimeter surrounding a first waveguide interface interior.Type: GrantFiled: December 29, 2021Date of Patent: January 2, 2024Assignee: NXP USA, INC.Inventor: Jinbang Tang
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Publication number: 20230207498Abstract: A wafer-scale die packaging device is fabricated by providing a high-k glass carrier substrate having a ceramic region which includes a defined waveguide area and extends to a defined die attach area, and then forming, on a first glass carrier substrate surface, a differential waveguide launcher having a pair of signal lines connected to a radiating element that is positioned adjacent to an air cavity and surrounded by a patterned array of conductors disposed over the ceramic region in a waveguide conductor ring. After attaching a die to the glass carrier substrate to make electrical connection to the differential waveguide launcher, a molding compound is formed to cover the die, differential waveguide launcher, and air cavity, and an array of conductors is formed in the molding compound to define a first waveguide interface perimeter surrounding a first waveguide interface interior.Type: ApplicationFiled: December 29, 2021Publication date: June 29, 2023Applicant: NXP USA, Inc.Inventor: Jinbang Tang
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Publication number: 20230178500Abstract: A wafer-scale die packaging device is fabricated by providing a high-k glass carrier substrate having a ceramic region which includes a defined waveguide area and extends to a defined die attach area, and then forming, on a first glass carrier substrate surface, a differential waveguide launcher having a pair of signal lines connected to a radiating element that is positioned adjacent to an air cavity and surrounded by a patterned array of conductors disposed over the ceramic region in a waveguide conductor ring. After attaching a die to the glass carrier substrate to make electrical connection to the differential waveguide launcher, a molding compound is formed to cover the die, differential waveguide launcher, and air cavity, and an array of conductors is formed in the molding compound to define a first waveguide interface perimeter surrounding a first waveguide interface interior.Type: ApplicationFiled: December 3, 2021Publication date: June 8, 2023Applicant: NXP USA, Inc.Inventor: Jinbang Tang
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Patent number: 11557565Abstract: A method of forming a semiconductor device includes attaching a semiconductor die to a flag of a leadframe and forming a conductive connector over a portion of the semiconductor die and a portion of the flag. A conductive connection between a first bond pad of the semiconductor die and the flag is formed by way of the conductive connector. A second bond pad of the semiconductor die is connected to a conductive lead of the plurality by way of a bond wire.Type: GrantFiled: October 6, 2020Date of Patent: January 17, 2023Assignee: NXP USA, INC.Inventor: Jinbang Tang
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Publication number: 20220415844Abstract: A method of forming a packaged semiconductor device includes attaching a backside surface of a semiconductor die to a major surface of a package substrate. A first conductive connector is formed over a portion of an active surface of the semiconductor die and a portion of the major surface of the package substrate. A first conductive connection between a first bond pad of the semiconductor die and a first substrate pad of the package substrate is formed by way of the first conductive connector. A bond wire connects a second bond pad of the semiconductor die to a second substrate pad of the package substrate. The first bond pad located between the second bond pad and an edge of the semiconductor die.Type: ApplicationFiled: August 29, 2022Publication date: December 29, 2022Inventor: Jinbang Tang
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Patent number: 11502054Abstract: A method of forming a packaged semiconductor device includes attaching a backside surface of a semiconductor die to a major surface of a package substrate. A first conductive connector is formed over a portion of an active surface of the semiconductor die and a portion of the major surface of the package substrate. A first conductive connection between a first bond pad of the semiconductor die and a first substrate pad of the package substrate is formed by way of the first conductive connector. A bond wire connects a second bond pad of the semiconductor die to a second substrate pad of the package substrate. The first bond pad located between the second bond pad and an edge of the semiconductor die.Type: GrantFiled: November 11, 2020Date of Patent: November 15, 2022Assignee: NXP USA, INC.Inventor: Jinbang Tang
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Patent number: 11462505Abstract: A method of forming a packaged semiconductor device includes attaching a backside surface of a semiconductor die to a major surface of a package substrate. A first conductive connector is formed over a portion of an active surface of the semiconductor die and a portion of the major surface of the package substrate. A first conductive connection between a first bond pad of the semiconductor die and a first substrate pad of the package substrate is formed by way of the first conductive connector. A bond wire connects a second bond pad of the semiconductor die to a second substrate pad of the package substrate. The first bond pad located between the second bond pad and an edge of the semiconductor die.Type: GrantFiled: November 11, 2020Date of Patent: October 4, 2022Assignee: NXP USA, INC.Inventor: Jinbang Tang
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Patent number: 11427464Abstract: Embodiments of a packaged electronic device and method of fabricating such a device are provided, where the packaged electronic device includes: a pressure sensor die having a diaphragm on a front side; an encapsulant material that encapsulates the pressure sensor die, wherein the front side of the pressure sensor die is exposed at a first major surface of the encapsulant material; an interconnect structure formed over the front side of the pressure sensor die and the first major surface of the encapsulant material, wherein an opening through the interconnect structure is generally aligned to the diaphragm; and a cap attached to an outer dielectric layer of the interconnect structure, the cap having a vent hole generally aligned with the opening through the interconnect structure.Type: GrantFiled: September 28, 2020Date of Patent: August 30, 2022Assignee: NXP USA, Inc.Inventors: Weng Foong Yap, Jinbang Tang, Sandeep Shantaram
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Publication number: 20220149000Abstract: A method of forming a packaged semiconductor device includes attaching a backside surface of a semiconductor die to a major surface of a package substrate. A first conductive connector is formed over a portion of an active surface of the semiconductor die and a portion of the major surface of the package substrate. A first conductive connection between a first bond pad of the semiconductor die and a first substrate pad of the package substrate is formed by way of the first conductive connector. A bond wire connects a second bond pad of the semiconductor die to a second substrate pad of the package substrate. The first bond pad located between the second bond pad and an edge of the semiconductor die.Type: ApplicationFiled: November 11, 2020Publication date: May 12, 2022Inventor: Jinbang Tang
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Publication number: 20220108973Abstract: A method of forming a semiconductor device includes attaching a semiconductor die to a flag of a leadframe and forming a conductive connector over a portion of the semiconductor die and a portion of the flag. A conductive connection between a first bond pad of the semiconductor die and the flag is formed by way of the conductive connector. A second bond pad of the semiconductor die is connected to a conductive lead of the plurality by way of a bond wire.Type: ApplicationFiled: October 6, 2020Publication date: April 7, 2022Inventor: Jinbang Tang
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Patent number: 11121467Abstract: A semiconductor device package is provided that incorporates an antenna structure within the package through use of three-dimensional additive manufacturing processes. Embodiments can provide semiconductor device packages that are thinner than traditional device packages by depositing specific metal and dielectric layers within the package in desired positions with precision that cannot be provided by other manufacturing techniques. Further, embodiments can provide antenna geometries and orientations that cannot be provided by other manufacturing techniques.Type: GrantFiled: June 24, 2019Date of Patent: September 14, 2021Assignee: NXP USA, INC.Inventors: Jinbang Tang, Zhiwei Gong, Betty Hill-Shan Yeung, Michael B. Vincent
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Patent number: 11101542Abstract: A semiconductor device package having at least one integrated circuit (IC) die, at least two antennas oriented in at least two different directions, and a combiner/divider structure connecting the at least two antennas to the at least one IC die and configured to combine/divide signals transmitted between the at least two antennas and the at least one IC die. The package may be fabricated using an additive manufacturing process (i.e., 3D printing). In certain embodiments, the package is an integrated radio package having a multi-directional antenna array.Type: GrantFiled: November 26, 2019Date of Patent: August 24, 2021Assignee: NXP USA, INC.Inventor: Jinbang Tang
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Publication number: 20210159584Abstract: A semiconductor device package having at least one integrated circuit (IC) die, at least two antennas oriented in at least two different directions, and a combiner/divider structure connecting the at least two antennas to the at least one IC die and configured to combine/divide signals transmitted between the at least two antennas and the at least one IC die. The package may be fabricated using an additive manufacturing process (i.e., 3D printing). In certain embodiments, the package is an integrated radio package having a multi-directional antenna array.Type: ApplicationFiled: November 26, 2019Publication date: May 27, 2021Inventor: Jinbang Tang
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Publication number: 20210009405Abstract: Embodiments of a packaged electronic device and method of fabricating such a device are provided, where the packaged electronic device includes: a pressure sensor die having a diaphragm on a front side; an encapsulant material that encapsulates the pressure sensor die, wherein the front side of the pressure sensor die is exposed at a first major surface of the encapsulant material; an interconnect structure formed over the front side of the pressure sensor die and the first major surface of the encapsulant material, wherein an opening through the interconnect structure is generally aligned to the diaphragm; and a cap attached to an outer dielectric layer of the interconnect structure, the cap having a vent hole generally aligned with the opening through the interconnect structure.Type: ApplicationFiled: September 28, 2020Publication date: January 14, 2021Inventors: Weng Foong Yap, Jinbang Tang, Sandeep Shantaram
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Publication number: 20200403314Abstract: A semiconductor device package is provided that incorporates an antenna structure within the package through use of three-dimensional additive manufacturing processes. Embodiments can provide semiconductor device packages that are thinner than traditional device packages by depositing specific metal and dielectric layers within the package in desired positions with precision that cannot be provided by other manufacturing techniques. Further, embodiments can provide antenna geometries and orientations that cannot be provided by other manufacturing techniques.Type: ApplicationFiled: June 24, 2019Publication date: December 24, 2020Applicant: NXP USA, Inc.Inventors: Jinbang Tang, Zhiwei Gong, Betty Hill-Shan Yeung, Michael B. Vincent
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Patent number: 10822224Abstract: Embodiments of a packaged electronic device and method of fabricating such a device are provided, where the packaged electronic device includes: a pressure sensor die having a diaphragm on a front side; an encapsulant material that encapsulates the pressure sensor die, wherein the front side of the pressure sensor die is exposed at a first major surface of the encapsulant material; an interconnect structure formed over the front side of the pressure sensor die and the first major surface of the encapsulant material, wherein an opening through the interconnect structure is generally aligned to the diaphragm; and a cap attached to an outer dielectric layer of the interconnect structure, the cap having a vent hole generally aligned with the opening through the interconnect structure.Type: GrantFiled: October 18, 2017Date of Patent: November 3, 2020Assignee: NXP USA, Inc.Inventors: Weng Foong Yap, Jinbang Tang, Sandeep Shantaram
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Patent number: 10319689Abstract: Embodiments are provided for a packaged semiconductor device that includes a package substrate that in turn includes an embedded die configured to process a radio frequency (RF) signal; a printed circuit board (PCB) attached to a front side of the package substrate, where the PCB includes a cavity; and an antenna enabling element attached to the front side of the package substrate within the cavity, the antenna enabling element configured to convey the RF signal through the cavity.Type: GrantFiled: December 1, 2015Date of Patent: June 11, 2019Assignee: NXP USA, Inc.Inventors: Weng Foong Yap, Jinbang Tang
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Publication number: 20190112180Abstract: Embodiments of a packaged electronic device and method of fabricating such a device are provided, where the packaged electronic device includes: a pressure sensor die having a diaphragm on a front side; an encapsulant material that encapsulates the pressure sensor die, wherein the front side of the pressure sensor die is exposed at a first major surface of the encapsulant material; an interconnect structure formed over the front side of the pressure sensor die and the first major surface of the encapsulant material, wherein an opening through the interconnect structure is generally aligned to the diaphragm; and a cap attached to an outer dielectric layer of the interconnect structure, the cap having a vent hole generally aligned with the opening through the interconnect structure.Type: ApplicationFiled: October 18, 2017Publication date: April 18, 2019Inventors: Weng Foong YAP, Jinbang Tang, Sandeep Shantaram
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Patent number: 10134660Abstract: A semiconductor device includes a lead frame site including a die attach region and corrugated metal leads around the die attach region. Each of the corrugated metal leads includes two or more corrugations. Each of the two or more corrugations includes a first flat horizontal portion, a first vertical portion with a first end directly adjacent and connected to a first end of the first flat horizontal portion, a second flat horizontal portion with a first end directly adjacent and connected to a second end of the first vertical portion, and a second vertical portion with a first end directly adjacent and connected to a second end of the second flat horizontal portion. The first flat horizontal portion is in a different plane than the second flat horizontal portion.Type: GrantFiled: March 23, 2017Date of Patent: November 20, 2018Assignee: NXP USA, Inc.Inventors: Jinbang Tang, Aruna Manoharan, Norman Lee Owens, Gary Carl Johnson
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Publication number: 20180277464Abstract: A semiconductor device includes a lead frame site including a die attach region and corrugated metal leads around the die attach region. Each of the corrugated metal leads includes two or more corrugations. Each of the two or more corrugations includes a first flat horizontal portion, a first vertical portion with a first end directly adjacent and connected to a first end of the first flat horizontal portion, a second flat horizontal portion with a first end directly adjacent and connected to a second end of the first vertical portion, and a second vertical portion with a first end directly adjacent and connected to a second end of the second flat horizontal portion. The first flat horizontal portion is in a different plane than the second flat horizontal portion.Type: ApplicationFiled: March 23, 2017Publication date: September 27, 2018Inventors: JINBANG TANG, Aruna Manoharan, Norman Lee Owens, Gary Carl Johnson