Patents by Inventor Jinbang Tang
Jinbang Tang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20120223325Abstract: A microelectronic assembly and a method for forming a microelectronic assembly are provided. A semiconductor substrate is provided. The semiconductor substrate has first and second opposing sides and first and second portions. A tuning depression is formed on the second opposing side and the second portion of the semiconductor substrate. A radio frequency conductor is formed on the first opposing side of the first semiconductor substrate. The radio frequency conductor has a first end on the first portion of the first semiconductor substrate and a second end on the second portion of the first semiconductor substrate. A microelectronic die having an integrated circuit formed therein is attached to the first opposing side and the first portion of the semiconductor substrate such that the integrated circuit is electrically connected to the first end of the radio frequency conductor.Type: ApplicationFiled: March 30, 2012Publication date: September 6, 2012Applicant: FREESCALE SEMICONDUCTOR, INC.Inventor: Jinbang Tang
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Patent number: 8168464Abstract: A microelectronic assembly and a method for forming a microelectronic assembly are provided. A semiconductor substrate (22) is provided. The semiconductor substrate (22) has first and second opposing sides (24, 26) and first and second portions (28, 30). A tuning depression (32) is formed on the second opposing side and the second portion of the semiconductor substrate. A radio frequency conductor (34) is formed on the first opposing side (24) of the first semiconductor substrate. The radio frequency conductor (34) has a first end (46) on the first portion (28) of the first semiconductor substrate (22) and a second end (48) on the second portion (30) of the first semiconductor substrate (22). A microelectronic die (78) having an integrated circuit formed therein is attached to the first opposing side (24) and the first portion (28) of the semiconductor substrate (22) such that the integrated circuit is electrically connected to the first end (46) of the radio frequency conductor (34).Type: GrantFiled: January 25, 2010Date of Patent: May 1, 2012Assignee: Freescale Semiconductor, Inc.Inventor: Jinbang Tang
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Patent number: 8097494Abstract: Electromagnetic shielding for an integrated circuit packaged device. The method includes forming shielding structures by forming openings in an encapsulated structure. The openings are filled with conductive material that surrounds at least one die. The encapsulated structure may include a plurality of integrated circuit die. A layered redistribution structure is formed on one side of the encapsulated structure.Type: GrantFiled: January 15, 2010Date of Patent: January 17, 2012Assignee: Freescale Semiconductor, Inc.Inventors: Jinbang Tang, Darrel Frear, Jong-Kai Lin, Marc A. Mangrum, Robert E. Booth, Lawrence N. Herr, Kenneth R. Burch
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Patent number: 8093700Abstract: A module, which in one embodiment may be a packaged millimeter waver module, includes a semiconductor lid portion; a packaging portion attached to the lid portion, wherein the packaging portion comprises a plurality of vias, a carrier portion, wherein a first semiconductor die is attached to the carrier portion, the packaging portion is attached to the carrier portion so that the packaging portion is over the carrier portion and the semiconductor die is within an opening in the packaging portion, and the lid portion and the carrier portion form an first air gap around the first semiconductor device.Type: GrantFiled: December 16, 2008Date of Patent: January 10, 2012Assignee: Freescale Semiconductor, Inc.Inventor: Jinbang Tang
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Publication number: 20110230014Abstract: A method of packaging an electronic device includes providing a patterned dielectric layer with an area sized to receive a first die, and another area sized to receive a second die, placing the first and second dies within the first and second areas, encapsulating the dies with an encapsulating material that has a different composition from the dielectric layer, forming a first signal line between the dies, forming a second signal line to the first die, and forming an additional signal line to the first die. The dielectric layer is disposed between the first signal line and the encapsulating material, the electronic device transmits a signal in an approximate range of 1 GHz to 100 GHz along the second signal line, and a signal that does not exceed approximately 900 MHz along the additional signal line.Type: ApplicationFiled: June 2, 2011Publication date: September 22, 2011Applicant: FREESCALE SEMICONDUCTOR, INC.Inventor: Jinbang Tang
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Publication number: 20110208467Abstract: An embodiment of a calibration standard includes a substrate, a set of conductive structures fabricated on the substrate, and a conductive end structure fabricated on the substrate. The set of conductive structures include an inner conductive structure, a first outer conductive structure positioned to one side of the inner conductive structure, and a second outer conductive structure positioned to an opposite side of the inner conductive structure. The inner and outer conductive structures are aligned in parallel with each other along offset principal axes of the inner and outer conductive structures. The conductive end structure is electrically connected between an end of the first outer conductive structure and an end of the second outer conductive structure, and the conductive end structure is spatially separated from an end of the inner conductive structure at the surface of the substrate.Type: ApplicationFiled: February 23, 2010Publication date: August 25, 2011Applicant: Freescale Semiconductor, Inc.Inventor: Jinbang Tang
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Patent number: 8004068Abstract: Embodiments include shielded multi-layer packages for use with multi-chip modules and the like. A substrate (102) (e.g., chip carrier) has an adhesive layer (104), where electronic components (106, 108) are attached. An insulating layer (110) is formed over the plurality of electronic components, and a conductive encapsulant structure (115) is formed over the insulating layer. The adhesive layer is detached from the electronic components, and multi-layer circuitry (140) is formed over, and in electrical communication with, the plurality of electronic components. A shielding via (150) is formed through the multilayer circuitry such that it contacts the conductive encapsulant.Type: GrantFiled: October 27, 2009Date of Patent: August 23, 2011Assignee: Freescale Semiconductor, Inc.Inventors: Jinbang Tang, Jong-Kai Lin
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Publication number: 20110180917Abstract: A microelectronic assembly and a method for forming a microelectronic assembly are provided. A semiconductor substrate (22) is provided. The semiconductor substrate (22) has first and second opposing sides (24, 26) and first and second portions (28, 30). A tuning depression (32) is formed on the second opposing side and the second portion of the semiconductor substrate. A radio frequency conductor (34) is formed on the first opposing side (24) of the first semiconductor substrate. The radio frequency conductor (34) has a first end (46) on the first portion (28) of the first semiconductor substrate (22) and a second end (48) on the second portion (30) of the first semiconductor substrate (22). A microelectronic die (78) having an integrated circuit formed therein is attached to the first opposing side (24) and the first portion (28) of the semiconductor substrate (22) such that the integrated circuit is electrically connected to the first end (46) of the radio frequency conductor (34).Type: ApplicationFiled: January 25, 2010Publication date: July 28, 2011Applicant: FREESCALE SEMICONDUCTOR, INC.Inventor: Jinbang Tang
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Publication number: 20110181488Abstract: An electronic device module as described herein includes an electronic device package having device contacts. The electronic device package is fixed within encapsulating material, along with an electrically conductive ground layer. The ground layer has a device opening in which the electronic device package resides, and the ground layer also has an antenna opening spaced apart from the device opening. The device contacts and one side of the ground layer correspond to a first surface, and a patch antenna element overlies the first surface. The antenna element is coupled to the electronic device package, and a projection of the patch antenna element onto the first surface resides within the antenna opening. Also provided are methods for manufacturing such an electronic device module.Type: ApplicationFiled: January 25, 2010Publication date: July 28, 2011Applicant: FREESCALE SEMICONDUCTOR, INC.Inventor: Jinbang Tang
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Patent number: 7981730Abstract: An integrated conformal electromagnetic interference (EMI) and/or electromagnetic radiation shield is formed on a plurality of encapsulated modules by attaching a plurality of modules (30-33) to a process carrier (1) using a double side adhesive tape (2), and then sequentially depositing an insulating layer (15) and a conductive shielding layer (16) before encapsulating the modules with a molding compound (17). After removing the adhesive tape (2) to expose a surface of the encapsulated modules, a multi-layer circuit substrate (100) is formed over the exposed surface, where the circuit substrate includes shielding via structures (101-112) that are aligned with and electrically connected to the conductive shielding layer (16), thereby encircling and shielding the circuit module(s).Type: GrantFiled: July 9, 2008Date of Patent: July 19, 2011Assignee: Freescale Semiconductor, Inc.Inventors: Jinbang Tang, Darrel R. Frear, Scott M. Hayes, Douglas G. Mitchell
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Patent number: 7977785Abstract: An electronic device and a method of packaging an electronic device are disclosed. In one embodiment, the electronic device can include a first die. The electronic device can also include a dielectric layer defining a first opening. The first die can be disposed within the first opening. Further, the electronic device can include an encapsulating material disposed adjacent to the first die. The encapsulating material can have a different composition as compared to the dielectric layer. In a particular embodiment, the electronic device can also include an electrically conductive carrier contacting the dielectric layer and the encapsulating material.Type: GrantFiled: March 5, 2009Date of Patent: July 12, 2011Assignee: Freescale Semiconductor, Inc.Inventor: Jinbang Tang
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Patent number: 7969164Abstract: A method for mini module EMI shielding effectiveness evaluation comprises providing a test vehicle including at least one test platform. The test platform includes at least one mini emitter, a mini receiver with a reference shield, and a mini receiver with a shield under test. EMI shielding effectiveness transmission signals are applied to the at least one mini emitter. Signals received by the mini receiver with a shield under test and the mini receiver with the reference shield are evaluated. The mini emitter, mini receiver with the reference shield, and mini receiver with the shield under test comprise components fabricated concurrently and under fabrication conditions used for fabrication of the test platform of the test vehicle. As used herein, a mini emitter and mini receiver may be interchanged according to the requirements of a given EMI shielding effectiveness evaluation.Type: GrantFiled: March 31, 2008Date of Patent: June 28, 2011Assignee: Freescale Semiconductor, Inc.Inventors: Jinbang Tang, James E. Drye, Scott M. Hayes
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Publication number: 20110075394Abstract: A shielding structure is provided for shielding a signal path extending between a first layer and a second layer in an electronic device at a transition region with a transition that extends in a first direction and a second direction orthogonal to the first direction. The shielding structure includes a shielding structure portion, which includes a first shielding via in proximity to a first area of the signal path at the transition; a second shielding via in proximity to a second area of the signal path at the transition; and an area metallization electrically coupled to the first shielding via.Type: ApplicationFiled: December 8, 2010Publication date: March 31, 2011Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Jinbang Tang, Jong-Kai Lin, Ronald V. McBean
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Publication number: 20110027984Abstract: An electronic device can include an interconnect level including a bonding pad region. An insulating layer can overlie the interconnect level and include an opening over the bonding pad region. In one embodiment, a conductive stud can lie within the opening and can be substantially encapsulated. In another embodiment, the electronic device can include a barrier layer lying along a side and a bottom of the opening and a conductive stud lying within the opening. The conductive stud can substantially fill the opening. A majority of the conductive stud can lie within the opening. In still another embodiment, a process for forming an electronic device can include forming a conductive stud within the opening wherein from a top view, the conductive stud lies substantially completely within the opening. The process can also include forming a second barrier layer overlying the conductive stud.Type: ApplicationFiled: October 11, 2010Publication date: February 3, 2011Applicant: Freescale Semiconductor, Inc.Inventors: Lakshmi N. Ramanathan, Tien Yu T. Lee, Jinbang Tang
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Patent number: 7869225Abstract: A shielding structure is provided for shielding a signal path extending between a first layer and a second layer in an electronic device at a transition region with a transition that extends in a first direction and a second direction orthogonal to the first direction. The shielding structure includes a shielding structure portion, which includes a first shielding via in proximity to a first area of the signal path at the transition; a second shielding via in proximity to a second area of the signal path at the transition; and an area metallization electrically coupled to the first shielding via.Type: GrantFiled: April 30, 2007Date of Patent: January 11, 2011Assignee: Freescale Semiconductor, Inc.Inventors: Jinbang Tang, Jong-Kai Lin, Ronald V. McBean
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Publication number: 20110003435Abstract: Electromagnetic shielding for an integrated circuit packaged device. The method includes forming shielding structures by forming openings in an encapsulated structure. The openings are filled with conductive material that surrounds at least one die. The encapsulated structure may include a plurality of integrated circuit die. A layered redistribution structure is formed on one side of the encapsulated structure.Type: ApplicationFiled: January 15, 2010Publication date: January 6, 2011Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: JINBANG TANG, DARREL FREAR, JONG-KAI LIN, MARC A. MANGRUM, ROBERT E. BOOTH, LAWRENCE N. HERR, KENNETH R. BURCH
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Patent number: 7842546Abstract: An integrated circuit (IC) module (20) includes a ground plane (22) having adjoining cutouts (30, 32). The cutout (32) defines a critical signal pathway (38). A device (24) is positioned in the cutout (30) and a device (26) is positioned outside of the cutout (30) adjacent to the cutout (32). An electrical interconnect (56) positioned in the critical signal pathway (38) interconnects the device (24) with the device (26). A method (60) of packaging the IC module (20) entails encapsulating the ground plane (22) and devices (24, 26) in a packaging material, and forming conductive vias (92) in the packaging material (84) that extend between the ground plane (22) and an exterior surface (94) of the packaging material (84). The conductive vias (92) surround the device (24) and cutout (32) to protect again electromagnetic interference and to provide guided signal pathways for high frequency signals on electrical interconnect (56).Type: GrantFiled: June 30, 2010Date of Patent: November 30, 2010Assignee: Freescale Semiconductor, Inc.Inventor: Jinbang Tang
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Patent number: 7838420Abstract: A packaged semiconductor device includes an interconnect layer over a first side of a polymer layer, a semiconductor device surrounded on at least three sides by the polymer layer and coupled to the interconnect layer, a first conductive element over a second side of the polymer layer, wherein the second side is opposite the first side, and a connector block within the polymer layer. The connector block has at least one electrical path extending from a first surface of the connector block to a second surface of the connector block. The at least one electrical path electrically couples the interconnect layer to the first conductive element. A method of forming the packaged semiconductor device is also described.Type: GrantFiled: August 29, 2007Date of Patent: November 23, 2010Assignee: Freescale Semiconductor, Inc.Inventors: Jinbang Tang, Darrel R. Frear, William H. Lytle
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Publication number: 20100276766Abstract: A device comprises a conductive substrate, a micro electromechanical systems (MEMS) structure, and a plurality of bond pads. The conductive substrate has a first side and a second side, the second side opposite the first side. The MEMS structure is formed over the first side of the conductive substrate. The plurality of bond pads are formed over the first side of the conductive substrate and electrically coupled to the first side of the conductive substrate. The conductive substrate and plurality of bond pads function to provide electrostatic shielding to the MEMS structure.Type: ApplicationFiled: April 29, 2009Publication date: November 4, 2010Inventors: Jinbang Tang, Lianjun Liu
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Publication number: 20100267207Abstract: An integrated circuit (IC) module (20) includes a ground plane (22) having adjoining cutouts (30, 32). The cutout (32) defines a critical signal pathway (38). A device (24) is positioned in the cutout (30) and a device (26) is positioned outside of the cutout (30) adjacent to the cutout (32). An electrical interconnect (56) positioned in the critical signal pathway (38) interconnects the device (24) with the device (26). A method (60) of packaging the IC module (20) entails encapsulating the ground plane (22) and devices (24, 26) in a packaging material, and forming conductive vias (92) in the packaging material (84) that extend between the ground plane (22) and an exterior surface (94) of the packaging material (84). The conductive vias (92) surround the device (24) and cutout (32) to protect again electromagnetic interference and to provide guided signal pathways for high frequency signals on electrical interconnect (56).Type: ApplicationFiled: June 30, 2010Publication date: October 21, 2010Applicant: FREESCALE SEMICONDUCTOR, INC.Inventor: Jinbang Tang