Patents by Inventor Jinbang Tang

Jinbang Tang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7812448
    Abstract: An electronic device can include an interconnect level (16) including a bonding pad region (110). An insulating layer (18) can overlie the interconnect level (16) and include an opening (112, 24) over the bonding pad region (110). In one embodiment, a conductive stud (34) can lie within the opening (112, 24) and can be substantially encapsulated. In another embodiment, the electronic device can include a barrier layer (22) lying along a side and a bottom of the opening (112, 24) and a conductive stud (34) lying within the opening (112, 24). The conductive stud (34) can substantially fill the opening (112, 24). A majority of the conductive stud (34) can lie within the opening (112, 24). In still another embodiment, a process for forming an electronic device can include forming a conductive stud (34) within the opening (112, 24) wherein the conductive stud (34) lies substantially completely within the opening (112, 24).
    Type: Grant
    Filed: August 7, 2006
    Date of Patent: October 12, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Lakshmi N. Ramanathan, Tien Yu T. Lee, Jinbang Tang
  • Publication number: 20100224969
    Abstract: An electronic device and a method of packaging an electronic device are disclosed. In one embodiment, the electronic device can include a first die. The electronic device can also include a dielectric layer defining a first opening. The first die can be disposed within the first opening. Further, the electronic device can include an encapsulating material disposed adjacent to the first die. The encapsulating material can have a different composition as compared to the dielectric layer. In a particular embodiment, the electronic device can also include an electrically conductive carrier contacting the dielectric layer and the encapsulating material.
    Type: Application
    Filed: March 5, 2009
    Publication date: September 9, 2010
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventor: Jinbang Tang
  • Patent number: 7772694
    Abstract: An integrated circuit (IC) module (20) includes a ground plane (22) having adjoining cutouts (30, 32). The cutout (32) defines a critical signal pathway (38). A device (24) is positioned in the cutout (30) and a device (26) is positioned outside of the cutout (30) adjacent to the cutout (32). An electrical interconnect (56) positioned in the critical signal pathway (38) interconnects the device (24) with the device (26). A method (60) of packaging the IC module (20) entails encapsulating the ground plane (22) and devices (24, 26) in a packaging material, and forming conductive vias (92) in the packaging material (84) that extend between the ground plane (22) and an exterior surface (94) of the packaging material (84). The conductive vias (92) surround the device (24) and cutout (32) to protect again electromagnetic interference and to provide guided signal pathways for high frequency signals on electrical interconnect (56).
    Type: Grant
    Filed: November 26, 2008
    Date of Patent: August 10, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Jinbang Tang
  • Patent number: 7763976
    Abstract: A disclosed integrated circuit (IC) module includes an IC panel and multi level circuit structure, referred to as an IPD structure, overlying an upper surface of the IC panel. The IC panel includes an electrically conductive embedded ground plane (EGP), an integrated circuit (IC) die, and an encapsulating material. The EGP is a substantially planar structure that includes or defines a plurality of cavities. The EGP may include or define an IC cavity and an IPD cavity. The IC die may be positioned within the IC cavity such that a perimeter of the IC cavity surrounds the IC die. The IPD structure may define or include a passive device such as an inductor. The passive device may be positioned or located overlying the void in the EGP.
    Type: Grant
    Filed: September 30, 2008
    Date of Patent: July 27, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Jinbang Tang, Darrel R. Frear, Robert J. Wenzel
  • Publication number: 20100148333
    Abstract: A module, which in one embodiment may be a packaged millimeter waver module, includes a semiconductor lid portion; a packaging portion attached to the lid portion, wherein the packaging portion comprises a plurality of vias, a carrier portion, wherein a first semiconductor die is attached to the carrier portion, the packaging portion is attached to the carrier portion so that the packaging portion is over the carrier portion and the semiconductor die is within an opening in the packaging portion, and the lid portion and the carrier portion form an first air gap around the first semiconductor device.
    Type: Application
    Filed: December 16, 2008
    Publication date: June 17, 2010
    Inventor: JINBANG TANG
  • Publication number: 20100127396
    Abstract: An integrated circuit (IC) module (20) includes a ground plane (22) having adjoining cutouts (30, 32). The cutout (32) defines a critical signal pathway (38). A device (24) is positioned in the cutout (30) and a device (26) is positioned outside of the cutout (30) adjacent to the cutout (32). An electrical interconnect (56) positioned in the critical signal pathway (38) interconnects the device (24) with the device (26). A method (60) of packaging the IC module (20) entails encapsulating the ground plane (22) and devices (24, 26) in a packaging material, and forming conductive vias (92) in the packaging material (84) that extend between the ground plane (22) and an exterior surface (94) of the packaging material (84). The conductive vias (92) surround the device (24) and cutout (32) to protect again electromagnetic interference and to provide guided signal pathways for high frequency signals on electrical interconnect (56).
    Type: Application
    Filed: November 26, 2008
    Publication date: May 27, 2010
    Applicant: Freescale Semiconductor, Inc.
    Inventor: Jinbang Tang
  • Publication number: 20100078760
    Abstract: A disclosed integrated circuit (IC) module includes an IC panel and multi level circuit structure, referred to as an IPD structure, overlying an upper surface of the IC panel. The IC panel includes an electrically conductive embedded ground plane (EGP), an integrated circuit (IC) die, and an encapsulating material. The EGP is a substantially planar structure that includes or defines a plurality of cavities. The EGP may include or define an IC cavity and an IPD cavity. The IC die may be positioned within the IC cavity such that a perimeter of the IC cavity surrounds the IC die. The IPD structure may define or include a passive device such as an inductor. The passive device may be positioned or located overlying the void in the EGP.
    Type: Application
    Filed: September 30, 2008
    Publication date: April 1, 2010
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Jinbang Tang, Darrel R. Frear, Robert J. Wenzel
  • Publication number: 20100044840
    Abstract: Embodiments include shielded multi-layer packages for use with multi-chip modules and the like. A substrate (102) (e.g., chip carrier) has an adhesive layer (104), where electronic components (106, 108) are attached. An insulating layer (110) is formed over the plurality of electronic components, and a conductive encapsulant structure (115) is formed over the insulating layer. The adhesive layer is detached from the electronic components, and multi-layer circuitry (140) is formed over, and in electrical communication with, the plurality of electronic components. A shielding via (150) is formed through the multilayer circuitry such that it contacts the conductive encapsulant.
    Type: Application
    Filed: October 27, 2009
    Publication date: February 25, 2010
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Jinbang Tang, Jong-Kai Lin
  • Patent number: 7651889
    Abstract: Electromagnetic shielding for an integrated circuit packaged device. The method includes forming shielding structures by forming openings in an encapsulated structure. The openings are filled with conductive material that surrounds at least one die. The encapsulated structure may include a plurality of integrated circuit die. A layered redistribution structure is formed on one side of the encapsulated structure.
    Type: Grant
    Filed: December 20, 2007
    Date of Patent: January 26, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Jinbang Tang, Darrel Frear, Jong-Kai Lin, Marc A. Mangrum, Robert E. Booth, Lawrence N. Herr, Kenneth R. Burch
  • Patent number: 7648858
    Abstract: Methods and structures provide a shielded multi-layer package for use with multi-chip modules and the like. A substrate (102) (e.g., chip carrier) has an adhesive layer (104), where electronic components (106, 108) are attached. An insulating layer (110) is formed over the plurality of electronic components, and a conductive encapsulant structure (115) is formed over the insulating layer. The adhesive layer is detached from the electronic components, and multi-layer circuitry (140) is formed over, and in electrical communication with, the plurality of electronic components. A shielding via (150) is formed through the multilayer circuitry such that it contacts the conductive encapsulant.
    Type: Grant
    Filed: June 19, 2007
    Date of Patent: January 19, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Jinbang Tang, Jong-Kai Lin
  • Publication number: 20100006988
    Abstract: An integrated conformal electromagnetic interference (EMI) and/or electromagnetic radiation shield is formed on a plurality of encapsulated modules by attaching a plurality of modules (30-33) to a process carrier (1) using a double side adhesive tape (2), and then sequentially depositing an insulating layer (15) and a conductive shielding layer (16) before encapsulating the modules with a molding compound (17). After removing the adhesive tape (2) to expose a surface of the encapsulated modules, a multi-layer circuit substrate (100) is formed over the exposed surface, where the circuit substrate includes shielding via structures (101-112) that are aligned with and electrically connected to the conductive shielding layer (16), thereby encircling and shielding the circuit module(s).
    Type: Application
    Filed: July 9, 2008
    Publication date: January 14, 2010
    Inventors: Jinbang Tang, Darrel R. Frear, Scott M. Hayes, Douglas G. Mitchell
  • Publication number: 20090243629
    Abstract: A method for mini module EMI shielding effectiveness evaluation comprises providing a test vehicle including at least one test platform. The test platform includes at least one mini emitter, a mini receiver with a reference shield, and a mini receiver with a shield under test. EMI shielding effectiveness transmission signals are applied to the at least one mini emitter. Signals received by the mini receiver with a shield under test and the mini receiver with the reference shield are evaluated. The mini emitter, mini receiver with the reference shield, and mini receiver with the shield under test comprise components fabricated concurrently and under fabrication conditions used for fabrication of the test platform of the test vehicle. As used herein, a mini emitter and mini receiver may be interchanged according to the requirements of a given EMI shielding effectiveness evaluation.
    Type: Application
    Filed: March 31, 2008
    Publication date: October 1, 2009
    Inventors: Jinbang Tang, James E. Drye, Scott M. Hayes
  • Publication number: 20090075428
    Abstract: Electromagnetic shielding for an integrated circuit packaged device. The method includes forming shielding structures by forming openings in an encapsulated structure. The openings are filled with conductive material that surrounds at least one die. The encapsulated structure may include a plurality of integrated circuit die. A layered redistribution structure is formed on one side of the encapsulated structure.
    Type: Application
    Filed: December 20, 2007
    Publication date: March 19, 2009
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Jinbang Tang, Darrel Frear, Jong-Kai Lin, Marc A. Mangrum, Robert E. Booth, Lawrence N. Herr, Kenneth R. Burch
  • Publication number: 20090072357
    Abstract: An electromagnetic interference (EMI) and/or electromagnetic radiation shield is formed on a plurality of encapsulated modules by attaching a plurality of modules (30-33) to a process carrier (10) using a double side adhesive tape (12) before encapsulating the modules with a molding compound (16), and then forming shielding via ring structures (51-54) in the molding compound (16) to surround and shield each module. After removing the adhesive tape (12) to expose a surface of the encapsulated modules, a multi-layer circuit substrate (101) is formed over the exposed surface, where the circuit substrate includes shielding via structures (121-124) that are aligned with and electrically connected to the shielding via ring structures (51-54), thereby encircling and shielding the circuit module(s).
    Type: Application
    Filed: September 13, 2007
    Publication date: March 19, 2009
    Inventors: Jinbang Tang, Darrel R. Frear, Jong-Kai Lin
  • Publication number: 20090057849
    Abstract: A packaged semiconductor device includes an interconnect layer over a first side of a polymer layer, a semiconductor device surrounded on at least three sides by the polymer layer and coupled to the interconnect layer, a first conductive element over a second side of the polymer layer, wherein the second side is opposite the first side, and a connector block within the polymer layer. The connector block has at least one electrical path extending from a first surface of the connector block to a second surface of the connector block. The at least one electrical path electrically couples the interconnect layer to the first conductive element. A method of forming the packaged semiconductor device is also described.
    Type: Application
    Filed: August 29, 2007
    Publication date: March 5, 2009
    Inventors: Jinbang Tang, Darrel R. Frear, William H. Lytle
  • Publication number: 20080315376
    Abstract: An electromagnetic interference (EMI) and/or electromagnetic radiation shield is formed on a plurality of encapsulated modules by attaching a molded package panel to a process carrier (10) using a double side adhesive tape (12) before singulating the individual modules without separating them from the double side adhesive tape. By forming a conductive layer (50) over a mold encapsulant (16) and on the sidewalls of grooves (40-47) that are cut through the mold encapsulant (16) and underlying circuit substrate (14), the conductive layer (50) may be electrically coupled to one or more conductive connection pads (61-66) by virtue of the placement of the conductive connection pads at the periphery or side of the circuit substrate (14).
    Type: Application
    Filed: June 19, 2007
    Publication date: December 25, 2008
    Inventors: Jinbang Tang, Jong-Kai Lin
  • Publication number: 20080315371
    Abstract: Methods and structures provide a shielded multi-layer package for use with multi-chip modules and the like. A substrate (102) (e.g., chip carrier) has an adhesive layer (104), where electronic components (106, 108) are attached. An insulating layer (110) is formed over the plurality of electronic components, and a conductive encapsulant structure (115) is formed over the insulating layer. The adhesive layer is detached from the electronic components, and multi-layer circuitry (140) is formed over, and in electrical communication with, the plurality of electronic components. A shielding via (150) is formed through the multilayer circuitry such that it contacts the conductive encapsulant.
    Type: Application
    Filed: June 19, 2007
    Publication date: December 25, 2008
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Jinbang Tang, Jong-Kai Lin
  • Publication number: 20080266829
    Abstract: A shielding structure is provided for shielding a signal path extending between a first layer and a second layer in an electronic device at a transition region with a transition that extends in a first direction and a second direction orthogonal to the first direction. The shielding structure includes a shielding structure portion, which includes a first shielding via in proximity to a first area of the signal path at the transition; a second shielding via in proximity to a second area of the signal path at the transition; and an area metallization electrically coupled to the first shielding via.
    Type: Application
    Filed: April 30, 2007
    Publication date: October 30, 2008
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Jinbang Tang, Jong-Kai Lin, Ronald V. McBean
  • Publication number: 20080029887
    Abstract: An electronic device can include an interconnect level (16) including a bonding pad region (110). An insulating layer (18) can overlie the interconnect level (16) and include an opening (112, 24) over the bonding pad region (110). In one embodiment, a conductive stud (34) can lie within the opening (112, 24) and can be substantially encapsulated. In another embodiment, the electronic device can include a barrier layer (22) lying along a side and a bottom of the opening (112, 24) and a conductive stud (34) lying within the opening (112, 24). The conductive stud (34) can substantially fill the opening (112, 24). A majority of the conductive stud (34) can lie within the opening (112, 24). In still another embodiment, a process for forming an electronic device can include forming a conductive stud (34) within the opening (112, 24) wherein from a top view, the conductive stud (34) lies substantially completely within the opening (112, 24).
    Type: Application
    Filed: August 7, 2006
    Publication date: February 7, 2008
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Lakshmi N. Ramanathan, Tien Yu T. Lee, Jinbang Tang
  • Patent number: 7145084
    Abstract: A radiation shielded module (120, 500, 600, 700) and method of shielding microelectronic devices (126, 412, 618, and 718) including a single interconnect substrate (110, 400, 612, 712) having a first side (122, 410, 620, 720) and a second side (124, 416, 610, 710). At least one microelectronic device is coupled to the first side of the single interconnect substrate. A shielding structure (100, 200, 300, 614, 714) is coupled to the single interconnect substrate and configured to shield radio frequency interference (RFI) and electromagnetic interference (EMI) that propagate through at least a portion of the single interconnect substrate.
    Type: Grant
    Filed: August 30, 2005
    Date of Patent: December 5, 2006
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Vijay Sarihan, Scott M. Hayes, Jinbang Tang