Patents by Inventor Jing-Cheng Lin

Jing-Cheng Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11417580
    Abstract: An embodiment is a method including: attaching a first die to a first side of a first component using first electrical connectors, attaching a first side of a second die to first side of the first component using second electrical connectors, attaching a dummy die to the first side of the first component in a scribe line region of the first component, adhering a cover structure to a second side of the second die, and singulating the first component and the dummy die to form a package structure.
    Type: Grant
    Filed: September 4, 2020
    Date of Patent: August 16, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chen-Hua Yu, Wen-Hsin Wei, Chi-Hsi Wu, Shang-Yun Hou, Jing-Cheng Lin, Hsien-Pin Hu, Ying-Ching Shih, Szu-Wei Lu
  • Patent number: 11401608
    Abstract: An atomic layer deposition equipment and an atomic layer deposition process method are disclosed. The atomic layer deposition equipment includes a chamber, a substrate stage, at least one bottom pumping port, at least one hollow component, a baffle and a shower head assembly, wherein the hollow component has an exhaust hole. The baffle is below the hollow component and forms an upper exhaust path with the hollow component, so that the flow field of the precursor in the atomic layer deposition process can be adjusted to a slow flow field to make a uniform deposition on the substrate.
    Type: Grant
    Filed: October 20, 2020
    Date of Patent: August 2, 2022
    Assignee: SKY TECH INC.
    Inventors: Jing-Cheng Lin, Ching-Liang Yi, Yun-Chi Hsu, Hsin-Yu Yao
  • Patent number: 11393770
    Abstract: A semiconductor device has a conductive via laterally separated from the semiconductor, an encapsulant between the semiconductor device and the conductive via, and a mark. The mark is formed from characters that are either cross-free characters or else have a overlap count of less than two. In another embodiment the mark is formed using a wobble scan methodology. By forming marks as described, defects from the marking process may be reduced or eliminated.
    Type: Grant
    Filed: October 26, 2020
    Date of Patent: July 19, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jing-Cheng Lin, Chen-Hua Yu, Po-Hao Tsai
  • Publication number: 20220220615
    Abstract: The present disclosure is a wafer support, which includes a heating unit, an insulating-and-heat-conducting unit and a conduct portion, wherein the insulating-and-heat-conducting unit is positioned between the conduct portion and the heating unit. During a deposition process, an AC bias is formed on the conduct portion to attract a plasma disposed thereabove. The heating unit includes at least one heating coil, wherein the heating coil heats the wafer supported by the wafer support via the insulating-and-heat-conducting unit and the conduct portion. The insulating-and-heat-conducting unit electrically insulates the heating unit and the conduct portion to prevent the AC flowing in the heating coil and the AC bias on the conduct portion from conducting each other, so the wafer support can generate a stable AC bias and temperature to facilitate forming an evenly-distributed thin film on the wafer supported by the wafer support.
    Type: Application
    Filed: January 8, 2021
    Publication date: July 14, 2022
    Inventors: JING-CHENG LIN, CHUN-FU WANG
  • Patent number: 11387217
    Abstract: An integrated fan out package on package architecture is utilized along with a reference via in order to provide a reference voltage that extends through the InFO-POP architecture. If desired, the reference via may be exposed and then connected to a shield coating that can be used to shield the InFO-POP architecture. The reference via may be exposed by exposing either a top surface or a sidewall of the reference via using one or more singulation processes.
    Type: Grant
    Filed: November 16, 2020
    Date of Patent: July 12, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jing-Cheng Lin, Chen-Hua Yu, Po-Hao Tsai
  • Publication number: 20220199860
    Abstract: The present disclosure is a light-emitting diode (LED) with oxidized aluminum nitride (oxidized-AlN) film, which includes a substrate, an aluminum nitride buffer (AlN-buffer) layer, an oxidized-AlN film and a light-emitting diode epitaxial structure. The AlN-buffer layer is disposed on a patterned surface of the substrate, wherein the patterned surface is formed with a plurality of protrusions and a bottom portion. The oxidized-AlN film is disposed on the AlN-buffer layer on the protrusions, and with none disposed on the AlN-buffer layer on the bottom portion. The LED epitaxial structure includes gallium nitride compound crystal formed on the oxidized-AlN film and the AlN-buffer layer, to effectively reduce defect density of the gallium nitride compound crystal and to improve a luminous intensity of the LED.
    Type: Application
    Filed: March 17, 2021
    Publication date: June 23, 2022
    Inventor: JING-CHENG LIN
  • Publication number: 20220199465
    Abstract: A method of forming a semiconductor device includes attaching a metal foil to a carrier, the metal foil being pre-made prior to attaching the metal foil; forming a conductive pillar on a first side of the metal foil distal the carrier; attaching a semiconductor die to the first side of the metal foil; forming a molding material around the semiconductor die and the conductive pillar; and forming a redistribution structure over the molding material.
    Type: Application
    Filed: February 21, 2022
    Publication date: June 23, 2022
    Inventors: Chih-Wei Wu, Ying-Ching Shih, Szu-Wei Lu, Jing-Cheng Lin, Long Hua Lee
  • Publication number: 20220199675
    Abstract: The present disclosure is a manufacturing method for reducing non-radiative recombination of micro LED. At least one etched LED epitaxial wafer includes a plurality of etching grooves and mesas, an etched sidewall of the mesa includes a stack of a first type semiconductor layer, an active layer and a second type semiconductor layer. Two stages of ALD are performed on the etched LED epitaxial wafer with different temperature ranges. The first ALD can be used to repair dangling bonds and defects on the etched side walls of the mesa, and the second ALD can be used to form a passivation layer on the etched side walls of the mesa. By the manufacturing method of the present disclosure, non-radiative recombination of the micro LED can be reduced, and the luminous brightness and luminous efficiency of the micro LED can be improved.
    Type: Application
    Filed: December 21, 2020
    Publication date: June 23, 2022
    Inventor: JING-CHENG LIN
  • Publication number: 20220189920
    Abstract: A package structure is provided. The package structure includes a first die and a second die, a dielectric layer, a bridge, an encapsulant, and a redistribution layer structure. The dielectric layer is disposed on the first die and the second die. The bridge is electrically connected to the first die and the second die, wherein the dielectric layer is spaced apart from the bridge. The encapsulant is disposed on the dielectric layer and laterally encapsulating the bridge. The redistribution layer structure is disposed over the encapsulant and the bridge. A top surface of the bridge is in contact with the RDL structure.
    Type: Application
    Filed: March 7, 2022
    Publication date: June 16, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shu-Hang Liao, Chih-Wei Wu, Jing-Cheng Lin, Szu-Wei Lu, Ying-Ching Shih
  • Patent number: 11362046
    Abstract: Some embodiments relate to a semiconductor package. The package includes a redistribution layer (RDL), and a first semiconductor die disposed over the RDL. The first semiconductor die includes a plurality of contact pads electrically coupled to the RDL. The RDL enables fan-out connection of the first semiconductor die. A die package is disposed over the first semiconductor die and over the RDL. The die package is coupled to a first surface of the RDL by a plurality of conductive bump structures. The plurality of conductive bump structures laterally surround the plurality of contact pads and have uppermost surfaces that are level with an uppermost surface of the first semiconductor die.
    Type: Grant
    Filed: May 29, 2020
    Date of Patent: June 14, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jing-Cheng Lin, Chin-Chuan Chang, Jui-Pin Hung
  • Publication number: 20220178021
    Abstract: The present disclosure is a thin-film deposition equipment including a chamber, a stage, at least one baffle and at least one shielding component. The stage is for carrying a substrate, the baffle prevents the substrate on the stage from backside coating. The shielding component is positioned higher the baffle for shielding the baffle, to receive target atoms which is yet deposited on the substrate for the baffle. Such that to avoid the target atoms deposited on the baffle forming a thin film, and to further prevent a problem of the thin film from being heated then flowing from the baffle to a contact area between the baffle and the substrate.
    Type: Application
    Filed: December 8, 2020
    Publication date: June 9, 2022
    Inventors: CHING-LIANG YI, JING-CHENG LIN, YAO-Syuan CHENG
  • Publication number: 20220181195
    Abstract: A wafer holder for generating a stable bias voltage, which mainly includes a holder, a ring member, and a cover ring, wherein a supporting surface of the holder is used to carry at least one wafer, and the ring member is arranged on the holder and located around the supporting surface and the wafer. The ring member includes an outer surface and an inner surface, wherein the inner surface of the ring member covers a part of the side surface of the holder and makes parts of the side surface exposed. When the cover ring is connected to the ring member, a shielding portion of the cover ring will cover the exposed side surface of the holder to avoid a film being formed on the exposed side surface of the holder to facilitate the formation of a uniform and stable bias voltage on the wafer holder.
    Type: Application
    Filed: March 5, 2021
    Publication date: June 9, 2022
    Inventors: JING-CHENG LIN, CHUN-FU WANG
  • Publication number: 20220181305
    Abstract: A chip package structure is provided. The chip package structure includes a chip structure. The chip package structure includes a first ground bump below the chip structure. The chip package structure includes a conductive shielding film disposed over the chip structure and extending onto the first ground bump. The conductive shielding film has a curved bottom surface.
    Type: Application
    Filed: February 25, 2022
    Publication date: June 9, 2022
    Inventors: Chen-Hua YU, An-Jhih SU, Jing-Cheng LIN, Po-Hao TSAI
  • Publication number: 20220178022
    Abstract: An atomic layer deposition equipment and an atomic layer deposition process method are disclosed. The atomic layer deposition equipment includes a chamber, a heater, a support unit, a hollow component, a bottom pumping port, and a shower head component, wherein the support unit is disposed on the top surface of the heater for supporting a substrate. There is an upper exhaust path formed between the hollow component and the support unit for exhausting process fluid such as precursors, so that the flow field of the process fluid in the atomic layer deposition process can be adjusted stably to make a uniform deposition on the substrate.
    Type: Application
    Filed: December 3, 2020
    Publication date: June 9, 2022
    Inventors: JING-CHENG LIN, TA-HAO KUO
  • Publication number: 20220181190
    Abstract: A wafer fixing mechanism as disclosed includes a fixing ring, a plurality of fixing members and a plurality of elastic units, wherein each fixing member is respectively connected to the fixing ring through a connecting shaft. The fixing ring includes a containing area for containing a wafer, and the wafer in the containing area is fixed by the fixing members. The two ends of the elastic unit are respectively connected to the fixing ring and the fixing member. When the wafer pushes the fixing members, the fixing members will swing relative to the fixing ring to prevent the fixing members from damaging the wafer. In addition, when the fixing member swings relative to the fixing ring, the elastic unit is deformed, so that the restoring force of the elastic unit is applied to the wafer via the fixing member, thereby fixing the wafer on a support pedestal.
    Type: Application
    Filed: December 3, 2020
    Publication date: June 9, 2022
    Inventors: JING-CHENG LIN, CHI-HUNG CHENG, YU-TE SHEN, YAO-SYUAN CHENG
  • Patent number: 11355406
    Abstract: A package includes a device die, a through-via having a sand timer profile, and a molding material molding the device die and the through-via therein, wherein a top surface of the molding material is substantially level with a top surface of the device die. A dielectric layer overlaps the molding material and the device die. A plurality of redistribution lines (RDLs) extends into the dielectric layer to electrically couple to the device die and the through-via.
    Type: Grant
    Filed: June 8, 2020
    Date of Patent: June 7, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Lin Huang, Jung-Hua Chang, Jy-Jie Gau, Jing-Cheng Lin
  • Publication number: 20220162750
    Abstract: A powder atomic layer deposition apparatus with special cover lid is disclosed, which includes a vacuum chamber, a shaft sealing device, and a driving unit that drives the vacuum chamber to rotate through the shaft sealing device. The vacuum chamber includes a chamber and a cover lid having an inner surface. At least one fan unit and a monitor wafer are arranged on the inner surface of the cover lid, wherein the monitor wafer is located between the fan unit and the cover lid, and there is a gap between the monitor wafer and the fan unit. An air intake line directs a gas toward the fan unit, and the fan unit drives the gas to flow throughout a reaction space, so that powders in the reaction space are blown around for thin films of uniform thickness to form on the surface of the powders and the monitor wafer.
    Type: Application
    Filed: May 30, 2021
    Publication date: May 26, 2022
    Inventors: JING-CHENG LIN, JUNG-HUA CHANG, CHIA-CHENG KU
  • Publication number: 20220165600
    Abstract: The present disclosure relates to a substrate transfer system, which includes a main body, a tray cassette base, a tray aligner, a tray robot, a substrate cassette base, a substrate aligner, a substrate robot and a Bernoulli robot. The tray can be transferred to the tray aligner by the tray robot. The substrate can be transferred to the substrate aligner by the substrate robot. By the Bernoulli robot, the substrate can be transferred from the substrate aligner to the tray on the tray aligner.
    Type: Application
    Filed: March 11, 2021
    Publication date: May 26, 2022
    Inventors: JING-CHENG LIN, JUNG-HUA CHANG
  • Publication number: 20220165611
    Abstract: A method includes forming a metal layer extending into openings of a dielectric layer to contact a first metal pad and a second metal pad, and bonding a bottom terminal of a component device to the metal layer. The metal layer has a first portion directly underlying and bonded to the component device. A raised via is formed on the metal layer, and the metal layer has a second portion directly underlying the raised via. The metal layer is etched to separate the first portion and the second portion of the metal layer from each other. The method further includes coating the raised via and the component device in a dielectric layer, revealing the raised via and a top terminal of the component device, and forming a redistribution line connecting the raised via to the top terminal.
    Type: Application
    Filed: February 14, 2022
    Publication date: May 26, 2022
    Inventors: Chen-Hua Yu, An-Jhih Su, Chi-Hsi Wu, Der-Chyang Yeh, Ming Shih Yeh, Jing-Cheng Lin, Hung-Jui Kuo
  • Publication number: 20220157695
    Abstract: Methods of packaging semiconductor devices and packaged semiconductor devices are disclosed. In some embodiments, a method of packaging a semiconductor device includes coupling through-vias to an insulating material, each of the through-vias having a first width. Dies are also coupled to the insulating material. A portion of the insulating material is removed proximate each of the through-vias. The portion of the insulating material proximate each of the through-vias removed has a second width, the second width being less than the first width.
    Type: Application
    Filed: January 31, 2022
    Publication date: May 19, 2022
    Inventors: Li-Hui Cheng, Po-Hao Tsai, Jing-Cheng Lin