Abstract: A method of manufacturing a semiconductor package is provided. The method includes: forming a plurality of sacrificial pads on a carrier substrate and a plurality of sacrificial solder bumps on the plurality of sacrificial pads, respectively; forming a plurality of conductive pillars and a protective insulating layer on a semiconductor chip, the protective insulating layer surrounding a side surface of each of the plurality of conductive pillars; polishing the plurality of conductive pillars and the protective insulating layer to obtain a polished surface in which a surface of each of the plurality of conductive pillars is coplanar with a surface of the protective insulating layer; and bonding the plurality of conductive pillars to the plurality of sacrificial solder bumps, respectively.

Abstract: A package structure includes a first semiconductor package and a second semiconductor package over the first semiconductor package. The first semiconductor package includes a dielectric structure, a semiconductor device on the dielectric structure, under bump metallization (UBM) structures in the dielectric structure. The USB structures each include a first region and a second region surrounded by the first region. The first region has more metal layers than the second region. The bumps are respectively on the second regions of the UBM structures.

Abstract: A semiconductor package is provided. The semiconductor package includes: a redistribution substrate; a first semiconductor chip provided on a right portion, in a first direction, of the redistribution substrate; a through-post provided on the redistribution substrate in a region adjacent to a left side, in the first direction, of the first semiconductor chip; a heat dissipation chip provided on the first semiconductor chip; and a second semiconductor device provided adjacent to the heat dissipation chip on the through-post. A metal pad and an adhesive layer are provided between the heat dissipation chip and the first semiconductor chip.

Abstract: Provided is a semiconductor package including a package substrate, a redistribution structure including a single-layered insulating layer positioned above the package substrate, and a plurality of horizontal redistribution structures embedded in the insulating layer and arranged side-by-side in a first horizontal direction parallel to an upper surface of the package substrate and in a second horizontal direction perpendicular to the first horizontal direction, external connection terminals arranged below the redistribution structure, and a semiconductor chip provided on the redistribution structure and including a chip body and chip connection terminals arranged below the chip body, wherein each of the plurality of horizontal redistribution structures includes a via passing through the insulating layer, and a tracer pattern formed integrally with the via and inclined and long from the first horizontal direction and the second horizontal direction.

Abstract: A semiconductor package according to an embodiment includes a first semiconductor chip, a second semiconductor chip, a first dielectric film surrounding the first semiconductor chip and the second semiconductor chip; first vias; second vias; a bridge chip; a second dielectric film surrounding the bridge chip and having an upper surface and a lower surface opposite to the upper surface; and a third via, some of the first vias are electrically connected to some of the bridge chip pads, some of the second vias are electrically connected to others of the bridge chip pads, and the passivation layer includes a same material as a material of the first dielectric film.

Abstract: Provided is a semiconductor package including a first redistribution structure, a second redistribution structure on the first redistribution structure, a plurality of semiconductor chips on an upper surface of the second redistribution structure, a bridge chip on a lower surface of the second redistribution structure, and a first molding layer between the first redistribution structure and the second redistribution structure and adjacent to the bridge chip, wherein the first molding layer is between the bridge chip and the first redistribution structure.

Abstract: A semiconductor package includes a redistribution structure including: a passivation layer; an under bump metallurgy (UBM) layer on a portion of a lower surface of the passivation layer; and a conductive layer in contact with the UBM layer and exposed from an upper surface of the passivation layer opposite to the lower surface of the passivation layer. The semiconductor package further includes: a bridge chip on the redistribution structure and including a bridge chip pad; a first molding layer sealing the bridge chip on the redistribution structure; conductive posts spaced apart from each other in a horizontal direction within the first molding layer, the bridge chip being between the conductive posts and each of the conductive posts; and a semiconductor chips on the first molding layer and the bridge chip, each of the semiconductor chips including a chip pad and a solder bump.

Abstract: A method of manufacturing a semiconductor package includes bonding a first semiconductor chip and a bridge structure onto a carrier structure; bonding a second semiconductor chip and a third semiconductor chip onto the bridge structure, the second semiconductor chip and the third semiconductor chip being apart from each other in a horizontal direction; and forming a plurality of connection bumps on the second semiconductor chip and the third semiconductor chip.

Abstract: A method of manufacturing a semiconductor package according to embodiments of the present disclosure has an effect of reducing the size of the semiconductor package by minimizing a distance between semiconductor chips by self-aligning the semiconductor chips on pads having fine gaps due to the surface tension of solder bumps.

Abstract: A method of manufacturing a semiconductor package according to embodiments of the present disclosure has an effect of reducing the size of the semiconductor package by minimizing a distance between semiconductor chips by self-aligning the semiconductor chips on pads having fine gaps due to the surface tension of solder bumps.

Abstract: A semiconductor package includes a first semiconductor chip, second semiconductor chips stacked on the first semiconductor chip, a first molding layer, a dummy chip and a second molding layer. Each second semiconductor chip includes a semiconductor substrate comprising an active surface and an inactive surface opposite to the active surface. The first molding layer surrounds a portion of an upper surface of the first semiconductor chip and side surfaces of the second semiconductor chips and includes a trench that extends from an upper surface of the first molding layer into the first molding layer. The dummy chip is stacked on an uppermost second semiconductor chip of the second semiconductor chips. The second molding layer surrounds side surfaces of the dummy chip, and covers the first molding layer.

Abstract: A method for forming a package structure may comprise applying a die and vias on a carrier having an adhesive layer and forming a molded substrate over the carrier and around the vias, and the ends of the vias and mounts on the die exposed. The vias may be in via chips with one or more dielectric layers separating the vias. The via chips 104 may be formed separately from the carrier. The dielectric layer of the via chips may separate the vias from, and comprise a material different than, the molded substrate. An RDL having RDL contact pads and conductive lines may be formed on the molded substrate. A second structure having at least one die may be mounted on the opposite side of the molded substrate, the die on the second structure in electrical communication with at least one RDL contact pad.

Abstract: A device includes an interposer, which includes a substrate having a top surface. An interconnect structure is formed over the top surface of the substrate, wherein the interconnect structure includes at least one dielectric layer, and metal features in the at least one dielectric layer. A plurality of through-substrate vias (TSVs) is in the substrate and electrically coupled to the interconnect structure. A first die is over and bonded onto the interposer. A second die is bonded onto the interposer, wherein the second die is under the interconnect structure.

Abstract: A method of forming a semiconductor device includes attaching a metal foil to a carrier, the metal foil being pre-made prior to attaching the metal foil; forming a conductive pillar on a first side of the metal foil distal the carrier; attaching a semiconductor die to the first side of the metal foil; forming a molding material around the semiconductor die and the conductive pillar; and forming a redistribution structure over the molding material.

Abstract: Some embodiments of the present disclosure provide a method of manufacturing a semiconductor device. The method includes: forming a carrier; forming a sacrificial layer on the carrier; forming a through via on the sacrificial layer, wherein the through via includes a seed layer and a metal feature; disposing a die on the sacrificial layer, wherein the die has a plurality of metal pillars disposed at a side of the die facing away from the sacrificial layer; forming a molding compound on the sacrificial layer to cover and surround the die and the through via; removing a portion of the molding compound and a portion of the through via above the die to expose the metal feature of the through via; and removing the carrier and sacrificial layer to expose the seed layer of the through via.

Abstract: A semiconductor package includes a first die, a plurality of through vias and a thermal conductive pattern. The through vias surround the first die. The thermal conductive pattern surrounds the first die, wherein the thermal conductive pattern is disposed between and electrically isolated from the first die and the through vias.

Abstract: A method is provided that includes operations as follows: bonding an epitaxial layer formed with a first semiconductor substrate and an ion-implanted layer that is formed between the epitaxial layer and the first semiconductor substrate, to a bonding oxide layer of a second semiconductor substrate; separating the first semiconductor substrate from the epitaxial layer, by removing the first semiconductor substrate together with a portion of the ion-implanted layer and keeping the epitaxial layer; and forming a first semiconductor device portion on the epitaxial layer, and an interconnect layer on the first semiconductor device portion.

Abstract: The present disclosure provides a deposition equipment, which includes a reaction chamber, a carrier, a target material, a magnetic device are at least one shield unit. The carrier and the target material are disposed within the containing space, wherein the carrier is for carrying a substrate, also a surface of the target material faces the carrier and the substrate. The magnetic device is disposed on another surface of the target material, to generate a magnetic field within the containing space through the target material. The shield unit is made electrical conductor and is disposed between a portion of the magnetic device and a portion of the target material, wherein the shield unit is for partially blocking and micro-adjusting the magnetic field generated by the magnetic device within the containing space, such that to improve an evenness of thickness for a thin film formed on the substrate.

Abstract: A parallelism-adjustable bonding machine includes a first chamber, a second chamber, a press-bonding unit, a carrier and plural parallelism-adjusting units. The first chamber is configured to connect to the second chamber, so as to define a closed space therebetween. The press-bonding unit is disposed within the first chamber, and the carrier is disposed within the second chamber. The press-bonding unit is disposed to face the carrier configured to press and bond substrates placed on the carrier. Each of the parallelism-adjusting units is disposed on the first chamber, and includes an adjustment shaft extending through the first chamber and connected to the press-bonding unit. The adjustment shaft includes an adjustment member located outside the first chamber and the closed space. A user is able to adjust a parallelism between the press-bonding unit and the carrier in an efficient and precise manner, from the adjustment member.

Abstract: The present disclosure provides a powder-atomic-layer-deposition device with knocker, which mainly includes a vacuum chamber, a shaft seal, a drive unit and a knocker. The drive unit is connected to the rear wall of the vacuum chamber via the shaft seal, for driving the vacuum chamber to rotate. The shaft seal includes an outer tube and an inner tube, wherein the inner tube is disposed within the containing space of the outer tube. The inner tube is disposed with a gas-extracting pipeline and a gas-inlet pipeline therein, wherein the gas-extracting pipeline is for gas extraction of the vacuum chamber, the gas-inlet pipeline is for transferring a precursor gas into the vacuum chamber. The knocker and the vacuum chamber are adjacent to each other, for knocking the vacuum chamber to prevent powders within the reacting space from sticking to the inner surface of the vacuum chamber.