Patents by Inventor Jing-Cheng Lin

Jing-Cheng Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210074683
    Abstract: An integrated fan out package on package architecture is utilized along with a reference via in order to provide a reference voltage that extends through the InFO-POP architecture. If desired, the reference via may be exposed and then connected to a shield coating that can be used to shield the InFO-POP architecture. The reference via may be exposed by exposing either a top surface or a sidewall of the reference via using one or more singulation processes.
    Type: Application
    Filed: November 16, 2020
    Publication date: March 11, 2021
    Inventors: Jing-Cheng Lin, Chen-Hua Yu, Po-Hao Tsai
  • Patent number: 10943873
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a conductive structure over the substrate. The semiconductor device structure includes first metal oxide fibers over the conductive structure. The semiconductor device structure includes a dielectric layer over the substrate and covering the conductive structure and the first metal oxide fibers. The dielectric layer fills gaps between the first metal oxide fibers.
    Type: Grant
    Filed: December 7, 2018
    Date of Patent: March 9, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jing-Cheng Lin, Chen-Hua Yu, Szu-Wei Lu, Yen-Yao Chi
  • Publication number: 20210057383
    Abstract: A method includes bonding a first and a second package component on a top surface of a third package component, and dispensing a polymer. The polymer includes a first portion in a space between the first and the third package components, a second portion in a space between the second and the third package components, and a third portion in a gap between the first and the second package components. A curing step is then performed on the polymer. After the curing step, the third portion of the polymer is sawed to form a trench between the first and the second package components.
    Type: Application
    Filed: November 10, 2020
    Publication date: February 25, 2021
    Inventors: Szu-Wei Lu, Ying-Da Wang, Li-Chung Kuo, Jing-Cheng Lin
  • Patent number: 10923431
    Abstract: A device includes an interposer, which includes a substrate having a top surface. An interconnect structure is formed over the top surface of the substrate, wherein the interconnect structure includes at least one dielectric layer, and metal features in the at least one dielectric layer. A plurality of through-substrate vias (TSVs) is in the substrate and electrically coupled to the interconnect structure. A first die is over and bonded onto the interposer. A second die is bonded onto the interposer, wherein the second die is under the interconnect structure.
    Type: Grant
    Filed: May 20, 2019
    Date of Patent: February 16, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Pin Hu, Chen-Hua Yu, Ming-Fa Chen, Jing-Cheng Lin, Jiun Ren Lai, Yung-Chi Lin
  • Publication number: 20210043547
    Abstract: Methods for forming a semiconductor device structure are provided. The method includes forming a conductive feature in a first wafer, and forming a first bonding layer over the conductive feature. The method includes forming a second bonding layer over a second wafer, and bonding the first wafer and the second wafer by bonding the first bonding layer and the second bonding layer. The method also includes forming a second transistor in a front-side of the second wafer, and after forming the second transistor in the front-side of the second wafer, forming a first TSV through the second wafer, wherein the first TSV stops at the conductive feature.
    Type: Application
    Filed: October 26, 2020
    Publication date: February 11, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Jing-Cheng LIN
  • Publication number: 20210043581
    Abstract: A semiconductor device has a conductive via laterally separated from the semiconductor, an encapsulant between the semiconductor device and the conductive via, and a mark. The mark is formed from characters that are either cross-free characters or else have a overlap count of less than two. In another embodiment the mark is formed using a wobble scan methodology. By forming marks as described, defects from the marking process may be reduced or eliminated.
    Type: Application
    Filed: October 26, 2020
    Publication date: February 11, 2021
    Inventors: Jing-Cheng Lin, Chen-Hua Yu, Po-Hao Tsai
  • Patent number: 10916450
    Abstract: A method includes forming a release film over a carrier, forming a metal post on the release film, encapsulating the metal post in an encapsulating material, performing a planarization on the encapsulating material to expose the metal post, forming a redistribution structure over the encapsulating material and the metal post, decomposing a first portion of the release film to separate a second portion of the release film from the carrier, and forming an opening in the release film to expose the metal post.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: February 9, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Ju Tsou, Chih-Wei Wu, Pu Wang, Szu-Wei Lu, Ying-Ching Shih, Jing-Cheng Lin
  • Patent number: 10916488
    Abstract: Semiconductor packages are provided. One of the semiconductor package includes a semiconductor die, a thermal conductive pattern, an encapsulant and a thermal conductive layer. The thermal conductive pattern is disposed aside the semiconductor die. The encapsulant encapsulates the semiconductor die and the thermal conductive pattern. The thermal conductive layer covers a rear surface of the semiconductor die, wherein the thermal conductive pattern is thermally coupled to the semiconductor die through the thermal conductive layer and electrically insulated from the semiconductor die.
    Type: Grant
    Filed: June 5, 2019
    Date of Patent: February 9, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jing-Cheng Lin, Szu-Wei Lu
  • Patent number: 10910267
    Abstract: A device includes a substrate, and an alignment mark including a conductive through-substrate via (TSV) penetrating through the substrate.
    Type: Grant
    Filed: June 22, 2020
    Date of Patent: February 2, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsin Chang, Fang Wen Tsai, Jing-Cheng Lin, Wen-Chih Chiou, Shin-Puu Jeng
  • Publication number: 20210028097
    Abstract: A method for forming a package structure may comprise applying a die and vias on a carrier having an adhesive layer and forming a molded substrate over the carrier and around the vias, and the ends of the vias and mounts on the die exposed. The vias may be in via chips with one or more dielectric layers separating the vias. The via chips 104 may be formed separately from the carrier. The dielectric layer of the via chips may separate the vias from, and comprise a material different than, the molded substrate. An RDL having RDL contact pads and conductive lines may be formed on the molded substrate. A second structure having at least one die may be mounted on the opposite side of the molded substrate, the die on the second structure in electrical communication with at least one RDL contact pad.
    Type: Application
    Filed: October 12, 2020
    Publication date: January 28, 2021
    Inventor: Jing-Cheng Lin
  • Publication number: 20210005464
    Abstract: An integrated circuit package and a method of forming the same are provided. A method includes forming a conductive column over a carrier. An integrated circuit die is attached to the carrier, the integrated circuit die being disposed adjacent the conductive column. An encapsulant is formed around the conductive column and the integrated circuit die. The carrier is removed to expose a first surface of the conductive column and a second surface of the encapsulant. A polymer material is formed over the first surface and the second surface. The polymer material is cured to form an annular-shaped structure. An inner edge of the annular-shaped structure overlaps the first surface in a plan view. An outer edge of the annular-shaped structure overlaps the second surface in the plan view.
    Type: Application
    Filed: September 21, 2020
    Publication date: January 7, 2021
    Inventors: Jing-Cheng Lin, Li-Hui Cheng, Po-Hao Tsai
  • Publication number: 20200411485
    Abstract: A chip package structure is provided. The chip package structure includes a redistribution structure including a dielectric structure, a redistribution line, and a seal ring structure. The redistribution line and the seal ring structure are in the dielectric structure, the seal ring structure continuously surrounds the redistribution line, the seal ring structure includes a first seal ring and a second seal ring over and electrically connected to the first seal ring, and the redistribution structure has a first sidewall, a first surface, and a second surface opposite to the first surface. The chip package structure includes a chip structure over the first surface. The chip package structure includes a ground bump over the second surface. The chip package structure includes a conductive shielding film covering the chip structure and the first sidewall of the redistribution structure.
    Type: Application
    Filed: September 14, 2020
    Publication date: December 31, 2020
    Inventors: Chen-Hua YU, An-Jhih SU, Jing-Cheng LIN, Po-Hao TSAI
  • Patent number: 10879194
    Abstract: A semiconductor device package includes a substrate, a semiconductor chip, a first ring structure and a second ring structure. The substrate includes a surface. The semiconductor chip is over the surface of the substrate. The first ring structure is over the surface of the substrate. The second ring structure is over the surface of the substrate, wherein the first ring structure is between the semiconductor chip and the second ring structure.
    Type: Grant
    Filed: May 25, 2017
    Date of Patent: December 29, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Jing-Cheng Lin, Li-Hui Cheng, Po-Hao Tsai, Jeh-Yin Chang, Li-Chung Kuo, Hsien-Ju Tsou, Yi Chou, Ying-Ching Shih, Szu-Wei Lu
  • Publication number: 20200402877
    Abstract: An embodiment is a method including: attaching a first die to a first side of a first component using first electrical connectors, attaching a first side of a second die to first side of the first component using second electrical connectors, attaching a dummy die to the first side of the first component in a scribe line region of the first component, adhering a cover structure to a second side of the second die, and singulating the first component and the dummy die to form a package structure.
    Type: Application
    Filed: September 4, 2020
    Publication date: December 24, 2020
    Inventors: Chen-Hua Yu, Wen-Hsin Wei, Chi-Hsi Wu, Shang-Yun Hou, Jing-Cheng Lin, Hsien-Pin Hu, Ying-Ching Shih, Szu-Wei Lu
  • Publication number: 20200402816
    Abstract: A method includes forming a release film over a carrier, attaching a device over the release film through a die-attach film, encapsulating the device in an encapsulating material, performing a planarization on the encapsulating material to expose the device, detaching the device and the encapsulating material from the carrier, etching the die-attach film to expose a back surface of the device, and applying a thermal conductive material on the back surface of the device.
    Type: Application
    Filed: August 31, 2020
    Publication date: December 24, 2020
    Inventors: Jing-Cheng Lin, Li-Hui Cheng, Po-Hao Tsai
  • Patent number: 10872850
    Abstract: A package structure includes a semiconductor device, a first redistribution line, a dielectric layer, a first conductive bump and a first sealing structure. The dielectric layer is over the first redistribution line and has a first opening therein. The first conductive bump is partially embedded in the first opening and electrically connected to the first redistribution line. The first sealing structure surrounds a bottom portion of the first conductive bump. The first sealing structure has a curved surface extending from an outer surface of the bottom portion of the first conductive bump to a top surface of the dielectric layer.
    Type: Grant
    Filed: June 16, 2017
    Date of Patent: December 22, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Li-Hui Cheng, Po-Hao Tsai, Jing-Cheng Lin
  • Patent number: 10867965
    Abstract: An embodiment is a method including bonding a first die to a first side of an interposer using first electrical connectors, bonding a second die to first side of the interposer using second electrical connectors, attaching a first dummy die to the first side of the interposer adjacent the second die, encapsulating the first die, the second die, and the first dummy die with an encapsulant, and singulating the interposer and the first dummy die to form a package structure.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ying-Ching Shih, Chi-Hsi Wu, Chen-Hua Yu, Chih-Wei Wu, Jing-Cheng Lin, Pu Wang, Szu-Wei Lu
  • Patent number: 10867897
    Abstract: A method of forming a PoP device comprises placing an adhesive layer on a carrier substrate, coupling a plurality of chip packages to the adhesive layer on the carrier substrate, placing a bonding layer on the chip packages, and coupling a plurality of chips to the bonding layer on the chip packages. The method further comprises injecting a molding compound to encapsulate the chip packages and the chips on the carrier substrate, grinding the molding compound to expose a plurality of connecting elements of the chips and a plurality of second connecting elements of the chip packages, forming a redistribution layer (RDL) on the molding compound and the exposed connecting elements and second connecting elements, forming a ball grid array (BGA) on the RDL, and de-bonding the carrier substrate.
    Type: Grant
    Filed: April 13, 2018
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chin-Chuan Chang, Jing-Cheng Lin, Nai-Wei Liu, Wan-Ting Shih
  • Patent number: 10861835
    Abstract: A package includes a first package including a device die, a molding compound molding the device die therein, a through-via penetrating through the molding compound, and a first plurality of Redistribution Lines (RDLs) and a second plurality of RDLs on opposite sides of the molding compound. The through-via electrically couples one of the first plurality of RDLs to one of the second plurality of RDLs. The package further includes a second package bonded to the first package, a spacer disposed in a gap between the first package and the second package, and a first electrical connector and a second electrical connector on opposite sides of the spacer. The first electrical connector and the second electrically couple the first package to the second package. The spacer is spaced apart from the first electrical connector and the second electrical connector.
    Type: Grant
    Filed: July 8, 2019
    Date of Patent: December 8, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jing-Cheng Lin, Chen-Hua Yu, Szu-Wei Lu, Shih Ting Lin, Shin-Puu Jeng
  • Publication number: 20200373264
    Abstract: An embodiment is a method including depositing a first dielectric layer over a molding compound and a chip and patterning a first opening in the first dielectric layer to expose a contact of the chip. A first metallization layer is deposited over the first dielectric layer and in the first opening, where a portion of the first metallization layer in the first opening has a flat top. A second dielectric layer is deposited over the first metallization layer and the first dielectric layer. A second metallization layer is deposited in a second opening in the second dielectric layer, where the second metallization layer does not have a flat top within the second opening.
    Type: Application
    Filed: August 10, 2020
    Publication date: November 26, 2020
    Inventors: Wan-Ting Shih, Nai-Wei Liu, Jing-Cheng Lin, Cheng-Lin Huang