Patents by Inventor Jing-Cheng Lin

Jing-Cheng Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11854877
    Abstract: Some embodiments of the present disclosure provide a semiconductor device. The semiconductor device includes: a bottom package; wherein an area of a contact surface between the conductor and the through via substantially equals a cross-sectional area of the through via, and the bottom package includes: a molding compound; a through via penetrating through the molding compound; a die molded in the molding compound; and a conductor on the through via. An associated method of manufacturing the semiconductor device is also disclosed.
    Type: Grant
    Filed: March 29, 2021
    Date of Patent: December 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Jing-Cheng Lin, Ying-Ching Shih, Pu Wang, Chen-Hua Yu
  • Patent number: 11848225
    Abstract: Methods and apparatus for pre-treating semiconductor wafers before edge trimming to enhance wafer edge quality prior to thinning the semiconductor wafers from an initial thickness, and increasing yield post-thinning of the pre-treated, edge trimmed semiconductor wafers. An apparatus includes a stage configured to receive one of a device wafer or a carrier wafer having a device wafer mounted thereto thereon, a laser tool located above the stage and oriented to direct a laser beam downwardly toward the stage, and a vertically movable blade rotatable about a horizontal axis along a radius from a vertical axis at a center of the device wafer and positionable proximate to and radially inward of an outer periphery of the device wafer.
    Type: Grant
    Filed: December 8, 2022
    Date of Patent: December 19, 2023
    Assignee: Micron Technology, Inc.
    Inventor: Jing-Cheng Lin
  • Patent number: 11846022
    Abstract: A thin-film-deposition machine includes a chamber, a carrier, an extraction ring and a dispensing unit. The chamber includes a containing space and an extraction channel disposed around the containing space. The extraction channel is partitioned into a first, a second and a third channel areas. The carrier is disposed within the containing space. The first channel area is connected to the third channel area via the second channel area. The third channel area is formed with a height greater than that of the first channel area. The extraction ring includes a plurality of extraction holes and a ring channel. The extraction holes are disposed around the carrier for extracting gas from the containing space to the extraction channel, sequentially via the extraction holes, the ring channel. Thereby an even and steady flow field can be formed above the carrier and the thickness uniformity of film deposition can be improved.
    Type: Grant
    Filed: January 5, 2022
    Date of Patent: December 19, 2023
    Assignee: SKY TECH INC.
    Inventors: Jing-Cheng Lin, Ta-Hao Kuo
  • Patent number: 11848247
    Abstract: A die includes a semiconductor substrate, a through-via penetrating through the semiconductor substrate, a seal ring overlying and connected to the through-via, and an electrical connector underlying the semiconductor substrate and electrically coupled to the seal ring through the through-via.
    Type: Grant
    Filed: June 1, 2021
    Date of Patent: December 19, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jing-Cheng Lin, Shih-Yi Syu
  • Patent number: 11842936
    Abstract: A method for forming an underfill structure and semiconductor packages including the underfill structure are disclosed. In an embodiment, the semiconductor package may include a package including an integrated circuit die; an interposer bonded to the integrated circuit die by a plurality of die connectors; and an encapsulant surrounding the integrated circuit die. The semiconductor package may further include a package substrate bonded to the interposer by a plurality of conductive connectors; a first underfill between the package and the package substrate, the first underfill having a first coefficient of thermal expansion (CTE); and a second underfill surrounding the first underfill, the second underfill having a second CTE less than the first CTE.
    Type: Grant
    Filed: July 26, 2021
    Date of Patent: December 12, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Wei Chen, Li-Chung Kuo, Ying-Ching Shih, Szu-Wei Lu, Jing-Cheng Lin, Long Hua Lee, Kuan-Yu Huang
  • Publication number: 20230382071
    Abstract: A bonding machine with horizontal correction function includes a first chamber, a second chamber, a pressing unit, a carrier, a plurality of level adjustment units, and a plurality of distance measuring units. The first chamber is configured to be connected to the second chamber to define an enclosed space therebetween. The pressing unit is disposed within the first chamber, and the carrier is disposed within the second chamber. The pressing unit faces the carrier and is configured to press the substrates placed on the carrier. The leveling units are disposed on the first chamber, and the distance measuring units are disposed on the second chamber. Each distance measuring unit is configured to project a detecting beam onto the pressing unit, to measure the level of the pressing unit so as to adjust the level of the pressing unit through the level adjustment unit.
    Type: Application
    Filed: May 25, 2022
    Publication date: November 30, 2023
    Inventors: JING-CHENG LIN, JUNG-HUA CHANG, MAO-CHAN CHANG
  • Publication number: 20230366090
    Abstract: A method for a deposition apparatus is disclosed. The deposition apparatus includes a chamber, a substrate carrier, a blocker and a cover ring. The cover ring is disposed on the blocker. The substrate carrier carries a wafer and moves with respect to the blocker. A position where the substrate carrier contacts the cover ring start is defined as a contact position, and a first position below the contact position and a second position above the contact position are also defined. When the reaching the first position, a movement speed of the substrate carrier is decreased, and the substrate carrier carries the cover ring to move away from the blocker. When reaching the second position, the movement speed of the substrate carrier away from the blocker is increased. Collision between the wafer and the deposition apparatus is eliminated to prevent undesired particles from occurring and the wafer from being damaged.
    Type: Application
    Filed: May 11, 2022
    Publication date: November 16, 2023
    Inventor: JING-CHENG LIN
  • Patent number: 11817437
    Abstract: A method includes forming an under bump metallization (UBM) layer over a dielectric layer, forming a redistribution structure over the UBM layer, disposing a semiconductor device over the redistribution structure, removing a portion of the dielectric layer to form an opening to expose the UBM layer, and forming a conductive bump in the opening such that the conductive bump is coupled to the UBM layer.
    Type: Grant
    Filed: November 1, 2021
    Date of Patent: November 14, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jing-Cheng Lin, Po-Hao Tsai
  • Publication number: 20230352323
    Abstract: A parallelism-adjustable bonding machine includes a first chamber, a second chamber, a press-bonding unit, a carrier and plural parallelism-adjusting units. The first chamber is configured to connect to the second chamber, so as to define a closed space therebetween. The press-bonding unit is disposed within the first chamber, and the carrier is disposed within the second chamber. The press-bonding unit is disposed to face the carrier configured to press and bond substrates placed on the carrier. Each of the parallelism-adjusting units is disposed on the first chamber, and includes an adjustment shaft extending through the first chamber and connected to the press-bonding unit. The adjustment shaft includes an adjustment member located outside the first chamber and the closed space. A user is able to adjust a parallelism between the press-bonding unit and the carrier in an efficient and precise manner, from the adjustment member.
    Type: Application
    Filed: April 27, 2022
    Publication date: November 2, 2023
    Inventors: JING-CHENG LIN, JUNG-HUA CHANG, MAO-CHAN CHANG
  • Patent number: 11791241
    Abstract: Methods for forming a semiconductor device structure are provided. The method includes forming a conductive feature in a first wafer, and forming a first bonding layer over the conductive feature. The method includes forming a second bonding layer over a second wafer, and bonding the first wafer and the second wafer by bonding the first bonding layer and the second bonding layer. The method also includes forming a second transistor in a front-side of the second wafer, and after forming the second transistor in the front-side of the second wafer, forming a first TSV through the second wafer, wherein the first TSV stops at the conductive feature.
    Type: Grant
    Filed: October 26, 2020
    Date of Patent: October 17, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Jing-Cheng Lin
  • Patent number: 11784094
    Abstract: The present disclosure provides a laser lift-off method for separating substrate and semiconductor-epitaxial structure, which includes: providing at least one semiconductor device, wherein the semiconductor device includes a substrate and at least one semiconductor-epitaxial structure disposed in a stack-up manner; irradiating a laser onto an edge area of the semiconductor device to separate portions of the substrate and the semiconductor-epitaxial structure in the edge area; and pressing against the edge area of the semiconductor device vis a pressing device, then irradiating the laser onto an inner area of the semiconductor device to separate portions of the substrate and the semiconductor-epitaxial structure in the inner area wherein gas is generated during separating the portions of the substrate and the semiconductor-epitaxial structure in the inner area and evacuated from the edge area, to prevent damage of the semiconductor-epitaxial structure during the separating process.
    Type: Grant
    Filed: March 5, 2021
    Date of Patent: October 10, 2023
    Assignee: SKY TECH INC.
    Inventors: Jing-Cheng Lin, Tsung-Hua Hsieh
  • Patent number: 11773319
    Abstract: The present disclosure provides a quantum dot particle with passivation layer, which mainly includes a one quantum dot (QD) particle, a first-passivation layer and a second-passivation layer, wherein the first-passivation layer is disposed on a surface of the QD particle, and the second-passivation layer is disposed on a surface of the first-passivation layer. A precursor chosen for forming the first-passivation layer does not cause damage to the QD particle. A precursor of the second-passivation layer includes a composition of trimethylaluminum (TMA) and water, or TMA and ozone, wherein a density of the second-passivation layer is greater than that of the first-passivation layer. The precursor of the second-passivation layer is kept out by the first-passivation layer, such that to prevent the precursor of the second-passivation layer from contacting the QD particle and causing deterioration thereto, and hence to improve a life cycle of the QD particle.
    Type: Grant
    Filed: September 2, 2021
    Date of Patent: October 3, 2023
    Assignee: SKY TECH INC.
    Inventors: Jing-Cheng Lin, Jung-Hua Chang
  • Patent number: 11776935
    Abstract: An integrated fan out package on package architecture is utilized along with a reference via in order to provide a reference voltage that extends through the InFO-POP architecture. If desired, the reference via may be exposed and then connected to a shield coating that can be used to shield the InFO-POP architecture. The reference via may be exposed by exposing either a top surface or a sidewall of the reference via using one or more singulation processes.
    Type: Grant
    Filed: June 29, 2022
    Date of Patent: October 3, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jing-Cheng Lin, Chen-Hua Yu, Po-Hao Tsai
  • Patent number: 11767591
    Abstract: A detachable atomic layer deposition apparatus for powders is disclosed, which includes a vacuum chamber, a shaft sealing device, and a driving unit. The driving unit is connected to the shaft sealing device. The vacuum chamber is fixed to one end of the shaft sealing device via at least one fixing member. The driving unit drives the vacuum chamber to rotate via the shaft sealing device to agitate the powders in a reaction space of the vacuum chamber to facilitate the formation of thin films with uniform thickness on the surface of the powders. In addition, the vacuum chamber can be removed from the shaft sealing device for users to take out the powders from the vacuum chamber and clean the vacuum chamber, thereby improving the convenience in usage.
    Type: Grant
    Filed: May 30, 2021
    Date of Patent: September 26, 2023
    Assignee: SKY TECH INC.
    Inventors: Jing-Cheng Lin, Jung-Hua Chang, Chia-Cheng Ku
  • Publication number: 20230295802
    Abstract: The invention provides a vibrating deposition device, which includes a vacuum chamber, a fixed rod and a powder tank. The vacuum chamber includes an inner side surface, and a plurality of bulges and notches are arranged on the inner side surface. The fixed rod and the powder tank are arranged in an accommodating space of the vacuum chamber, wherein the powder tank is used for accommodating powders and contacts the inner side surface of the vacuum chamber through a protruding unit. When the vacuum chamber rotates, the protruding unit will be displaced between the bulge and the notch, and the powder tank will be displaced up and down relative to the vacuum chamber to vibrate powders in the powder tank, so that a uniform film will be formed on the surface of powders.
    Type: Application
    Filed: March 16, 2022
    Publication date: September 21, 2023
    Inventor: JING-CHENG LIN
  • Patent number: 11764139
    Abstract: A semiconductor device includes a substrate, a first redistribution layer (RDL) over a first side of the substrate, one or more semiconductor dies over and electrically coupled to the first RDL, and an encapsulant over the first RDL and around the one or more semiconductor dies. The semiconductor device also includes connectors attached to a second side of the substrate opposing the first side, the connectors being electrically coupled to the first RDL. The semiconductor device further includes a polymer layer on the second side of the substrate, the connectors protruding from the polymer layer above a first surface of the polymer layer distal the substrate. A first portion of the polymer layer contacting the connectors has a first thickness, and a second portion of the polymer layer between adjacent connectors has a second thickness smaller than the first thickness.
    Type: Grant
    Filed: July 12, 2021
    Date of Patent: September 19, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jing-Cheng Lin, Chi-Hsi Wu, Chen-Hua Yu, Po-Hao Tsai
  • Patent number: 11756802
    Abstract: A method includes forming a release film over a carrier, attaching a device over the release film through a die-attach film, encapsulating the device in an encapsulating material, performing a planarization on the encapsulating material to expose the device, detaching the device and the encapsulating material from the carrier, etching the die-attach film to expose a back surface of the device, and applying a thermal conductive material on the back surface of the device.
    Type: Grant
    Filed: July 27, 2022
    Date of Patent: September 12, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jing-Cheng Lin, Li-Hui Cheng, Po-Hao Tsai
  • Patent number: 11742310
    Abstract: A method of manufacturing a semiconductor device includes providing a substrate, disposing a plurality of pads on a surface of the substrate, disposing a plurality of conductive bumps on the plurality of pads correspondingly; disposing a solder bracing material surrounding the plurality of conductive bumps and over the surface of the substrate after the disposing of the plurality of conductive bumps, wherein the solder bracing material is in contact with a sidewall of each of the plurality of pads and the plurality of conductive bumps; disposing a release film on the solder bracing material and the plurality of conductive bumps; and removing the release film to form a rough surface of the solder bracing material. The rough surface of the solder bracing material includes a plurality of protruded portions and a plurality of recessed portions.
    Type: Grant
    Filed: May 4, 2021
    Date of Patent: August 29, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Jing-Cheng Lin, Feng-Cheng Hsu
  • Patent number: 11739423
    Abstract: An atomic layer deposition apparatus for coating particles is disclosed. The atomic layer deposition apparatus includes a vacuum chamber, a shaft sealing device, and a driving unit. The driving unit is connected to and drives the vacuum chamber to rotate through the shaft sealing device. The vacuum chamber includes a reaction space for accommodating a plurality of particles, wherein the reaction space has a polygonal columnar shape or a wavy circular columnar shape. An air extraction line and an air intake line are fluidly connected to the vacuum chamber, and the air intake line is used to transport a precursor gas and a non-reactive gas to the reaction space. Through the special shape of the reaction space together with the non-reactive gas, the particles in the reaction space can be effectively stirred to form a thin film with a uniform thickness on the surface of each particle.
    Type: Grant
    Filed: March 11, 2021
    Date of Patent: August 29, 2023
    Assignee: SKY TECH INC.
    Inventors: Jing-Cheng Lin, Jung-Hua Chang, Ta-Hao Kuo, Chia-Cheng Ku
  • Patent number: 11735456
    Abstract: The present disclosure is an alignment mechanism of a bonding machine, in particular an alignment mechanism of a wafer bonding machine, which mainly has a support pedestal, at least three first alignment pins, and at least three second alignment pins, a first cam and a second cam. When the first cam rotates relative to the support pedestal, it will drive the first alignment pin to move relative to the support pedestal to position the first substrate on the support pedestal. When the second cam rotates relative to the support pedestal, it drives the second alignment pin to move relative to the support pedestal to position the second substrate above the first substrate, so that the second substrate is aligned with the first substrate to facilitate bonding the first substrate and the second substrate.
    Type: Grant
    Filed: March 11, 2021
    Date of Patent: August 22, 2023
    Assignee: SKY TECH INC.
    Inventors: Jing-Cheng Lin, Jung-Hua Chang, Mao-chan Chang