Abstract: A testing device and a testing method for an optical film are disclosed. The testing device includes a carrier having a cavity, wherein the cavity is an enclosed space; a test condition providing module disposed in the enclosed space; wherein the optical film is disposed in the enclosed space and the test condition providing module is configured for providing a test condition simulating a real environment in a liquid crystal display module for the optical film. The testing device for an optical film is configured for testing the optical film to be tested.

Abstract: A method of forming self-aligned STI regions extending over portions of a Si substrate to enable the subsequent formation of epitaxially grown embedded S/D regions without using a lithography mask and the resulting device are provided. Embodiments include forming a STI etch mask with laterally separated openings over a Si substrate; forming shallow trenches into the Si substrate through the openings; forming first through fourth oxide spacers on opposite sidewalls of the shallow trenches and the openings; forming a deep STI trench between the first and second oxide spacers and between the third and fourth oxide spacers down into the Si substrate; forming a STI oxide layer over the first through fourth oxide spacers and a portion of the STI etch mask, the STI oxide layer filling the deep STI trenches; and planarizing the STI oxide layer down to the portion of the STI etch mask.

Abstract: The invention provides combinations comprising a MERTK inhibitor, or a pharmaceutically acceptable salt thereof, and an EGFR inhibitor and methods of use thereof, including methods of treating disorders such as cancer.

Abstract: Embodiments of the present invention provide a metal gate structure and method of formation. In the replacement metal gate (RMG) process flow, the gate cut process is performed after the metal gate is formed. This allows for a reduced margin between the end of the gate and an adjacent fin. It enables a thinner sacrificial layer on top of the dummy gate, since the gate cut step is deferred. The thinner sacrificial layer improves device quality by reducing the adverse effect of shadowing during implantation. Furthermore, in this process flow, the work function metal layer is terminated along the semiconductor substrate by a capping layer, which reduces undesirable shifts in threshold voltage that occurred in prior methods and structures.

Abstract: Provided are approaches for forming gate and source/drain (S/D) contacts. Specifically, a gate contact opening is formed over at least one of a set of gate structures, a set of S/D contact openings is formed over fins of the semiconductor device, and a metal material is deposited over the semiconductor device to form a gate contact within the gate contact opening and a set of S/D contacts within the set of S/D contact openings. In one approach, nitride remains between the gate contact and at least one of the S/D contacts. In another approach, the device includes merged gate and S/D contacts. This approach provides selective etching to partition areas where oxide will be further removed selectively to nitride to create cavities to metallize and create contact to the S/D, while isolation areas between contact areas are enclosed in nitride and do not get removed during the oxide etch.

Abstract: Embodiments of the present invention provide a metal gate structure and method of formation. In the replacement metal gate (RMG) process flow, the gate cut process is performed after the metal gate is formed. This allows for a reduced margin between the end of the gate and an adjacent fin. It enables a thinner sacrificial layer on top of the dummy gate, since the gate cut step is deferred. The thinner sacrificial layer improves device quality by reducing the adverse effect of shadowing during implantation. Furthermore, in this process flow, the work function metal layer is terminated along the semiconductor substrate by a capping layer, which reduces undesirable shifts in threshold voltage that occurred in prior methods and structures.

Abstract: A method of forming self-aligned STI regions extending over portions of a Si substrate to enable the subsequent formation of epitaxially grown embedded S/D regions without using a lithography mask and the resulting device are provided. Embodiments include forming a STI etch mask with laterally separated openings over a Si substrate; forming shallow trenches into the Si substrate through the openings; forming first through fourth oxide spacers on opposite sidewalls of the shallow trenches and the openings; forming a deep STI trench between the first and second oxide spacers and between the third and fourth oxide spacers down into the Si substrate; forming a STI oxide layer over the first through fourth oxide spacers and a portion of the STI etch mask, the STI oxide layer filling the deep STI trenches; and planarizing the STI oxide layer down to the portion of the STI etch mask.

Abstract: A testing device and a testing method for an optical film are disclosed. The testing device includes a carrier having a cavity, wherein the cavity is an enclosed space; a test condition providing module disposed in the enclosed space; wherein the optical film is disposed in the enclosed space and the test condition providing module is configured for providing a test condition simulating a real environment in a liquid crystal display module for the optical film. The testing device for an optical film is configured for testing the optical film to be tested.

Abstract: A method of forming a nanowire device includes patterning a plurality of semiconductor material layers such that each layer has first and second exposed end surfaces. The method further includes forming doped extension regions in the first and second exposed end surfaces of the semiconductor material layers. The method further includes, after forming the doped extension regions, forming epi semiconductor material in source and drain regions of the device.

Abstract: A method of forming a nanowire device includes forming semiconductor material layers above a semiconductor substrate, forming a gate structure above the semiconductor material layers, forming a first sidewall spacer adjacent to the gate structure and forming a second sidewall spacer adjacent to the first sidewall spacer. The method further includes patterning the semiconductor material layers such that each layer has first and second exposed end surfaces. The gate structure, the first sidewall spacer, and the second sidewall spacer are used in combination as an etch mask during the patterning process. The method further includes removing the first and second sidewall spacers, thereby exposing at least a portion of the patterned semiconductor material layers. The method further includes forming doped extension regions in at least the exposed portions of the patterned semiconductor material layers after removing the first and second sidewall spacers.

Abstract: An improved semiconductor structure and methods of fabrication that provide improved transistor contacts in a semiconductor structure are provided. A set of masks is formed over a portion of the semiconductor structure. Each mask in this set of masks covers at least one source/drain (s/d) contact location. An oxide layer is removed from remainder portions of the semiconductor structure that are not covered by the set of masks. Then an opposite-mask fill layer is formed in the remainder portions from which the oxide layer was removed. The oxide layer is then removed from the remainder of the semiconductor structure, i.e., the portion previously covered by the set of masks and contacts are formed to the at least s/d contact location in the recesses formed by the removal of the remainder of the oxide layer.

Abstract: Methods are presented for facilitating fabrication of a semiconductor device, such as a gate-all-around nanowire field-effect transistor. The methods include, for instance: providing at least one stack structure including at least one layer or bump extending above the substrate structure; selectively oxidizing at least a portion of the at least one stack structure to form at least one nanowire extending within the stack structure(s) surrounded by oxidized material of the stack structure(s); and removing the oxidized material from the stack structure(s), exposing the nanowire(s). This selectively oxidizing may include oxidizing an upper portion of the substrate structure, such as an upper portion of one or more fins supporting the stack structure(s) to facilitate full 360° exposure of the nanowire(s). In one embodiment, the stack structure includes one or more diamond-shaped bumps or ridges.

Abstract: Integrated circuits and methods for producing the same are provided. A method for producing an integrated circuit includes forming a layered fin overlying a substrate, where the layered fin includes an SiGe layer and an Si layer. The SiGe layer and the Si layer alternate along a height of the layered fin. A dummy gate is formed overlying the substrate and the layered fin, and a source and a drain area formed in contact with the layered fin. The dummy gate is removed to expose the SiGe layer and the Si layer, and the Si layer is removed to produce an SiGe nanowire. A high K dielectric layer that encases the SiGe nanowire between the source and the drain is formed, and a replacement metal gate is formed so that the replacement metal gate encases the high K dielectric layer and the SiGe nanowire between the source and drain.

Abstract: An improved semiconductor structure and methods of fabrication that provide improved transistor contacts in a semiconductor structure are provided. A set of masks is formed over a portion of the semiconductor structure. Each mask in this set of masks covers at least one source/drain (s/d) contact location. An oxide layer is removed from remainder portions of the semiconductor structure that are not covered by the set of masks. Then an opposite-mask fill layer is formed in the remainder portions from which the oxide layer was removed. The oxide layer is then removed from the remainder of the semiconductor structure, i.e., the portion previously covered by the set of masks and contacts are formed to the at least s/d contact location in the recesses formed by the removal of the remainder of the oxide layer.

Abstract: A tunnel-effect transistor the drain region of which includes a first zone doped with a doping of a first type, and a second zone doped with a doping of a second type forming a junction with the first zone.

Abstract: Integrated circuits and methods for producing the same are provided. A method for producing an integrated circuit includes forming a layered fin overlying a substrate, where the layered fin includes an SiGe layer and an Si layer. The SiGe layer and the Si layer alternate along a height of the layered fin. A dummy gate is formed overlying the substrate and the layered fin, and a source and a drain area formed in contact with the layered fin. The dummy gate is removed to expose the SiGe layer and the Si layer, and the Si layer is removed to produce an SiGe nanowire. A high K dielectric layer that encases the SiGe nanowire between the source and the drain is formed, and a replacement metal gate is formed so that the replacement metal gate encases the high K dielectric layer and the SiGe nanowire between the source and drain.

Abstract: Methods are presented for facilitating fabrication of a semiconductor device, such as a gate-all-around nanowire field-effect transistor. The methods include, for instance: providing at least one stack structure including at least one layer or bump extending above the substrate structure; selectively oxidizing at least a portion of the at least one stack structure to form at least one nanowire extending within the stack structure(s) surrounded by oxidized material of the stack structure(s); and removing the oxidized material from the stack structure(s), exposing the nanowire(s). This selectively oxidizing may include oxidizing an upper portion of the substrate structure, such as an upper portion of one or more fins supporting the stack structure(s) to facilitate full 360° exposure of the nanowire(s). In one embodiment, the stack structure includes one or more diamond-shaped bumps or ridges.

Abstract: Embodiments of the present invention provide a fin-type field effect transistor (finFET) with confined epitaxy. A protective layer is formed on a fin. The protective layer is recessed to expose the fin top. A fin cavity is formed in the fin. An epitaxial region is formed in the fin cavity. The epitaxial region has a confined portion and a diamond-shaped portion, resulting in increased epitaxial volume. The increased epitaxial volume can result in enhanced carrier mobility and improved device performance.

Abstract: A method of forming a nanowire device includes forming semiconductor material layers above a semiconductor substrate, forming a gate structure above the semiconductor material layers, forming a first sidewall spacer adjacent to the gate structure and forming a second sidewall spacer adjacent to the first sidewall spacer. The method further includes patterning the semiconductor material layers such that each layer has first and second exposed end surfaces. The gate structure, the first sidewall spacer, and the second sidewall spacer are used in combination as an etch mask during the patterning process. The method further includes removing the first and second sidewall spacers, thereby exposing at least a portion of the patterned semiconductor material layers. The method further includes forming doped extension regions in at least the exposed portions of the patterned semiconductor material layers after removing the first and second sidewall spacers.

Abstract: A method of forming a nanowire device includes patterning a plurality of semiconductor material layers such that each layer has first and second exposed end surfaces. The method further includes forming doped extension regions in the first and second exposed end surfaces of the semiconductor material layers. The method further includes, after forming the doped extension regions, forming epi semiconductor material in source and drain regions of the device.