Abstract: A p-type FinFET has an oxygen reservoir disposed on the gate stack. The oxygen reservoir provides an oxygen rich environment during processing steps of manufacturing the device to help the work function metal retain or obtain oxygen to maintain or increase the work function and keep the Vth of the device lower.

Abstract: A method of forming a complementary metal oxide semiconductor (CMOS) device is provided. The method includes forming a separate gate structure on each of a pair of vertical fins, wherein the gate structures include a gate dielectric layer and a gate metal layer, and forming a protective liner layer on the gate structures. The method further includes heat treating the pair of gate structures, and replacing the protective liner layer with an encapsulation layer. The method further includes exposing a portion of the gate dielectric layer by recessing the encapsulation layer. The method further includes forming a top source/drain on the top surface of one of the pair of vertical fins, and subjecting the exposed portion of the gate dielectric layer to a second heat treatment conducted in an oxidizing atmosphere.

Abstract: A semiconductor structure and formation thereof. The semiconductor structure including: a nano-sheet field-effect transistor; a layer of support material that is located beneath a stack of nano-sheets that are included in the nano-sheet field-effect transistor; and a vertical support that is affixed to a stack of nano-sheets, wherein the vertical support (i) has an end that is affixed to the layer of support material and (ii) a side that is a affixed to at least one nano-sheet of the stack of nano-sheets.

Abstract: A first fin field effect transistor (FinFET) has an internal source/drain (S/D) with a facetted face that is connected to a dielectric side of a first RRAM. A second FinFET and RRAM structure are also disclosed. In some embodiments, an electrode contact side of each RRAM is connected in common to form a 2T2R device. The locations of one or more electrode points on the diamond-shaped, facetted surface of the bottom electrode accurately position electric fields through the dielectric to accurately and repeatably locate where the filaments/current paths are formed (or reset) through the RRAM dielectric. Material selection and accurate thickness of the RRAM dielectric determine the voltage at which the filaments/current paths are formed (or reset).

Abstract: A method is presented for triggering asymmetric threshold voltage along a channel of a vertical transport field effect transistor (VTFET). The method includes constructing a first set fins from a first material, constructing a second set of fins from a second material, forming a source region between the first set of fins, and forming a drain region between the second set of fins, the source region composed of a different material than the drain region. The method further includes depositing a first high-k metal gate over the first set of fins and depositing a second high-k metal gate over the second set of fins, the second high-k metal gate being different than the first high-k metal gate such that the asymmetric threshold voltage is present along the channel of the VTFET in a region defined at the bottom of the first and second set of fins.

Abstract: A method of forming a nanosheet field effect transistor device is provided. The method includes forming a stack of alternating sacrificial layer segments and nanosheet layer segments on a substrate. The method further includes removing the sacrificial layer segments to form channels on opposite sides of the nanosheet layer segments. The method further includes depositing a gate dielectric layer around each of the nanosheet layer segments, and forming a work function material block on the gate dielectric layer to form a gate-all-around structure on the nanosheet layer segments. The method further includes forming a capping layer on the work function material block.

Abstract: Vertical transport field effect transistors (FETs) having improved device performance are provided. Notably, vertical transport FETs having a gradient threshold voltage are provided. The gradient threshold voltage is provided by introducing a threshold voltage modifying dopant into a physically exposed portion of a metal gate layer composed of an n-type workfunction TiN. The threshold voltage modifying dopant changes the threshold voltage of the original metal gate layer.

Abstract: Parasitic transistor formation under a semiconductor containing nanosheet device is eliminated by forming an airgap between the source/drain regions of the semiconductor containing nanosheet device and the semiconductor substrate. The airgap is created by forming a sacrificial germanium-containing semiconductor material at the bottom of the source/drain regions prior to the epitaxial growth of the source/drain regions from physically exposed sidewalls of each semiconductor channel material nanosheet of a nanosheet material stack. After inner dielectric spacer formation, the sacrificial germanium-containing semiconductor material can be reflown to seal any possible openings to the semiconductor substrate. The source/drain regions are then epitaxially grown and thereafter, the sacrificial germanium-containing semiconductor material is removed from the structure creating the airgap between the source/drain regions of the semiconductor containing nanosheet device and the semiconductor substrate.

Abstract: Provided is a nanosheet semiconductor device. In embodiments of the invention, the nanosheet semiconductor device includes a channel nanosheet formed over a substrate. The nanosheet semiconductor device includes a buffer layer formed between the substrate and the channel nanosheet. The buffer layer has a lower conductivity than the channel nanosheet.

Abstract: A FinFET having an asymmetric threshold voltage distribution is provided by forming a halo ion implantation region in a semiconductor fin, and in close proximity to a source region, of the FinFET. The halo ion implantation region is self-aligned to an outermost sidewall surface of the functional gate structure of the FinFET and it has a higher dopant concentration than the remaining portion of the channel region.

Abstract: A cross-point memory is provided that enables the use of complementary pass transistors as selection devices in a dense memory array. The density impact of doubling the transistor count and the additional lines required for addressing the array is minimized by stacking the memory elements on vertical transistors with shared transistor bodies (i.e., semiconductor material pillars) and shared wordlines.

Abstract: A method is presented for reducing external resistance of a vertical field-effect-transistor (FET). The method includes forming a plurality of fins over a sacrificial layer disposed over a substrate, selectively removing the sacrificial layer to form an etch stop layer in direct contact with the substrate, disposing embedded bottom source/drain regions between a bottom portion of the plurality of fins and the etch stop layer, disposing encapsulation layers over the plurality of fins, recessing at least one of the encapsulation layers to expose top portions of the plurality of fins, forming top spacers adjacent the top portions of the plurality of fins, and forming top source/drain regions over the top portions of the plurality of fins.

Abstract: A method of forming a source/drain contact is provided. The method includes forming a sacrificial layer on a source/drain, and depositing an oxidation layer on the sacrificial layer. The method further includes heat treating the oxidation layer and the sacrificial layer to form a modified sacrificial layer. The method further includes forming a protective liner on the modified sacrificial layer, and depositing an interlayer dielectric layer on the protective liner. The method further includes forming a trench in the interlayer dielectric layer that exposes a portion of the protective liner.

Abstract: A method for forming a nanosheet semiconductor device includes forming a nanosheet stack comprising channel nanosheets. The method includes depositing silicon on the nanosheet stack, the silicon completely filling a space between adjacent channel nanosheets. The method includes etching the silicon. The method includes exposing the nanosheet stack to a gas phase heat treatment.

Abstract: Semiconductor devices and methods of forming the same include forming an inner spacer on a semiconductor fin. Two outer spacers are formed around the inner spacer, with one outer spacer being in contact with the inner spacer and with the other outer spacer being separated from the inner spacer by a gap. A dipole-forming layer is formed on the semiconductor fin in the gap. The inner spacer is etched away. A gate stack is formed on the semiconductor fin, between the outer spacers.

Abstract: A method of forming a source/drain contact is provided. The method includes forming a sacrificial layer on a source/drain, and depositing an oxidation layer on the sacrificial layer. The method further includes heat treating the oxidation layer and the sacrificial layer to form a modified sacrificial layer. The method further includes forming a protective liner on the modified sacrificial layer, and depositing an interlayer dielectric layer on the protective liner. The method further includes forming a trench in the interlayer dielectric layer that exposes a portion of the protective liner.

Abstract: A self-limiting etch is used to provide a semiconductor base located between a semiconductor substrate and a semiconductor fin. The semiconductor base has an upper portion, a lower portion and a midsection. The midsection has a narrower width than the lower and upper portions. A bottom source/drain structure is grown from surfaces of the semiconductor substrate and the semiconductor base. The bottom source/drain structure has a tip region that contacts the midsection of the semiconductor base. The bottom source/drain structures on each side of the semiconductor fin are in close proximity to each other and they have increased volume. Reduced access resistance may also be achieved since the bottom source/drain structure has increased volume.

Abstract: An I/O device nanosheet material stack of suspended semiconductor channel material nanosheets is provided above a semiconductor substrate. A physically exposed portion of each suspended semiconductor channel material nanosheet is thinned to increase the inter-nanosheet spacing between each vertically stacked semiconductor channel material nanosheet. An I/O device functional gate structure is formed wrapping around the thinned portion of each suspended semiconductor channel material nanosheet.

Abstract: A semiconductor structure containing a gate-all-around nanosheet field effect transistor having a self-limited inner spacer composed of a rare earth doped germanium dioxide that provides source/drain isolation between rare earth metal silicide ohmic contacts is provided.

Abstract: A semiconductor structure including vertically stacked n-type field effect transistors (nFETs) and p-type field effect transistors (pFETs) containing suspended semiconductor channel material nanosheets having an isolation layer located between a pFET source/drain (S/D) structure and an nFET S/D region is provided together with a method of forming such a structure. The pFET S/D structure includes a pFET S/D SiGe region having a first germanium content and an overlying SiGe region having a second germanium content that is greater than the first germanium content.