Abstract: Embodiments of the present invention are directed to fabrication method and resulting structures for vertical tunneling field effect transistors (VFETs) having an oxygen vacancy passivating bottom spacer. In a non-limiting embodiment of the invention, a first semiconductor fin is formed in a first region of a substrate and a second semiconductor fin is formed in a second region of the substrate. A bilayer bottom spacer is formed in direct contact with sidewalls of the semiconductor fins. The bilayer bottom spacer includes a first layer and an oxygen-donating second layer positioned on the first layer. A first dielectric film is formed on the sidewalls of the first semiconductor fin. The first dielectric film terminates on the first layer. A second dielectric film is formed on the sidewalls of the second semiconductor fin. The second dielectric film extends onto a surface of the oxygen-donating second layer.

Abstract: A method is presented for triggering asymmetric threshold voltage along a channel of a vertical transport field effect transistor (VTFET). The method includes constructing a first set fins from a first material, constructing a second set of fins from a second material, forming a source region between the first set of fins, and forming a drain region between the second set of fins, the source region composed of a different material than the drain region. The method further includes depositing a first high-k metal gate over the first set of fins and depositing a second high-k metal gate over the second set of fins, the second high-k metal gate being different than the first high-k metal gate such that the asymmetric threshold voltage is present along the channel of the VTFET in a region defined at the bottom of the first and second set of fins.

Abstract: A semiconductor structure and formation thereof. The semiconductor structure including: a nano-sheet field-effect transistor; a layer of support material that is located beneath a stack of nano-sheets that are included in the nano-sheet field-effect transistor; and a vertical support that is affixed to a stack of nano-sheets, wherein the vertical support (i) has an end that is affixed to the layer of support material and (ii) a side that is a affixed to at least one nano-sheet of the stack of nano-sheets.

Abstract: Semiconductor devices and methods of forming the same include forming a stack of alternating first and second sacrificial layers. The first sacrificial layers are recessed relative to the second sacrificial layers. Replacement channel layers are grown from sidewalls of the first sacrificial layers. A first source/drain region is grown from the replacement channel layer. The recessed first sacrificial layers are etched away. A second source/drain region is grown from the replacement channel layer. The second sacrificial layers are etched away. A gate stack is formed between and around the replacement channel layers.

Abstract: A method of forming a nanosheet device is provided. The method includes forming two amorphous source/drain fills on a substrate and one or more semiconductor nanosheet layers between the two amorphous source/drain fills. The method further includes forming a gate dielectric layer on exposed portions of the one or more semiconductor nanosheet layers. The method further includes forming a protective capping layer on the gate dielectric layer, and subjecting the two amorphous source/drain fills to a recrystallization treatment to cause a phase change from the amorphous state to a single crystal or poly-crystalline phase.

Abstract: A method for making first and second superimposed transistors, including: making, on a substrate, a stack of several semiconducting nanowires; etching a first nanowire so that a remaining portion of the first nanowire forms a channel of the first transistor; etching a second nanowire arranged between the substrate and the first nanowire, so that a remaining portion of the second nanowire forms a channel of the second transistor and has a greater length than that of the remaining portion of the first nanowire; making second source and drain regions in contact with ends of the remaining portion of the second nanowire; depositing a first dielectric encapsulation layer covering the second source and drain regions and forming vertical insulating portions; making first source and drain regions in contact with ends of the remaining portion of the first nanowire and insulated from the second source and drain regions by the vertical insulating portions.

Abstract: A method for fabricating stacked resistive memory with individual switch control is provided. The method includes forming a first random access memory (ReRAM) device. The method further includes forming a second ReRAM device in a stacked nanosheet configuration on the first ReRAM device. The method also includes forming separate gate contacts for the first ReRAM device and the second ReRAM device.

Abstract: Semiconductor devices and methods of forming the same include forming first recesses in a first stack of alternating sacrificial layers and channel layers. A first inner spacer sub-layer is formed in the first recesses from a first dielectric material. A second inner spacer sub-layer is formed in the first recesses from a second dielectric material, different from the first dielectric material. The sacrificial layers and the first inner spacer sub-layer are replaced with a gate stack in contact with the second inner spacer sub-layer.

Abstract: A semiconductor structure including a nanosheet stack on a silicon germanium on insulator substrate, the nanosheet stack including alternating layers of a sacrificial semiconductor material and a semiconductor channel material vertically aligned and stacked one on top of another, a gate conductor orthogonal to the nanosheet stack and wrapping around the semiconductor channel material layers of the nanosheet stack, and a gate contact on the gate conductor layer adjacent to the nanosheet stack.

Abstract: Embodiments of the invention include a method for fabricating a semiconductor device and the resulting structure. A stack of alternating nanosheets of sacrificial semiconductor material nanosheets and semiconductor material nanosheets located on a surface of a substrate are provided, wherein a sacrificial gate structure and a dielectric spacer material layer straddle over the nanosheet stack. End portions of each of the sacrificial semiconductor material nanosheets are recessed. A dielectric spacer is formed within each recess. Doped semiconductor portions are formed on the physically exposed sidewalls of each semiconductor material nanosheet and on the surface of the substrate. The semiconductor structure is thermally annealed. The sacrificial gate, each sacrificial semiconductor material nanosheet, and the dielectric spacer are each removed.

Abstract: A method of forming a semiconductor device that includes forming an inner dielectric spacer and outer dielectric spacer combination structure on a sacrificial gate structure that is present on a fin structure, wherein the inner dielectric spacer and outer dielectric spacer combination structure separates source and drain regions from the sacrificial gate structure. The method further includes removing the inner sidewall dielectric spacer; and forming a channel epitaxial wrap around layer on the portion of the fin structure that is exposed by removing the inner sidewall dielectric spacer. The method further includes removing the sacrificial gate structure to provide a gate opening to a channel portion of the fin structure, wherein the gate opening exposes the channel epitaxial wrap around layer; and forming a functional gate structure within the gate opening.

Abstract: Devices and methods for a vertical field effect transistor (VTFET) semiconductor device include recessing a gate dielectric and a gate conductor of a vertical gate structure below a top of a vertical fin to form openings between the top of the vertical fin and an etch stop layer, the top of the vertical fin being opposite to a substrate at a bottom of the vertical fin. A spacer material is deposited in the openings to form a spacer corresponding to each of the openings. Each spacer is recessed below the top of the vertical fin. A top spacer is selectively deposited in each of the openings to line the etch stop layer and the spacer such that the top of the vertical fin is exposed above the top spacer and the spacer is covered by the top spacer. A source/drain region is formed on the top of the vertical fin.

Abstract: A method for fabricating a semiconductor device including vertical transistors having uniform channel length includes defining a channel length of at least one first fin formed on a substrate in a first device region and a channel length of at least one second fin formed on the substrate in a second device region. Defining the channel lengths includes creating at least one divot in the second device region. The method further includes modifying the channel length of the at least one second fin to be substantially similar to the channel length of the at least one first fin by filling the at least one divot with additional gate conductor material.

Abstract: A method is presented for attaining different gate threshold voltages across a plurality of field effect transistor (FET) devices. The method includes forming first, second, and third nanosheet stacks, removing sacrificial layers of the first, second, and third nanosheet stacks, and depositing an interfacial layer and a high-k layer within the first, second, and third nanosheet stacks. The method further includes depositing a first work function metal (WFM) layer within the first nanosheet stack having a first thickness, depositing a second WFM layer within the second nanosheet stack having a second thickness, wherein the second thickness is greater than the first thickness, depositing a third WFM layer within the third nanosheet stack having a third thickness, wherein the third thickness is greater than the second thickness, depositing a dipole material, and diffusing the dipole material into the IL to provide different gate threshold voltages for the plurality of FET devices.

Abstract: A method is presented for reducing parasitic capacitance. The method includes forming a p-type epitaxial region and an n-type epitaxial region over a substrate, depositing an epitaxial growth over the p-type epitaxial region and the n-type epitaxial region, depositing a first dielectric between the p-type epitaxial region and the n-type epitaxial region such that an airgap is defined therebetween, and selectively removing the epitaxial growth to expose top surfaces of the p-type and n-type epitaxial regions. The method further includes depositing a second dielectric in direct contact with the exposed top surfaces of the p-type and n-type epitaxial regions, selectively etching the first and second dielectrics to form a strapped contact, and applying a metallization layer over the strapped contact.

Abstract: A method is presented for reducing sagging effects in nanosheet devices. The method includes forming at least two nanosheet structures over a substrate, wherein each nanosheet structure includes alternating layers of a first semiconductor material and a second semiconductor material, depositing a dielectric layer over the at least two nanosheet structures, depositing a dummy gate over the dielectric layer, etching the first semiconductor material to create voids filled with inner spacers, removing the dummy gate and the dielectric layer such that a supporting dielectric section remains between the at least two nanosheet structures, and removing the etched first semiconductor material such that a supporting structure is defined including the supporting dielectric section and the second semiconductor material.

Abstract: A semiconductor structure includes a first field-effect transistor disposed on a substrate. The first field-effect transistor includes a stack of nanosheet layers, a first gate, and a first source/drain region. The semiconductor structure further includes a second field-effect transistor vertically stacked above the first field-effect transistor. The second field-effect transistor includes a plurality of nanowires, a second gate, and a second source/drain region. The first gate and the second gate are vertically aligned. The first source/drain region and the second source/drain region are vertically aligned.

Abstract: A semiconductor device is provided. The semiconductor device includes an n-doped field effect transistor (nFET) section, a p-doped field effect transistor (pFET) section and an insulator pillar. The nFET section includes nFET nanosheets and nFET source or drain (S/D) regions partially surrounding the nFET nanosheets. The pFET section includes pFET nanosheets and pFET S/D regions partially surrounding the pFET nanosheets. The insulator pillar is interposed between the nFET S/D regions and the pFET S/D regions to form a fork-sheet structure with the nFET nanosheets and the pFET nanosheets.

Abstract: A semiconductor structure including a nanosheet stack on a silicon germanium on insulator substrate, the nanosheet stack including alternating layers of a sacrificial semiconductor material and a semiconductor channel material vertically aligned and stacked one on top of another, a gate conductor orthogonal to the nanosheet stack and wrapping around the semiconductor channel material layers of the nanosheet stack, and a gate contact on the gate conductor layer adjacent to the nanosheet stack.

Abstract: A semiconductor structure includes a plurality of fins on a semiconductor substrate, the plurality of fins including an alternating sequence of a first nanosheet made of epitaxially grown silicon and a second nanosheet made of epitaxially grown silicon germanium, and a shallow trench isolation region within the semiconductor substrate adjacent to the plurality of fins. The shallow trench isolation region including a recess within the substrate filled with a first liner, a second liner directly above the first liner, a third liner directly above the second liner, and a dielectric material directly above the third liner. The first liner is made of a first oxide material, the third liner is made of a nitride material, and the second liner is made of a second oxide material that creates a dipole effect for neutralizing positive charges within the third liner and positive charges between the third liner and the first liner.