Abstract: VTFET devices having a differential top spacer are provided. In one aspect, a method of forming a VTFET device includes: patterning fins in a wafer including NFET and PFET fins; forming bottom source and drains at a base of the NFET/PFET fins; forming bottom spacers on the bottom source and drains; forming gate stacks alongside the NFET/PFET fins that include a same workfunction metal on top of a gate dielectric; annealing the gate stacks which generates oxygen vacancies in the gate dielectric; forming top spacers that include an oxide spacer layer in contact with only the gate stacks alongside the PFET fins, wherein the oxide spacer layer supplies oxygen filling the oxygen vacancies in the gate dielectric only in the gate stacks alongside the PFET fins; and forming top source and drains above the gate stacks at the tops of the NFET/PFET fins. A VTFET device is also provided.

Abstract: A SiGe channel FinFET structure has an asymmetric threshold voltage, Vth, laterally along the SiGe channel. Uses of sacrificial layers, selective Ge condensation, and/or the use of spacers enable precise creation of first and second channel regions with different Ge concentration, even for channels with short lengths. The second channel region near the source side of the device is modified with a selective Germanium (Ge) condensation to have a higher Vth than the first channel region near the drain side. A lateral electric field is created in the channel to enhance carrier mobility.

Abstract: A method of fabricating a semiconductor device includes providing a high-k dielectric layer arranged on a channel region including a first transistor area and a second transistor area. The method further includes depositing a multivalent oxide layer directly on the high-k dielectric layer of the first transistor area. The method includes depositing a first work function metal on the multivalent oxide layer of the first transistor area and directly on the high-k dielectric layer of the second transistor area.

Abstract: A semiconductor device and method of forming the same including a plurality of vertically aligned semiconductor channel layers disposed above a substrate layer, a gate stack formed on, and around the vertically aligned semiconductor channel layers and source and drain elements disposed in contact with sidewalls of the vertically aligned semiconductor channel layers. An uppermost vertically aligned semiconductor channel layer has a first thickness of semiconductor material and the remaining vertically aligned semiconductor channel layers have a second thickness of semiconductor material different from the first thickness.

Abstract: A semiconductor device and method of forming the same including a plurality of vertically aligned long channel semiconductor channel layers disposed above a substrate layer, a plurality of vertically aligned short channel semiconductor channel layers disposed above a substrate layer, and a plurality of tri-layer dielectric spacers disposed between the vertically aligned long channel semiconductor layers.

Abstract: A semiconductor device includes a first gate-all-around field-effect transistor (GAA FET) device including a first gate stack having first channels and dielectric material including first and second portions having respective thicknesses formed around the first interfacial layers. The semiconductor device further includes a second GAA FET device including a second gate stack having second channels and the dielectric material formed around the second interfacial layers. A threshold voltage (Vt) shift associated with the semiconductor device is achieved based on a thickness of the first portion of the dielectric material.

Abstract: A method of forming a nanosheet field effect transistor device is provided. The method includes forming a stack of alternating sacrificial layer segments and nanosheet layer segments on a substrate. The method further includes removing the sacrificial layer segments to form channels on opposite sides of the nanosheet layer segments. The method further includes depositing a gate dielectric layer around each of the nanosheet layer segments, and forming a work function material block on the gate dielectric layer to form a gate-all-around structure on the nanosheet layer segments. The method further includes forming a capping layer on the work function material block.

Abstract: A method of forming a nanosheet device is provided. The method includes forming a plurality of narrow nanosheets on a first region of a substrate, and forming a plurality of wide nanosheets on a second region of the substrate. The method further includes forming an interfacial layer on the plurality of narrow nanosheets and the plurality of wide nanosheets. The method further includes depositing a gate dielectric layer on the plurality of narrow nanosheets and the plurality of wide nanosheets. The method further includes depositing a dummy gate layer on the gate dielectric layer on the plurality of narrow nanosheets and the plurality of wide nanosheets. The method further includes forming a dummy cover layer on the dummy gate layer on the plurality of narrow nanosheets and the plurality of wide nanosheets.

Abstract: A method of forming a semiconductor structure includes forming at least one fin disposed over a substrate, wherein sidewalls of the at least one fin includes a first portion proximate a top surface of the substrate having a tapered profile and a second portion disposed above the first portion. The method also includes forming a bottom source/drain region surrounding at least part of the first portion of the sidewalls of the at least one fin having the tapered profile and forming a bottom spacer disposed over a top surface of the bottom source/drain region surrounding at least part of the second portion of the sidewalls of the at least one fin. The at least one fin provides a channel for a vertical field-effect transistor.

Abstract: Semiconductor devices and methods of forming the same include forming an inner spacer on a semiconductor fin. Two outer spacers are formed around the inner spacer, with one outer spacer being separated from the inner spacer by a gap. A dipole-forming layer is formed on the semiconductor fin in the gap. A gate stack is formed on the semiconductor fin, between the outer spacers.

Abstract: A method of forming a semiconductor structure includes forming a recess within a semiconductor substrate, the recess is located between adjacent fins of a plurality of fins on the semiconductor substrate, forming a first liner above a perimeter including the recess, top surfaces of the semiconductor substrate, and top surfaces and sidewalls of the plurality of fins, the first liner includes a first oxide material, forming a second liner directly above the first liner, and forming a third liner directly above the second liner, the third liner includes a nitride material, the second liner includes a second oxide material capable of creating a dipole effect that neutralizes positive charges generated within the third liner and between the third liner and the first liner.

Abstract: A method of forming a complementary metal oxide semiconductor (CMOS) device is provided. The method includes forming a separate gate structure on each of a pair of vertical fins, wherein the gate structures include a gate dielectric layer and a gate metal layer, and forming a protective liner layer on the gate structures. The method further includes heat treating the pair of gate structures, and replacing the protective liner layer with an encapsulation layer. The method further includes exposing a portion of the gate dielectric layer by recessing the encapsulation layer. The method further includes forming a top source/drain on the top surface of one of the pair of vertical fins, and subjecting the exposed portion of the gate dielectric layer to a second heat treatment conducted in an oxidizing atmosphere.

Abstract: A p-type FinFET has an oxygen reservoir disposed on the gate stack. The oxygen reservoir provides an oxygen rich environment during processing steps of manufacturing the device to help the work function metal retain or obtain oxygen to maintain or increase the work function and keep the Vth of the device lower.

Abstract: A semiconductor structure and formation thereof. The semiconductor structure including: a nano-sheet field-effect transistor; a layer of support material that is located beneath a stack of nano-sheets that are included in the nano-sheet field-effect transistor; and a vertical support that is affixed to a stack of nano-sheets, wherein the vertical support (i) has an end that is affixed to the layer of support material and (ii) a side that is a affixed to at least one nano-sheet of the stack of nano-sheets.

Abstract: A first fin field effect transistor (FinFET) has an internal source/drain (S/D) with a facetted face that is connected to a dielectric side of a first RRAM. A second FinFET and RRAM structure are also disclosed. In some embodiments, an electrode contact side of each RRAM is connected in common to form a 2T2R device. The locations of one or more electrode points on the diamond-shaped, facetted surface of the bottom electrode accurately position electric fields through the dielectric to accurately and repeatably locate where the filaments/current paths are formed (or reset) through the RRAM dielectric. Material selection and accurate thickness of the RRAM dielectric determine the voltage at which the filaments/current paths are formed (or reset).

Abstract: A method is presented for triggering asymmetric threshold voltage along a channel of a vertical transport field effect transistor (VTFET). The method includes constructing a first set fins from a first material, constructing a second set of fins from a second material, forming a source region between the first set of fins, and forming a drain region between the second set of fins, the source region composed of a different material than the drain region. The method further includes depositing a first high-k metal gate over the first set of fins and depositing a second high-k metal gate over the second set of fins, the second high-k metal gate being different than the first high-k metal gate such that the asymmetric threshold voltage is present along the channel of the VTFET in a region defined at the bottom of the first and second set of fins.

Abstract: A method of forming a nanosheet field effect transistor device is provided. The method includes forming a stack of alternating sacrificial layer segments and nanosheet layer segments on a substrate. The method further includes removing the sacrificial layer segments to form channels on opposite sides of the nanosheet layer segments. The method further includes depositing a gate dielectric layer around each of the nanosheet layer segments, and forming a work function material block on the gate dielectric layer to form a gate-all-around structure on the nanosheet layer segments. The method further includes forming a capping layer on the work function material block.

Abstract: Vertical transport field effect transistors (FETs) having improved device performance are provided. Notably, vertical transport FETs having a gradient threshold voltage are provided. The gradient threshold voltage is provided by introducing a threshold voltage modifying dopant into a physically exposed portion of a metal gate layer composed of an n-type workfunction TiN. The threshold voltage modifying dopant changes the threshold voltage of the original metal gate layer.

Abstract: Parasitic transistor formation under a semiconductor containing nanosheet device is eliminated by forming an airgap between the source/drain regions of the semiconductor containing nanosheet device and the semiconductor substrate. The airgap is created by forming a sacrificial germanium-containing semiconductor material at the bottom of the source/drain regions prior to the epitaxial growth of the source/drain regions from physically exposed sidewalls of each semiconductor channel material nanosheet of a nanosheet material stack. After inner dielectric spacer formation, the sacrificial germanium-containing semiconductor material can be reflown to seal any possible openings to the semiconductor substrate. The source/drain regions are then epitaxially grown and thereafter, the sacrificial germanium-containing semiconductor material is removed from the structure creating the airgap between the source/drain regions of the semiconductor containing nanosheet device and the semiconductor substrate.

Abstract: Provided is a nanosheet semiconductor device. In embodiments of the invention, the nanosheet semiconductor device includes a channel nanosheet formed over a substrate. The nanosheet semiconductor device includes a buffer layer formed between the substrate and the channel nanosheet. The buffer layer has a lower conductivity than the channel nanosheet.