Abstract: I/O devices for gate-all-around transistors are provided. In one aspect, a method of forming an integrated circuit includes: forming at least first/second logic and I/O device stacks on a wafer having nanosheets of a channel material; forming an IL oxide on the nanosheets in the first and second device stacks; depositing a gate dielectric on the nanosheets in the first and second device stacks; selectively forming an oxygen containing layer on the second device stack; depositing a sacrificial layer onto the nanosheets and onto the oxygen containing layer; depositing a barrier layer onto the first and second device stacks; annealing the first and second device stacks to drive oxygen atoms from the oxygen containing layer into the IL oxide in the second device stack; removing the oxygen containing layer, sacrificial layer and barrier layer; and depositing a conformal gate conductor over the gate dielectric. An integrated circuit is also provided.

Abstract: I/O devices for gate-all-around transistors are provided. In one aspect, a method of forming an integrated circuit includes: forming at least first/second logic and I/O device stacks on a wafer having nanosheets of a channel material; forming an IL oxide on the nanosheets in the first and second device stacks; depositing a gate dielectric on the nanosheets in the first and second device stacks; selectively forming an oxygen containing layer on the second device stack; depositing a sacrificial layer onto the nanosheets and onto the oxygen containing layer; depositing a barrier layer onto the first and second device stacks; annealing the first and second device stacks to drive oxygen atoms from the oxygen containing layer into the IL oxide in the second device stack; removing the oxygen containing layer, sacrificial layer and barrier layer; and depositing a conformal gate conductor over the gate dielectric. An integrated circuit is also provided.

Abstract: A method of forming a nanosheet field effect transistor device is provided. The method includes forming a stack of alternating sacrificial layer segments and nanosheet layer segments on a substrate. The method further includes removing the sacrificial layer segments to form channels on opposite sides of the nanosheet layer segments. The method further includes depositing a gate dielectric layer around each of the nanosheet layer segments, and forming a work function material block on the gate dielectric layer to form a gate-all-around structure on the nanosheet layer segments. The method further includes forming a capping layer on the work function material block.

Abstract: A sacrificial inner dielectric spacer is formed on physically exposed sidewalls of each recessed semiconductor channel material nanosheet of a nanosheet material stack that further includes recessed sacrificial semiconductor material nanosheets that have an inner dielectric spacer formed on physically exposed sidewalls thereof. A local isolation region is then formed by selective epitaxial growth on a surface of a semiconductor substrate containing the nanosheet material stack. After forming the local isolation region, the sacrificial inner dielectric spacers are removed and a source/drain region is formed on the physically exposed surface of each recessed semiconductor channel material nanosheet. A portion of the source/drain structure is formed in a gap located between each neighboring pair of vertically spaced apart inner dielectric spacers.

Abstract: A stacked nanosheet semiconductor device and method of forming are provided. In an illustrative embodiment, a gate all around (GAA) stacked nanosheet field effect transistor (FET) includes a plurality of stacked semiconductor channel nanosheet layers and a dummy nanosheet layer formed above a top one of the stacked semiconductor channel nanosheet layers, the dummy nanosheet formed from a dielectric material. The GAA stacked nanosheet FET also includes a high dielectric constant (high-k) material formed around each of the plurality of stacked semiconductor channel nanosheet layers and around the dummy nanosheet layer and a first work function (WF) metal formed around the plurality of stacked semiconductor channel nanosheet layers and the dummy nanosheet layer.

Abstract: A semiconductor structure is provided that includes a pFET device including a first functional gate structure containing at least a p-type work function metal and present on physically exposed surfaces, and between, each Si channel material nanosheet of a first set of vertically stacked and suspended Si channel material nanosheets. The structure further includes an nFET device stacked vertically above the pFET device. The nFET device includes a second functional gate structure containing at least an n-type work function metal present on physically exposed surfaces, and between, each Si channel material nanosheet of a second set of vertically stacked and suspended Si channel material nanosheets.

Abstract: Vertical transport field effect transistors (FETs) having improved device performance are provided. Notably, vertical transport FETs having a gradient threshold voltage are provided. The gradient threshold voltage is provided by forming a gradient threshold voltage adjusting gate dielectric structure between the bottom drain region of the FET and the top source region of the FET. The gradient threshold voltage adjusting gate dielectric structure includes a doped interface high-k gate dielectric material that is located in proximity to the bottom drain region and a non-doped high-k dielectric material that is located in proximity to the top source region. The non-doped high-k dielectric material has a higher threshold voltage than the doped interface high-k gate dielectric.

Abstract: A resistive memory structure is provided. The resistive memory structure includes a vertical fin on a substrate, wherein the sidewalls of the vertical fin each have a {100} crystal face. The resistive memory structure further includes a fin template on the vertical fin, and a gate structure on the vertical fin. The resistive memory structure further includes a top source/drain on opposite sidewalls of the vertical fin, and a bottom electrode layer on the top source/drain, wherein the bottom electrode layer is on opposite sides of the fin template. The resistive memory structure further includes a first middle resistive layer on a portion of the bottom electrode layer, a top electrode layer on the first middle resistive layer, and a first electrical contact on a portion of the bottom electrode layer.

Abstract: A method is presented for attaining different gate dielectric thicknesses across a plurality of field effect transistor (FET) devices. The method includes forming an interfacial dielectric around alternate semiconductor layers of the plurality of FET devices, depositing a first sacrificial capping layer over the plurality of FET devices, selectively removing the first sacrificial capping layer from a first set of the plurality of FET devices, depositing a second sacrificial capping layer and an oxygen blocking layer, selectively removing the oxygen blocking layer from a second set of the plurality of FET devices, and performing an anneal to create the different gate dielectric thicknesses for each of the plurality of FET devices.

Abstract: A method for retrieving an audio file includes: collecting an audio segment in real time; and for every two chronologically adjacent audio frames in a plurality of audio frames of the audio segment, acquiring a difference value between spectral centroids of a sub-band corresponding to the two audio frames, to obtain a plurality of difference values; and obtaining an audio fingerprint corresponding to the two audio frames based on the plurality of difference values. A quantity of the plurality of difference values equaling a quantity of sub-bands of one of the two audio frames. Each bit of the audio fingerprint being determined based on a comparison between a difference value corresponding to the bit and a preset difference value threshold. The method also includes retrieving, in an audio file library based on audio fingerprints of the plurality of audio frames, a target audio file matching the audio segment.

Abstract: A method is presented for attaining different gate dielectric thicknesses across a plurality of field effect transistor (FET) devices. The method includes forming interfacial and high-k dielectric layers around alternate semiconductor layers of the plurality of FET devices, pinching off gaps between the alternate semiconductor layers by depositing a high work function capping layer over the plurality of FET devices, selectively removing the high work function capping layer from a first set of the plurality of FET devices, depositing a sacrificial capping layer, with the sacrificial capping layer leaving gaps between the alternate semiconductor layers of the first set of the plurality of FET devices, depositing an oxygen blocking layer, and annealing the plurality of FET devices to create different gate dielectric thicknesses for each of the plurality of FET devices.

Abstract: A method of forming a semiconductor device that includes providing a first stack of nanosheets having a first thickness and a second stack of nanosheets having a second thickness; and forming a oxide layer on the first and second stack of nanosheets. The oxide layer fills a space between said nanosheets in the first stack, and is conformally present on the nanosheets in the second stack. The method further includes forming a work function metal layer on the first and second stack of nanosheets. In some embodiments, the work function metal layer is present on only exterior surfaces of the first stack to provide a single gate structure and is conformally present about an entirety of the nanosheets in the second stack to provide a multiple gate structure.

Abstract: Vertical field effect transistors (VFETs) having a gradient threshold voltage and an engineered channel are provided. The engineered channel includes a vertical dog-bone shaped channel structure that is composed of silicon having a germanium content that is 1 atomic percent or less and having a lower portion having a first channel width, a middle portion having a second channel width that is less than the first channel width, and an upper portion having the first channel width. Due to the quantum confinement effect, the middle portion of the vertical dog-bone shaped channel structure has a higher threshold voltage than the lower portion and the upper portion of the vertical dog-bone shaped channel structure. Hence, the at least one vertical dog-bone shaped channel structure has an asymmetric threshold voltage profile. Also, the VFET containing the vertical dog-bone shaped channel structure has improved electrical characteristics and device performance.

Abstract: Techniques regarding FET 1T2R unit cells are provided. For example, one or more embodiments described herein can comprise a system, which can comprise a first resistive random-access memory unit operably coupled to a field-effect transistor by a first extrinsic semiconductor layer. The system can also comprise a second resistive random-access memory unit operably coupled to the field-effect transistor by a second extrinsic semiconductor layer.

Abstract: A method is presented for attaining different gate dielectric thicknesses across a plurality of field effect transistor (FET) devices. The method includes forming interfacial and high-k dielectric layers around alternate semiconductor layers of the plurality of FET devices, pinching off gaps between the alternate semiconductor layers by depositing a high work function capping layer over the plurality of FET devices, selectively removing the high work function capping layer from a first set of the plurality of FET devices, depositing a sacrificial capping layer, with the sacrificial capping layer leaving gaps between the alternate semiconductor layers of the first set of the plurality of FET devices, depositing an oxygen blocking layer, and annealing the plurality of FET devices to create different gate dielectric thicknesses for each of the plurality of FET devices.

Abstract: A FinFET having an asymmetric threshold voltage distribution is provided by modifying a portion of the channel region of a semiconductor fin that is nearest to the drain side with an epitaxial semiconductor material layer. In some embodiments, the channel region of the semiconductor fin nearest to the drain side is trimmed prior to forming the epitaxial semiconductor material layer.

Abstract: A FinFET having an asymmetric threshold voltage distribution is provided by modifying a portion of the channel region of a semiconductor fin that is nearest to the drain side with an epitaxial semiconductor material layer. In some embodiments, the channel region of the semiconductor fin nearest to the drain side is trimmed prior to forming the epitaxial semiconductor material layer.

Abstract: Embodiments of the invention are directed to a method of forming a semiconductor device. A non-limiting example of the method includes forming a fin having a fin bottom region. A charged region is formed on a sidewall of the fin bottom region, wherein the charged region includes charged particles, and wherein the fin bottom region is formed from an undoped semiconductor material. The charged particles attract charge carriers in the fin bottom region toward and adjacent to the sidewall of the fin bottom region, wherein the charge carriers form a current path through the undoped semiconductor material of the fin bottom region.

Abstract: An aspect of the invention includes reading a scale in image data representing an image of physical characteristics and resizing at least a portion of the image data to align with target image data representing a target image based at least in part on the scale to form resized image data representing one or more resized images. Noise reduction is applied to the resized image data to produce test image data representing one or more test images. A best fit analysis is performed on the test image data with respect to the target image data. Test image data having the best fit are stored with training image data representing classification training images indicative of one or more recognized features. An anomaly in unclassified image data representing an unclassified image is identified based at least in part on an anomaly detector as trained using the classification training images.

Abstract: A semiconductor structure is provided that includes a pFET device including a first functional gate structure containing at least a p-type work function metal and present on physically exposed surfaces, and between, each Si channel material nanosheet of a first set of vertically stacked and suspended Si channel material nanosheets. The structure further includes an nFET device stacked vertically above the pFET device. The nFET device includes a second functional gate structure containing at least an n-type work function metal present on physically exposed surfaces, and between, each Si channel material nanosheet of a second set of vertically stacked and suspended Si channel material nanosheets.