Patents by Inventor Jinhan Zhang

Jinhan Zhang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220190110
    Abstract: The HEMT includes a channel layer, a barrier layer, a drain, and a gate conductor. The barrier layer is disposed on the channel layer. The drain is disposed on the barrier layer. The gate conductor is disposed on the barrier layer. The channel layer includes a doped semiconductor structure overlapping with a top surface of the channel layer and having a bottom-most border that is located over a bottom-most surface of the channel layer and is spaced apart from the bottom-most surface of the channel layer. The doped semiconductor structure is located between the drain and the gate conductor.
    Type: Application
    Filed: March 3, 2022
    Publication date: June 16, 2022
    Inventors: King Yuen WONG, Ronghui HAO, Jinhan ZHANG
  • Publication number: 20220190111
    Abstract: The HEMT includes a channel layer, a barrier layer, a drain, and a gate conductor. The barrier layer is disposed on the channel layer. The drain is disposed on the barrier layer. The gate conductor is disposed on the barrier layer. The barrier layer comprises a doped semiconductor region extending from a top surface to a bottom surface of the barrier layer and located between the drain and the gate conductor.
    Type: Application
    Filed: March 3, 2022
    Publication date: June 16, 2022
    Inventors: King Yuen WONG, Ronghui HAO, Jinhan ZHANG
  • Patent number: 11302778
    Abstract: The present disclosure provides a high electron mobility transistor (HEMT). The HEMT includes a substrate, a buffer layer, a channel layer, a barrier layer, a source, a drain, and a gate. The substrate, the buffer layer, the channel layer, the barrier layer, the source, the drain, and the gate are stacked in sequence in a thickness direction of the HEMT. The channel layer includes a doped semiconductor structure. The present disclosure further provides a method for manufacturing an HEMT. The HEMT has good performance and has features such as low drain electric field intensity, a high breakdown voltage, high stability, and low costs.
    Type: Grant
    Filed: April 8, 2020
    Date of Patent: April 12, 2022
    Assignee: Innoscience (Zhuhai) Technology Co., Ltd.
    Inventors: King Yuen Wong, Ronghui Hao, Jinhan Zhang
  • Publication number: 20210384303
    Abstract: Embodiments of this application disclose a semiconductor device and a manufacturing method thereof The semiconductor device includes a substrate, a first nitride semiconductor layer disposed on the substrate and having a first bandgap, and a second nitride semiconductor layer disposed on the first nitride semiconductor layer and having a second bandgap. The second bandgap is larger than the first bandgap. The semiconductor device further includes a gate contact disposed over the second nitride semiconductor layer and a first field plate disposed over the gate contact. The first field plate has a first surface facing the substrate, a second surface facing the substrate, and a protruded portion. The protruded portion has a bottom surface facing the substrate. The bottom surface is located between the first surface and the second surface.
    Type: Application
    Filed: October 8, 2020
    Publication date: December 9, 2021
    Inventors: Jinhan ZHANG, Xiaoyan ZHANG, Kai HU, Ronghui HAO, Junhui MA
  • Publication number: 20210202698
    Abstract: The present disclosure provides a high electron mobility transistor (HEMT). The HEMT includes a substrate, a buffer layer, a channel layer, a barrier layer, a source, a drain, and a gate. The substrate, the buffer layer, the channel layer, the barrier layer, the source, the drain, and the gate are stacked in sequence in a thickness direction of the HEMT. The channel layer includes a doped semiconductor structure. The present disclosure further provides a method for manufacturing an HEMT. The HEMT has good performance and has features such as low drain electric field intensity, a high breakdown voltage, high stability, and low costs.
    Type: Application
    Filed: April 8, 2020
    Publication date: July 1, 2021
    Inventors: King Yuen WONG, Ronghui HAO, Jinhan ZHANG
  • Publication number: 20210151594
    Abstract: A semiconductor device includes a substrate, a channel layer, a barrier layer, a gate, a strained layer and a passivation layer. The channel layer is disposed on the substrate. The barrier layer is disposed on the channel layer. The gate is disposed on the barrier layer. The strained layer is disposed on the barrier layer. The passivation layer covers the gate and the strained layer. The material of the passivation layer differs from that of the strained layer.
    Type: Application
    Filed: December 20, 2019
    Publication date: May 20, 2021
    Inventors: KINGYUEN WONG, HAN-CHIN CHIU, MING-HONG CHANG, CHUNHUA ZHOU, JINHAN ZHANG
  • Publication number: 20200380252
    Abstract: In some embodiments, apparatuses and methods are provided herein useful to detecting egress. In some embodiments, there is provided a system for detecting egress at an entrance including a video camera; a computer; a network; and a control circuit configured to receive live video footage; detect a human and estimate a location of the human; track a location and movement of a detected human; determine that the detected human has moved from a first region to a second region and to a third region; and transmit an alert message that indicates that the human has exited the retail facility through the entrance area. In some embodiments, the systems and methods may be configured to comply with privacy requirements which may vary between jurisdictions. For example, before any recording, collection, capturing or processing of user images (e.g., video image, video footage, etc.), a “consent to capture” process may be implemented.
    Type: Application
    Filed: May 29, 2020
    Publication date: December 3, 2020
    Inventors: Yi Ding, Joseph Duffy, Jiankun Liu, Tianyi Mao, Ryan B. Reagan, Zhichun Xiao, Jinhan Zhang, Shouyi Zhang
  • Publication number: 20200203502
    Abstract: The present disclosure provides a high electron mobility transistor, including a silicon substrate, a channel layer, a barrier layer and a gate sequentially stacked in a thickness direction of the high electron mobility transistor. The high electron mobility transistor further includes a strain layer made of an insulating material. A surface of the barrier layer distal to the channel layer includes a gate region and an enhancement region. The gate is disposed in the gate region. The strain layer includes an enhancement portion stacked in the enhancement region. A mismatch rate of a lattice constant of the strain layer to a lattice constant of the barrier layer is not less than 0.5%. The present disclosure further provides a method for manufacturing a high electron mobility transistor. The high electron mobility transistor has good performance and low cost.
    Type: Application
    Filed: December 10, 2019
    Publication date: June 25, 2020
    Inventors: Roy Wong, Han-Chin Chiu, Ming-Hong Chang, David Zhou, Jinhan Zhang