High Electron Mobility Transistor and Method for Manufacturing the Same

Abstract

The present disclosure provides a high electron mobility transistor, including a silicon substrate, a channel layer, a barrier layer and a gate sequentially stacked in a thickness direction of the high electron mobility transistor. The high electron mobility transistor further includes a strain layer made of an insulating material. A surface of the barrier layer distal to the channel layer includes a gate region and an enhancement region. The gate is disposed in the gate region. The strain layer includes an enhancement portion stacked in the enhancement region. A mismatch rate of a lattice constant of the strain layer to a lattice constant of the barrier layer is not less than 0.5%. The present disclosure further provides a method for manufacturing a high electron mobility transistor. The high electron mobility transistor has good performance and low cost.

Description

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority to Chinese Patent Application No. 201811571363.5 filed Dec. 21, 2018, the disclosure of which is hereby incorporated by reference in its entirety.

TECHNICAL FIELD

The present disclosure relates to the field of microelectronics, and in particular, to a high electron mobility transistor and a method for manufacturing the high electron mobility transistor.

BACKGROUND

A high electron mobility transistor (HEMT) is a field effect transistor, and includes a silicon substrate 110, a channel layer 120 disposed on the silicon substrate 110, a barrier layer 130 disposed on the channel layer 120, and a source 141, a drain 142 and a gate 143 disposed on the barrier layer 130, as shown in FIG. 1. In order to ensure that the high electron mobility transistor is in a normally-off state and can be turned on when the voltage at the gate 143 reaches a threshold voltage, it is necessary to reduce the two-dimensional electron gas (2 DEG) concentration of a gate region (i.e., a region under the gate 143) and increase the two-dimensional electron gas concentrations of a source region (i.e., a region under the source 141) and a drain region (i.e., a region under the drain 142).

In order to increase the two-dimensional electron gas of the source and drain regions and decrease the two-dimensional electron gas of the gate region, a barrier material regrowth layer is typically provided between the source 141 and the barrier layer 130 and between the drain 142 and the barrier layer 130, as shown in FIG. 2. However, the high electron mobility transistor with such a structure is complicated in manufacturing process and high in cost.

Therefore, how to manufacture a high-performance high electron mobility transistor at low cost is an urgent technical problem to be solved in the field.

SUMMARY

An object of the present disclosure is to provide a high electron mobility transistor and a method for manufacturing the high electron mobility transistor. The high electron mobility transistor has relatively high two-dimensional electron gas concentrations in a source region and a drain region and a relatively low two-dimensional electron gas concentration in a gate region, and has a relatively low manufacturing cost.

In order to achieve the above object, as an aspect of the present disclosure, there is provided a high electron mobility transistor including a silicon substrate, a channel layer, a barrier layer and a gate, the silicon substrate, the channel layer, the barrier layer, and the gate being sequentially stacked in a thickness direction of the high electron mobility transistor, wherein the high electron mobility transistor further includes a strain layer made of an insulating material, a surface of the barrier layer distal to the channel layer includes a gate region and an enhancement region, the gate is disposed in the gate region, the strain layer includes an enhancement portion stacked in the enhancement region, and a mismatch rate of a lattice constant of the strain layer to a lattice constant of the barrier layer is not less than 0.5%.

In an embodiment, the strain layer further includes a gate covering portion covering an outer surface of the gate, the gate covering portion and the enhancement portion are formed as a whole.

In an embodiment, a material of the strain layer includes a nitrogen-based material and/or an oxygen-based material.

In an embodiment, the material of the strain layer includes at least one of silicon nitride, silicon oxide, silicon oxynitride, boron oxide, boron nitride, boron oxynitride, aluminum oxide, aluminum nitride, aluminum oxynitride, titanium oxide, titanium nitride, and titanium oxynitride.

In an embodiment, a thickness of the strain layer is between 1 nm and 100 nm.

In an embodiment, the high electron mobility transistor further includes a source, a drain, a passivation layer stacked on the strain layer, and a planarization layer stacked on a surface of the passivation layer.

The source is connected to the channel layer through a source via hole penetrating through the planarization layer, the passivation layer and the strain layer, and the drain is connected to the channel layer through a drain via hole penetrating through the planarization layer, the passivation layer and the strain layer.

In an embodiment, the high electron mobility transistor further includes a buffer layer disposed between the silicon substrate and the channel layer.

In an embodiment, a material of the channel layer includes GaN, and a material of the barrier layer includes AlGaN.

As a second aspect of the present disclosure, there is provided a method for manufacturing a high electron mobility transistor, the method including:

providing a silicon substrate;

forming a channel layer;

forming a barrier layer, a surface of the barrier layer distal to the channel layer including a gate region and an enhancement region;

forming a gate in the gate region; and

forming a strain layer using an insulating material, the strain layer including an enhancement portion disposed in the enhancement region, wherein a mismatch rate of a lattice constant of the strain layer to a lattice constant of the barrier layer is not less than 0.5%.

In an embodiment, the strain layer further includes a gate covering portion covering an outer surface of the gate, the gate covering portion and the enhancement portion being formed as a whole.

In an embodiment, a material of the strain layer includes a nitrogen-based material and/or an oxygen-based material.

In an embodiment, the material of the strain layer includes at least one of silicon nitride, silicon oxide, silicon oxynitride, boron oxide, boron nitride, boron oxynitride, aluminum oxide, aluminum nitride, aluminum oxynitride, titanium oxide, titanium nitride, and titanium oxynitride.

In an embodiment, a thickness of the strain layer is between 1 nm and 100 nm.

In an embodiment, the manufacturing method further includes, after the step of forming the strain layer, steps of:

forming a passivation layer;

forming a planarization layer;

forming a source via hole penetrating through the planarization layer, the passivation layer and the strain layer and a drain via hole penetrating through the planarization layer, the passivation layer and the strain layer; and

forming a source and a drain, wherein the source is connected to the barrier layer through the source via hole, and the drain is connected to the barrier layer through the drain via hole.

In an embodiment, the manufacturing method further includes, between the step of providing the silicon substrate and the step of forming the channel layer, a step of:

forming a buffer layer.

In an embodiment, a material of the channel layer includes GaN, and a material of the barrier layer includes AlGaN.

Because there is a relatively large difference between the lattice constant of the strain layer and the lattice constant of the barrier layer, and the enhancement portion of the strain layer is attached to the barrier layer, lattice deformation occurs, and an additional piezoelectric effect will be generated, so that the two-dimensional electron gas in the region corresponding to the enhancement region can be increased. Because no strain layer is provided in the gate region where the gate is provided, the two-dimensional electron gas in the region corresponding to the gate region will not be increased. As a result, the high electron mobility transistor has improved performance.

In the present disclosure, the two-dimensional electron gas in the enhancement region can be increased only by arranging the enhancement portion in the enhancement region, and compared with the case of forming a source ohmic contact layer and a drain ohmic contact layer in the related art, the process for forming the strain layer is simpler, so that the cost for forming a high-performance high electron mobility transistor can be reduced.

BRIEF DESCRIPTION OF THE DRAWINGS

Accompanying drawings, which constitute a part of the specification, are intended to provide a further understanding of the present disclosure, and are used for explaining the present disclosure together with the following specific implementations, rather than limiting the present disclosure. In the drawing:

FIG. 1 is a schematic diagram of a high electron mobility transistor in the related art;

FIG. 2 is a schematic diagram of another high electron mobility transistor in the related art;

FIG. 3 is a schematic diagram of a high electron mobility transistor according to an embodiment of the present disclosure;

FIG. 4 is a flow chart of a method for manufacturing a high electron mobility transistor according to an embodiment of the present disclosure;

FIG. 5 is a schematic diagram of a semi-finished high electron mobility transistor formed with a gate.

FIG. 6 is a schematic diagram of a semi-finished high electron mobility transistor formed with a strain layer.

FIG. 7 is a schematic diagram of a semi-finished high electron mobility transistor formed with a passivation layer.

FIG. 8 is a graph illustrating test curves of drain currents of a high electron mobility transistor according to an embodiment of the present disclosure and a high electron mobility transistor according to a comparative example.

FIG. 9a is a graph illustrating comparison between threshold voltages of a high electron mobility transistor according to an embodiment of the present disclosure and a high electron mobility transistor according to a comparative example.

FIG. 9b is a graph illustrating comparison between Ron,sp of a high electron mobility transistor according to an embodiment of the present disclosure and Ron,sp of a high electron mobility transistor according to a comparative example.

REFERENCE NUMERALS

110: Silicon substrate   120: Channel layer
130: Barrier layer       141: Source
142: Drain               143: Gate
144: Field plate         150: Strain layer
151: Enhancement portion 152: Gate covering portion
160: Passivation layer   170: Planarization layer
180: Buffer layer        141a: Source via hole
142a: Drain via hole

DETAILED DESCRIPTION

The specific implementations of the present disclosure will be described in detail below with reference to the accompanying drawings. It should be understood that the specific implementations described herein are merely for the purpose of describing and explaining the present disclosure, and are not intended to limit the present disclosure.

As one aspect of the present disclosure, there is provided a high electron mobility transistor, which, as shown in FIG. 3, includes a silicon substrate 110, a channel layer 120, a barrier layer 130, and a gate 143. The silicon substrate 110, the channel layer 120, the barrier layer 130 and the gate 143 are sequentially stacked along a thickness direction of the high electron mobility transistor (i.e., an up-down direction in FIG. 3). The high electron mobility transistor further includes a strain layer 150 made of an insulating material, and a surface of the barrier layer 130 distal to the channel layer 120 includes a gate region and an enhancement region. As shown in the figures, the gate 143 is disposed in the gate region, the strain layer 150 includes an enhancement portion 151 disposed in the enhancement region in a stacked manner, and a mismatch rate of a lattice constant of the strain layer 150 to a lattice constant of the barrier layer 130 is not less than 0.5%.

Since there is a relatively large difference between the lattice constant of the strain layer 150 and the lattice constant of the barrier layer 130, and the enhancement portion 151 of the strain layer 150 is attached to the barrier layer 130, the lattice deformation occurs, and an additional piezoelectric effect will be generated, so that the two-dimensional electron gas in the region corresponding to the enhancement region can be increased. Because no strain layer is provided in the gate region where the gate 143 is provided, the two-dimensional electron gas in the region corresponding to the gate region will not be increased, thereby improving performance of the high electron mobility transistor.

In the present disclosure, the increase of the two-dimensional electron gas in the enhancement region can be achieved simply by providing the strain layer 150 including the enhancement portion 151 in the enhancement region, and the process of forming the strain layer is simpler as compared to an implementation (i.e., the implementation shown in FIG. 2) in which a barrier material regrowth layer is provided in the related art, so that the cost for forming a high-performance high electron mobility transistor can be reduced.

In the present disclosure, there is no special requirement on the specific structure of the strain layer 150, for example, the portion of the strain layer 150 corresponding to the gate is a gate through hole. In other words, the strain layer 150 includes a gate through hole and an enhancement portion surrounding the gate through hole. To form the strain layer having this structure, a whole layer of strain material may be formed first and then patterned to obtain the gate through hole and the enhancement portion.

For convenience of manufacturing, in an embodiment, the strain layer 150 further includes a gate covering portion 152 covering the outer surface of the gate 143, and the gate covering portion 152 and the enhancement portion 151 are formed as a whole, as shown in FIG. 3. In the process of forming the high electron mobility transistor, after the pattern of the gate 143 is formed, the strain layer 150 in a form of a complete layer is directly formed without patterning the strain layer 150, so that the cost for manufacturing the high electron mobility transistor can be reduced.

In the present disclosure, the specific material of the strain layer is not particularly limited as long as the material of the strain layer is an insulating material and the mismatch rate of the lattice constant of the strain layer and the lattice constant of the barrier layer is not less than 0.5% such that the enhancement portion 151 of the strain layer 150 can generate an additional piezoelectric effect. In an embodiment, the material of the strain layer 150 includes a nitrogen-based material and/or an oxygen-based material.

In an embodiment, the material of the strain layer includes at least one of silicon nitride, silicon oxide, silicon oxynitride, boron oxide, boron nitride, boron oxynitride, aluminum oxide, aluminum nitride, aluminum oxynitride, titanium oxide, titanium nitride, and titanium oxynitride.

To ensure that sufficient strain is generated at the interface between the strain layer 150 and the barrier layer 130 to cause the barrier layer 130 to deform and provide an additional piezoelectric polarization effect, the strain layer 150 may have a thickness larger than 1 nm in an embodiment. In the meanwhile, in order to prevent the strain layer 150 from having a too large thickness to cause a relaxation effect, a decrease in stress of the barrier layer 130 and a decrease in piezoelectric polarization effect, the thickness of the strain layer 150 is not larger than 100 nm in an embodiment. In other words, the thickness of the strain layer 150 in some embodiments of the present disclosure is between 1 nm and 100 nm.

The high electron mobility transistor further includes a source and a drain. As an implementation, the source and the drain may be disposed in the same layer as the gate 143. However, the present disclosure is not limited thereto, and for example, in the embodiment shown in FIG. 3, both the source 141 and the drain 142 are located in a different layer from the gate 143. In the embodiment shown in FIG. 3, a field plate 144 is disposed between the source 141 and drain 142.

In an embodiment, the high electron mobility transistor further includes a passivation layer 160 stacked on the strain layer, and a planarization layer 170 stacked on a surface of the passivation layer 160. The source 141 and the drain 142 are disposed on a surface of the planarization layer 170. The source 141 is connected to the barrier layer 130 through a source via hole 141a penetrating through the planarization layer 170, the passivation layer 160 and the strain layer 150. The drain 142 is connected to the barrier layer 130 through a drain via hole 142a penetrating through the planarization layer 170, the passivation layer 160 and the strain layer 150.

The source 141 and the drain 142 are not directly disposed on the barrier layer 130, but are connected to the barrier layer 130 through the via holes, so that part of the enhancement portion 151 covers a portion of the barrier layer 130 under the source 141, and another part of the enhancement portion 151 covers a portion of the barrier layer 130 under the drain 142, thereby further increasing two-dimensional electron gas in both the region under the source 141 and the region under the drain 142, and further improving the performance of the high electron mobility transistor.

In an embodiment of the present disclosure, the high electron mobility transistor further includes a buffer layer 180 disposed between the silicon substrate 110 and the channel layer 120. In the present disclosure, a specific material of the buffer layer 180 is not particularly limited, and the buffer layer 180 may be made of, for example, AlN.

In the present disclosure, specific materials of the channel layer 120 and the barrier layer 130 are not particularly limited, and in an embodiment, the material of the channel layer 120 may include GaN, and the material of the barrier layer 130 may include AlGaN.

As a second aspect of the present disclosure, there is provided a method for manufacturing a high electron mobility transistor. As shown in FIG. 4, the method includes the following steps.

In step S110, a silicon substrate is provided.

In step S120, a channel layer is formed.

In step S130, a barrier layer is formed, a surface of the barrier layer distal to the channel layer including a gate region and an enhancement region.

In step S140, a gate 143 is formed in the gate region (as shown in FIG. 5);

In step S150, a strain layer 150 including an enhancement portion 151 in the enhancement region is formed using an insulating material (as shown in FIG. 6), a mismatch rate of a lattice constant of the strain layer and a lattice constant of the barrier layer being not less than 0.5%.

The manufacturing method provided in the present disclosure can be used for manufacturing the high electron mobility transistor provided in the present disclosure. The working principle and the beneficial effects of the high electron mobility transistor have been described in detail above, and are not repeatedly described herein.

For convenience of manufacturing, in an embodiment, the strain layer 150 further includes a gate covering portion 152 covering an outer surface of the gate 143, and the gate covering portion 152 and the enhancement portion 151 are formed as a whole, as shown in FIG. 6.

In an embodiment, the material of the strain layer 150 includes a nitrogen-based material and/or an oxygen-based material.

In an embodiment, the material of the strain layer 150 includes at least one of silicon nitride, silicon oxide, silicon oxynitride, boron oxide, boron nitride, boron oxynitride, aluminum oxide, aluminum nitride, aluminum oxynitride, titanium oxide, titanium nitride, and titanium oxynitride.

In an embodiment, the thickness of the strain layer is between 1 nm and 100 nm.

In order to form the high electron mobility transistor shown in FIG. 3, in an embodiment, the manufacturing method further includes the following steps after the step of forming the strain layer.

In step S160, a passivation layer 160 is formed (as shown in FIG. 7).

In step S170, a planarization layer is formed.

In step S180, a source via hole penetrating through the planarization layer, the passivation layer and the strain layer and a drain via hole penetrating through the planarization layer, the passivation layer and the strain layer are formed.

In step S190, a source and a drain are formed, the source being connected to the barrier layer through the source via hole, and the drain being connected to the barrier layer through the drain via hole.

In an embodiment, the manufacturing method further includes, between the step of providing the silicon substrate and the step of forming the channel layer, a step of:

forming a buffer layer.

In an embodiment, the material of the channel layer includes GaN, and the material of the barrier layer includes AlGaN.

Example 1

The high electron mobility transistor is manufactured using the following method.

In step S110, a silicon substrate is provided.

A buffer layer is formed using AlN.

In step S120, a channel layer is formed using GaN.

In step S130, a barrier layer is formed using AlGaN, a surface of the barrier layer distal to the channel layer including a gate region and an enhancement region.

In step S140, a gate is formed in the gate region.

In step S150, a strain layer 150 is formed using a silicon nitride (as shown in FIG. 6), and the strain layer 150 includes an enhancement portion 151 disposed in the enhancement region and a gate covering portion covering the gate.

In step S160, a passivation layer is formed.

In step S170, a planarization layer is formed.

In step S180, a source via hole penetrating through the planarization layer, the passivation layer, and the strain layer and a drain via hole penetrating through the planarization layer, the passivation layer, and the strain layer are formed.

In step S190, a source and a drain are formed, the source is connected to the barrier layer through the source via hole, and the drain is connected to the barrier layer through the drain via hole.

Comparative Example

The high electron mobility transistor is manufactured using the following method.

In step S110, a silicon substrate is provided.

A buffer layer is formed using AlN.

In step S120, a channel layer is formed using GaN.

In step S130, a barrier layer is formed using AlGaN, a surface of the barrier layer distal to the channel layer including a gate region and an enhancement region.

In step S140, a gate is formed in the gate region.

In step S160, a passivation layer is formed.

In step S170, a planarization layer is formed.

In step S180, a source via hole penetrating through the planarization layer and the passivation layer and a drain via hole penetrating through the planarization layer and the passivation layer are formed.

In step S190, a source and a drain are formed, the source is connected to the barrier layer through the source via hole, and the drain is connected to the barrier layer through the drain via hole.

Test Example

1. 100V Direct-Current Contrast Test

The drain current I_D of the high electron mobility transistor HEMT-B manufactured in the example 1 and the drain current I_D of the high electron mobility transistor HEMT-A manufactured in the comparative example under different gate-source voltages V_GS are respectively tested at 25° C., and both the drain-source voltage V_DS of the high electron mobility transistor HEMT-B manufactured in the example 1 and the drain-source voltage V_DS of the high electron mobility transistor HEMT-A manufactured in the comparative example are 1V. It can be seen from FIG. 8 that the difference in current between the high electron mobility transistor HEMT-B manufactured in the example 1 and the high electron mobility transistor HEMT-A manufactured in the comparative example under different gate-source voltages V_GS is not significant. That is to say, the presence of the strain layer does not affect the performance of the high electron mobility transistor.

2. Threshold Voltage Test

The threshold voltages of the high electron mobility transistor HEMT-B manufactured in the example 1 and the high electron mobility transistor HEMT-A manufactured in the comparative example are respectively tested at 25° C., and as shown in FIG. 9a, the threshold voltages of the high electron mobility transistor HEMT-B and the high electron mobility transistor HEMT-A are nearly the same, and both are about 1.5V.

3. Ultra-Low Specific On-Resistance R_{ON, sp} Test

The ultra-low specific on-resistances R_{ON, sp} of the high electron mobility transistor HEMT-B manufactured in the example 1 and the high electron mobility transistor HEMT-A manufactured in the comparative example are respectively tested at 25° C. As shown in FIG. 9B, the ultra-low specific on-resistance R_{ON, sp} of the high electron mobility transistor HEMT-B manufactured in the example 1 is 0.2 mΩ·cm², the ultra-low specific on-resistance R_{ON, sp} of the high electron mobility transistor HEMT-A manufactured in the comparative example is 0.3 mΩ·cm², and thus, the ultra-low specific on-resistance of the high electron mobility transistor HEMT-B is lower than the ultra-low specific on-resistance of the high electron mobility transistor HEMT-A manufactured in the comparative example. Therefore, the high electron mobility transistor provided in the present disclosure has a relatively low energy consumption.

It could be understood that the above implementations are merely exemplary implementations for illustrating the principle of the present disclosure, but the present disclosure is not limited thereto. Various modifications and improvements can be made by those skilled in the art without departing from the spirit and essence of the present disclosure, and these modifications and improvements are also considered to be within the protection scope of the present disclosure.

Claims

1. A high electron mobility transistor, comprising:

a silicon substrate, a channel layer, a barrier layer, and a gate; with the silicon substrate, the channel layer, the barrier layer, and the gate being sequentially stacked in a thickness direction of the high electron mobility transistor;

wherein the high electron mobility transistor further comprises a strain layer made of an insulating material, a surface of the barrier layer distal to the channel layer comprises a gate region and an enhancement region, the gate is disposed in the gate region, the strain layer comprises an enhancement portion stacked in the enhancement region, and a mismatch rate of a lattice constant of the strain layer to a lattice constant of the barrier layer is not less than 0.5%.

2. The high electron mobility transistor of claim 1, wherein the strain layer further comprises a gate covering portion covering an outer surface of the gate, and the gate covering portion and the enhancement portion are formed as a whole.

3. The high electron mobility transistor of claim 1, wherein a material of the strain layer comprises a nitrogen-based material and/or an oxygen-based material.

4. The high electron mobility transistor of claim 3, wherein the material of the strain layer comprises at least one of silicon nitride, silicon oxide, silicon oxynitride, boron oxide, boron nitride, boron oxynitride, aluminum oxide, aluminum nitride, aluminum oxynitride, titanium oxide, titanium nitride, and titanium oxynitride.

5. The high electron mobility transistor of claim 3, wherein a thickness of the strain layer is between 1 nm and 100 nm.

6. The high electron mobility transistor of claim 1, further comprising a source, a drain, a passivation layer stacked on the strain layer, and a planarization layer stacked on a surface of the passivation layer,

wherein the source is connected to the barrier layer through a source via hole penetrating through the planarization layer, the passivation layer and the strain layer, and the drain is connected to the barrier layer through a drain via hole penetrating through the planarization layer, the passivation layer and the strain layer.

7. The high electron mobility transistor of claim 1, further comprising a buffer layer disposed between the silicon substrate and the channel layer.

8. The high electron mobility transistor of claim 1, wherein a material of the channel layer comprises GaN, and a material of the barrier layer comprises AlGaN.

9. A method for manufacturing a high electron mobility transistor, comprising:

providing a silicon substrate;

forming a channel layer;

forming a barrier layer, a surface of the barrier layer distal to the channel layer comprising a gate region and an enhancement region;

forming a gate in the gate region; and

forming a strain layer using an insulating material, the strain layer comprising an enhancement portion disposed in the enhancement region, wherein a mismatch rate of a lattice constant of the strain layer to a lattice constant of the barrier layer is not less than 0.5%.

10. The method of claim 9, wherein the strain layer further comprises a gate covering portion covering an outer surface of the gate, the gate covering portion and the enhancement portion being formed as a whole.

11. The method of claim 9, wherein a material of the strain layer comprises a nitrogen-based material and/or an oxygen-based material.

12. The method of claim 11, wherein the material of the strain layer comprises at least one of silicon nitride, silicon oxide, silicon oxynitride, boron oxide, boron nitride, boron oxynitride, aluminum oxide, aluminum nitride, aluminum oxynitride, titanium oxide, titanium nitride, and titanium oxynitride.

13. The method of claim 11, wherein a thickness of the strain layer is between 1 nm and 100 nm.

14. The method of claim 9, further comprising, after the step of forming the strain layer, steps of:

forming a passivation layer;

forming a planarization layer;

forming a source via hole penetrating through the planarization layer, the passivation layer and the strain layer and a drain via hole penetrating through the planarization layer, the passivation layer and the strain layer; and

forming a source and a drain, wherein the source is connected to the barrier layer through the source via hole, and the drain is connected to the barrier layer through the drain via hole.

15. The method of claim 9, further comprising, between the step of providing the silicon substrate and the step of forming the channel layer, a step of:

forming a buffer layer.

16. The method of claim 9, wherein a material of the channel layer comprises GaN, and a material of the barrier layer comprises AlGaN.