Abstract: A display device comprises a substrate including a display area and a non-display area, and pixels disposed in the display area, each of the pixels including sub-pixels. Each of sub-pixels includes a pixel circuit layer, and a display element layer including at least one light emitting element. The display element layer includes first and second electrodes spaced apart from each other, the light emitting element disposed between the first electrode and second electrode, a first contact electrode that electrically connects an end of the light emitting element to the first electrode, and a second contact electrode that electrically connects another end of the light emitting element to the second electrode. Each of sub-pixels includes a first area in which the pixel circuit layer is disposed, and a second area adjacent to the first area. The second area includes a transmission area through which the light passes.

Abstract: An apparatus for manufacturing a light emitting display device includes a substrate transfer stage including a plurality of support plates arranged at an interval in a first direction, each of the plurality of support plates extending in a second direction; and at least one electric-field application module disposed on at least one side of the substrate transfer stage. The at least one electric-field application module includes a probe head including at least one probe pin; and a driver connected to the probe head to move the probe head at least up and down.

Abstract: A display device and a method of manufacturing the same are provided. The display device comprises a first area which extends in a first direction, a second area which extends in the first direction and is alongside the first area in a second direction intersecting the first direction, at least one first light emitting element in the first area, at least one second light emitting element in the second area, at least one first wiring coupled to an end of the first light emitting element in the first area and that extends in the first direction and at least one second wiring coupled to an end of the second light emitting element in the second area and that extends in the first direction, wherein the first wiring and the second wiring are electrically isolated from each other.

Abstract: A satellite antenna positioner having a satellite tracking function according to the present invention relates to a satellite antenna positioner which has a satellite tracking function, supports an antenna, and is configured to direct the antenna on the basis of a satellite reception signal, the satellite antenna positioner comprising: a first motor for generating a driving force for adjusting an elevation angle of the antenna; a second motor for generating a driving force for adjusting an azimuth angle of the antenna; and a control module for controlling the first motor and the second motor on the basis of the sensitivity of the satellite reception signal, wherein the control module calculates an average value of satellite reception signals received in the process of driving at least one of the first motor and the second motor during a preset time, and controls at least one of the first motor and the second motor on the basis of the average value of the satellite reception signals.

Abstract: A dipole alignment device includes an electric field forming part including a stage, and a probe part which form an electric field on the stage; an inkjet printing apparatus including at least one inkjet head which sprays ink including dipoles and a solvent with the dipoles dispersed therein onto the stage; a transportation part comprising a first moving part which moves the electric field forming part in at least one direction; and a light irradiation apparatus including a light irradiation part which applies light to the ink sprayed onto the stage.

Abstract: The present invention relates to a non-coating thermoplastic resin composition, a method for manufacturing a molded article by using the same, and a molded article manufactured by the same. More specifically, the present invention is characterized by providing the thermoplastic resin composition which contains polycarbonate, polysiloxane-polycarbonate copolymer, polyester, master-batched carbon black, and additives in specific contents and the molded article, which has excellent chemical resistance, mechanical properties, light resistance, hydrolysis resistance, and low glossiness, manufactured by using the same.

Abstract: A satellite antenna positioner having a satellite tracking function according to the present invention relates to a satellite antenna positioner which has a satellite tracking function, supports an antenna, and is configured to direct the antenna on the basis of a satellite reception signal, the satellite antenna positioner comprising: a first motor for generating a driving force for adjusting an elevation angle of the antenna; a second motor for generating a driving force for adjusting an azimuth angle of the antenna; and a control module for controlling the first motor and the second motor on the basis of the sensitivity of the satellite reception signal, wherein the control module calculates an average value of satellite reception signals received in the process of driving at least one of the first motor and the second motor during a preset time, and controls at least one of the first motor and the second motor on the basis of the average value of the satellite reception signals.

Abstract: A semiconductor memory device includes a source layer, a channel structure, gate electrodes on the source layer and spaced apart on a sidewall of the channel structure, and a common source line. The gate electrodes include a first word line group including first and second gate electrodes and a second word line group including third and fourth gate electrodes. The semiconductor memory device, in response to a voltage of the common source line reaching a target voltage, causes an inhibition voltage to be applied to the second word line group and an erase voltage to be applied to the first word line group in a first erase operation interval, and causes the inhibition voltage to be applied to the first word line group and the erase voltage to be applied to the second word line group in a second erase operation interval.

Abstract: There is provided an additive for secondary battery electrolyte, containing aluminum silicate. The aluminum silicate has a particle size of 200 nm to 20 ?m. The aluminum silicate has a mass ratio of 60 to 70 wt % of oxygen (O), 0.1 to 2.0 wt % of aluminum (Al), and 25 to 35 wt % of silicon (Si). The aluminum silicate has a surface area of 50 to 1,000 m2/g. The aluminum silicate has a pore size of 0.1 to 20 nm.

Abstract: There is provided an additive, containing magnesium silicate, for a secondary battery electrolyte and a preparation method therefor. The magnesium silicate has a mass ratio of 50 to 70 wt % of oxygen (O), 5 to 20 wt % of magnesium (Al), and 15 to 35 wt % of silicon (Si). The magnesium silicate has a surface area of 50 to 500 m2/g. The magnesium silicate has a pore size of 0.1 to 20 nm.

Abstract: A semiconductor memory device includes a source layer, a channel structure, gate electrodes on the source layer and spaced apart on a sidewall of the channel structure, and a common source line. The gate electrodes include a first word line group including first and second gate electrodes and a second word line group including third and fourth gate electrodes. The semiconductor memory device, in response to a voltage of the common source line reaching a target voltage, causes an inhibition voltage to be applied to the second word line group and an erase voltage to be applied to the first word line group in a first erase operation interval, and causes the inhibition voltage to be applied to the first word line group and the erase voltage to be applied to the second word line group in a second erase operation interval.

Abstract: A semiconductor memory device includes a source layer, a channel structure, gate electrodes on the source layer and spaced apart on a sidewall of the channel structure, and a common source line. The gate electrodes include a first word line group including first and second gate electrodes and a second word line group including third and fourth gate electrodes. The semiconductor memory device, in response to a voltage of the common source line reaching a target voltage, causes an inhibition voltage to be applied to the second word line group and an erase voltage to be applied to the first word line group in a first erase operation interval, and causes the inhibition voltage to be applied to the first word line group and the erase voltage to be applied to the second word line group in a second erase operation interval.

Abstract: A non-volatile memory device including: a memory cell array including non-volatile memory blocks connected to a plurality of word lines, a plurality of bit lines and a common source line; a common source line driver configured to supply a common source line voltage to the common source line; a page buffer unit configured to supply a bit line voltage to at least one of the plurality of bit lines; a control logic circuit configured to adjust the common source line voltage and the bit line voltage; and a channel initialization circuit, wherein the channel initialization circuit sets the common source line voltage and the bit line voltage to an initialization pulse, and the channel initialization circuit applies the initialization pulse between a plurality of read sections in which a read voltage is applied to at least two of the plurality of word lines.

Abstract: A semiconductor memory device includes a stack structure including electrodes and insulating layers alternately stacked on a substrate, and a vertical channel structure penetrating the stack structure. The vertical channel structure includes a semiconductor pattern and a vertical insulating layer between the semiconductor pattern and the electrodes. The vertical insulating layer includes a charge storage layer, a filling insulating layer, and a tunnel insulating layer. The vertical insulating layer has a cell region between the semiconductor pattern and each electrode and a cell separation region between the semiconductor pattern and each insulating layer. A portion of the charge storage layer of the cell region is in physical contact with the tunnel insulating layer. The filling insulating layer is between the semiconductor pattern and a remaining portion of the charge storage layer of the cell region.

Abstract: Disclosed herein is an inclined thin film solar cell. The inclined thin film solar cell includes a substrate including at least one first surface having a surface inclined at a first angle with respect to the bottom surface of the substrate and at least one second surface located adjacent to the first surface and having a surface which is connected to a next inclined surface and inclined at a second angle, a first electrode famed on a surface of the substrate, a light absorbing layer famed on the first electrode, and a second electrode formed on the light absorbing layer.

Abstract: A non-volatile memory device including: a memory cell array including non-volatile memory blocks connected to a plurality of word lines, a plurality of bit lines and a common source line; a common source line driver configured to supply a common source line voltage to the common source line; a page buffer unit configured to supply a bit line voltage to at least one of the plurality of bit lines; a control logic circuit configured to adjust the common source line voltage and the bit line voltage; and a channel initialization circuit, wherein the channel initialization circuit sets the common source line voltage and the bit line voltage to an initialization pulse, and the channel initialization circuit applies the initialization pulse between a plurality of read sections in which a read voltage is applied to at least two of the plurality of word lines.

Abstract: A three-dimensional semiconductor memory device including a stack structure including gate structures and first dielectric patterns alternately stacked, a vertical channel penetrating the stack structure, and a charge storage layer extending from between the vertical channel and the first gate structures to between the vertical channel and the first dielectric patterns. The gate structures include first gate structures having a top surface and a bottom surface facing each other and having different width. The charge storage layer includes first segments between the vertical channel and the first gate structures, and second segments between the vertical channel and the first dielectric patterns. A thickness of the first segments is greater than a thickness of the second segments. One of the width of the top surface and the width of bottom surface of each first gate structure is the same as that of a first dielectric pattern on the first gate structure.

Abstract: Disclosed herein is an inclined thin film solar cell. The inclined thin film solar cell includes a substrate including at least one first surface having a surface inclined at a first angle with respect to the bottom surface of the substrate and at least one second surface located adjacent to the first surface and having a surface which is connected to a next inclined surface and inclined at a second angle, a first electrode famed on a surface of the substrate, a light absorbing layer famed on the first electrode, and a second electrode formed on the light absorbing layer.

Abstract: A three-dimensional semiconductor memory device including a stack structure including gate structures and first dielectric patterns alternately stacked, a vertical channel penetrating the stack structure, and a charge storage layer extending from between the vertical channel and the first gate structures to between the vertical channel and the first dielectric patterns. The gate structures include first gate structures having a top surface and a bottom surface facing each other and having different width. The charge storage layer includes first segments between the vertical channel and the first gate structures, and second segments between the vertical channel and the first dielectric patterns. A thickness of the first segments is greater than a thickness of the second segments. One of the width of the top surface and the width of bottom surface of each first gate structure is the same as that of a first dielectric pattern on the first gate structure.

Abstract: A semiconductor memory device includes a stack structure including electrodes and insulating layers alternately stacked on a substrate, and a vertical channel structure penetrating the stack structure. The vertical channel structure includes a semiconductor pattern and a vertical insulating layer between the semiconductor pattern and the electrodes. The vertical insulating layer includes a charge storage layer, a filling insulating layer, and a tunnel insulating layer. The vertical insulating layer has a cell region between the semiconductor pattern and each electrode and a cell separation region between the semiconductor pattern and each insulating layer. A portion of the charge storage layer of the cell region is in physical contact with the tunnel insulating layer. The filling insulating layer is between the semiconductor pattern and a remaining portion of the charge storage layer of the cell region.