Abstract: The present invention relates to a method and system for providing language learning services. The method of providing language learning services, according to the present invention, the method may include: activating, in response to receiving an input for acquiring a learning target image through a user terminal, a camera of the user terminal; specifying at least a portion of an image taken by the camera as the learning target image; receiving language learning information for the learning target image from a server; providing the language learning information to the user terminal; and storing, based on a request for storing of the language learning information, the language learning information in association with the learning target image, such that the learning target image is used in conjunction with learning of the language learning information.

Abstract: A display device includes a sensing circuit and a controller which selects a pixel row in a frame period. A vertical blank period of the frame period includes a sensing time in which the sensing circuit performs a sensing operation for the selected pixel row. The sensing circuit measures a first source voltage of a driving transistor of a pixel in the selected pixel row at a first time point of the sensing time, and measures a second source voltage of the driving transistor at a second time point of the sensing time. The controller calculates a threshold voltage parameter and a mobility parameter based on the first and second source voltages, predicts a saturated source voltage of the driving transistor based on the threshold voltage parameter and the mobility parameter, and calculates a threshold voltage of the driving transistor based on the saturated source voltage.

Abstract: There is provided an additive, containing magnesium silicate, for a secondary battery electrolyte and a preparation method therefor. The magnesium silicate has a mass ratio of 50 to 70 wt % of oxygen (O), 5 to 20 wt % of magnesium (Al), and 15 to 35 wt % of silicon (Si). The magnesium silicate has a surface area of 50 to 500 m2/g. The magnesium silicate has a pore size of 0.1 to 20 nm.

Abstract: There is provided an additive for secondary battery electrolyte, containing aluminum silicate. The aluminum silicate has a particle size of 200 nm to 20 ?m. The aluminum silicate has a mass ratio of 60 to 70 wt % of oxygen (O), 0.1 to 2.0 wt % of aluminum (Al), and 25 to 35 wt % of silicon (Si). The aluminum silicate has a surface area of 50 to 1,000 m2/g. The aluminum silicate has a pore size of 0.1 to 20 nm.

Abstract: An organic light emitting display device driven at a first driving frequency or a second driving frequency lower than the first driving frequency includes pixels coupled to first scan lines, second scan lines, and data lines, a first scan driver configured to supply scan signals to the first scan lines during a first period and a second period in one frame period, when the organic light emitting display device is driven at the second driving frequency, a second scan driver configured to supply scan signals to the second scan lines during the first period, when the organic light emitting display device is driven at the second driving frequency, and a data driver configured to supply a data signal to the data lines during the first period.

Abstract: A semiconductor memory device includes a source layer, a channel structure, gate electrodes on the source layer and spaced apart on a sidewall of the channel structure, and a common source line. The gate electrodes include a first word line group including first and second gate electrodes and a second word line group including third and fourth gate electrodes. The semiconductor memory device, in response to a voltage of the common source line reaching a target voltage, causes an inhibition voltage to be applied to the second word line group and an erase voltage to be applied to the first word line group in a first erase operation interval, and causes the inhibition voltage to be applied to the first word line group and the erase voltage to be applied to the second word line group in a second erase operation interval.

Abstract: A semiconductor memory device includes a source layer, a channel structure, gate electrodes on the source layer and spaced apart on a sidewall of the channel structure, and a common source line. The gate electrodes include a first word line group including first and second gate electrodes and a second word line group including third and fourth gate electrodes. The semiconductor memory device, in response to a voltage of the common source line reaching a target voltage, causes an inhibition voltage to be applied to the second word line group and an erase voltage to be applied to the first word line group in a first erase operation interval, and causes the inhibition voltage to be applied to the first word line group and the erase voltage to be applied to the second word line group in a second erase operation interval.

Abstract: A non-volatile memory device including: a memory cell array including non-volatile memory blocks connected to a plurality of word lines, a plurality of bit lines and a common source line; a common source line driver configured to supply a common source line voltage to the common source line; a page buffer unit configured to supply a bit line voltage to at least one of the plurality of bit lines; a control logic circuit configured to adjust the common source line voltage and the bit line voltage; and a channel initialization circuit, wherein the channel initialization circuit sets the common source line voltage and the bit line voltage to an initialization pulse, and the channel initialization circuit applies the initialization pulse between a plurality of read sections in which a read voltage is applied to at least two of the plurality of word lines.

Abstract: A semiconductor memory device includes a stack structure including electrodes and insulating layers alternately stacked on a substrate, and a vertical channel structure penetrating the stack structure. The vertical channel structure includes a semiconductor pattern and a vertical insulating layer between the semiconductor pattern and the electrodes. The vertical insulating layer includes a charge storage layer, a filling insulating layer, and a tunnel insulating layer. The vertical insulating layer has a cell region between the semiconductor pattern and each electrode and a cell separation region between the semiconductor pattern and each insulating layer. A portion of the charge storage layer of the cell region is in physical contact with the tunnel insulating layer. The filling insulating layer is between the semiconductor pattern and a remaining portion of the charge storage layer of the cell region.

Abstract: Disclosed herein is an inclined thin film solar cell. The inclined thin film solar cell includes a substrate including at least one first surface having a surface inclined at a first angle with respect to the bottom surface of the substrate and at least one second surface located adjacent to the first surface and having a surface which is connected to a next inclined surface and inclined at a second angle, a first electrode famed on a surface of the substrate, a light absorbing layer famed on the first electrode, and a second electrode formed on the light absorbing layer.

Abstract: A non-volatile memory device including: a memory cell array including non-volatile memory blocks connected to a plurality of word lines, a plurality of bit lines and a common source line; a common source line driver configured to supply a common source line voltage to the common source line; a page buffer unit configured to supply a bit line voltage to at least one of the plurality of bit lines; a control logic circuit configured to adjust the common source line voltage and the bit line voltage; and a channel initialization circuit, wherein the channel initialization circuit sets the common source line voltage and the bit line voltage to an initialization pulse, and the channel initialization circuit applies the initialization pulse between a plurality of read sections in which a read voltage is applied to at least two of the plurality of word lines.

Abstract: A three-dimensional semiconductor memory device including a stack structure including gate structures and first dielectric patterns alternately stacked, a vertical channel penetrating the stack structure, and a charge storage layer extending from between the vertical channel and the first gate structures to between the vertical channel and the first dielectric patterns. The gate structures include first gate structures having a top surface and a bottom surface facing each other and having different width. The charge storage layer includes first segments between the vertical channel and the first gate structures, and second segments between the vertical channel and the first dielectric patterns. A thickness of the first segments is greater than a thickness of the second segments. One of the width of the top surface and the width of bottom surface of each first gate structure is the same as that of a first dielectric pattern on the first gate structure.

Abstract: Disclosed herein is an inclined thin film solar cell. The inclined thin film solar cell includes a substrate including at least one first surface having a surface inclined at a first angle with respect to the bottom surface of the substrate and at least one second surface located adjacent to the first surface and having a surface which is connected to a next inclined surface and inclined at a second angle, a first electrode famed on a surface of the substrate, a light absorbing layer famed on the first electrode, and a second electrode formed on the light absorbing layer.

Abstract: A three-dimensional semiconductor memory device including a stack structure including gate structures and first dielectric patterns alternately stacked, a vertical channel penetrating the stack structure, and a charge storage layer extending from between the vertical channel and the first gate structures to between the vertical channel and the first dielectric patterns. The gate structures include first gate structures having a top surface and a bottom surface facing each other and having different width. The charge storage layer includes first segments between the vertical channel and the first gate structures, and second segments between the vertical channel and the first dielectric patterns. A thickness of the first segments is greater than a thickness of the second segments. One of the width of the top surface and the width of bottom surface of each first gate structure is the same as that of a first dielectric pattern on the first gate structure.

Abstract: A semiconductor memory device includes a stack structure including electrodes and insulating layers alternately stacked on a substrate, and a vertical channel structure penetrating the stack structure. The vertical channel structure includes a semiconductor pattern and a vertical insulating layer between the semiconductor pattern and the electrodes. The vertical insulating layer includes a charge storage layer, a filling insulating layer, and a tunnel insulating layer. The vertical insulating layer has a cell region between the semiconductor pattern and each electrode and a cell separation region between the semiconductor pattern and each insulating layer. A portion of the charge storage layer of the cell region is in physical contact with the tunnel insulating layer. The filling insulating layer is between the semiconductor pattern and a remaining portion of the charge storage layer of the cell region.

Abstract: A magnetic sheet having a magnetic material particle comprising a hexaferrite and a nanofiber matrix made of two or more nanofibers, wherein the magnetic material particle is dispersed in the nanofiber matrix. A manufacturing method thereof and a speaker including the magnetic sheet are also provided.

Abstract: The present invention provides a 3-dimensional P-N junction solar cell composed of a base board coated with a back plate on the upper face of the same; a P type semiconductor thin film formed on the top side of the back plate which has a 3-dimensional porous structure and is composed of P type semiconductor crystal grains; a N type buffer layer formed on the surface of the crystal grains of the said P type semiconductor thin film with playing a role of coating the thin film; and a transparent electrode formed on the surface of the crystal grains of the P type semiconductor thin film on which the N type buffer layer is formed. The solar cell of the present invention is a P-N junction solar cell including a 3-dimensional photo catalytic thin film, which can provide an improved photoelectric conversion efficiency, compared with the conventional P-N junction solar cell, owing to the formation of the N-type buffer layer on the surface of the crystal grains of the 3-dimensional P type semiconductor thin film.

Abstract: Disclosed is a thin film solar cell including a substrate, a first electrode, a light absorbing layer, a buffer layer, a window layer, and a second electrode, wherein a compound layer of MxSy or MxSey (here, M is metal, and x and y each are a natural number) is present in an interface between the first electrode and the light absorbing layer, the thickness of the compound layer of MxSy or MxSey being 150 nm or less.

Abstract: A magnetic sheet having a magnetic material particle comprising a hexaferrite and a nanofiber matrix made of two or more nanofibers, wherein the magnetic material particle is dispersed in the nanofiber matrix. A manufacturing method thereof and a speaker including the magnetic sheet are also provided.

Abstract: An operating method of a nonvolatile memory device is provided which sequentially performs a plurality of erase loops to erase at least one of a plurality of memory blocks. The operating method comprises performing at least one of the plurality of erase loops; performing a post-program operation on the at least one memory block after the at least one erase loop is executed; and performing remaining erase loops of the plurality of erase loops. The post-program operation is not performed when each of the remaining erase loops is executed.