Abstract: A circuit stage including a first transistor including a first electrode and a gate electrode, the first electrode being coupled to a first input terminal and the gate electrode being coupled to a second input terminal configured to receive a first clock signal, an output circuit coupled to the second input terminal and a second power input terminal, an input circuit coupled to a second electrode of the first transistor and to a third input terminal, the third input terminal being configured to receive a first control clock signal, the input circuit being configured to control voltages of the second node and a third node, a first driving circuit coupled to a first power input terminal and to a fourth input terminal configured to receive a second control clock signal, and a second driving circuit coupled to the fourth input terminal and the third node.

Abstract: A multi-band shark fin antenna for a vehicle comprises: a base; a substrate coupled to an upper portion of the base and on which feed lines are formed; and a first antenna frame coupled on the substrate and to which a plurality of radiators are coupled, wherein the first antenna frame comprises: a first radiator coupling part to which a first radiator is coupled; and a first support extending from the first radiator coupling part and supporting the first radiator coupling part, wherein an antenna coil is coupled to an outer circumferential surface of the first support, and the antenna coil is electrically connected to the first radiator.

Abstract: An automatic supply apparatus of secondary battery electrodes, which includes an electrode supply hoist 120; a supply shuttle 130 receiving electrodes in the form of reels from the electrode supply hoist 120; a first unwinder 140 and a second unwinder 150 disposed at a position the supply shuttle 130 comes forward. A notching facility 110 is disposed at a position where the supply shuttle 130 comes forward, and the first unwinder 140 is disposed in the notching facility 110, the second unwinder 150 is mounted on the notching facility 110 and disposed at a downward position of the first unwinder 140, and a tape supply device 160 is provided at a front position of the notching facility 110 so as to be disposed above the first unwinder 140.

Abstract: A semiconductor memory device includes a source layer, a channel structure, gate electrodes on the source layer and spaced apart on a sidewall of the channel structure, and a common source line. The gate electrodes include a first word line group including first and second gate electrodes and a second word line group including third and fourth gate electrodes. The semiconductor memory device, in response to a voltage of the common source line reaching a target voltage, causes an inhibition voltage to be applied to the second word line group and an erase voltage to be applied to the first word line group in a first erase operation interval, and causes the inhibition voltage to be applied to the first word line group and the erase voltage to be applied to the second word line group in a second erase operation interval.

Abstract: A satellite antenna positioner having a satellite tracking function according to the present invention relates to a satellite antenna positioner which has a satellite tracking function, supports an antenna, and is configured to direct the antenna on the basis of a satellite reception signal, the satellite antenna positioner comprising: a first motor for generating a driving force for adjusting an elevation angle of the antenna; a second motor for generating a driving force for adjusting an azimuth angle of the antenna; and a control module for controlling the first motor and the second motor on the basis of the sensitivity of the satellite reception signal, wherein the control module calculates an average value of satellite reception signals received in the process of driving at least one of the first motor and the second motor during a preset time, and controls at least one of the first motor and the second motor on the basis of the average value of the satellite reception signals.

Abstract: A satellite antenna positioner having a satellite tracking function according to the present invention relates to a satellite antenna positioner which has a satellite tracking function, supports an antenna, and is configured to direct the antenna on the basis of a satellite reception signal, the satellite antenna positioner comprising: a first motor for generating a driving force for adjusting an elevation angle of the antenna; a second motor for generating a driving force for adjusting an azimuth angle of the antenna; and a control module for controlling the first motor and the second motor on the basis of the sensitivity of the satellite reception signal, wherein the control module calculates an average value of satellite reception signals received in the process of driving at least one of the first motor and the second motor during a preset time, and controls at least one of the first motor and the second motor on the basis of the average value of the satellite reception signals.

Abstract: A semiconductor memory device includes a source layer, a channel structure, gate electrodes on the source layer and spaced apart on a sidewall of the channel structure, and a common source line. The gate electrodes include a first word line group including first and second gate electrodes and a second word line group including third and fourth gate electrodes. The semiconductor memory device, in response to a voltage of the common source line reaching a target voltage, causes an inhibition voltage to be applied to the second word line group and an erase voltage to be applied to the first word line group in a first erase operation interval, and causes the inhibition voltage to be applied to the first word line group and the erase voltage to be applied to the second word line group in a second erase operation interval.

Abstract: There is provided an additive for secondary battery electrolyte, containing aluminum silicate. The aluminum silicate has a particle size of 200 nm to 20 ?m. The aluminum silicate has a mass ratio of 60 to 70 wt % of oxygen (O), 0.1 to 2.0 wt % of aluminum (Al), and 25 to 35 wt % of silicon (Si). The aluminum silicate has a surface area of 50 to 1,000 m2/g. The aluminum silicate has a pore size of 0.1 to 20 nm.

Abstract: There is provided an additive, containing magnesium silicate, for a secondary battery electrolyte and a preparation method therefor. The magnesium silicate has a mass ratio of 50 to 70 wt % of oxygen (O), 5 to 20 wt % of magnesium (Al), and 15 to 35 wt % of silicon (Si). The magnesium silicate has a surface area of 50 to 500 m2/g. The magnesium silicate has a pore size of 0.1 to 20 nm.

Abstract: A semiconductor memory device includes a source layer, a channel structure, gate electrodes on the source layer and spaced apart on a sidewall of the channel structure, and a common source line. The gate electrodes include a first word line group including first and second gate electrodes and a second word line group including third and fourth gate electrodes. The semiconductor memory device, in response to a voltage of the common source line reaching a target voltage, causes an inhibition voltage to be applied to the second word line group and an erase voltage to be applied to the first word line group in a first erase operation interval, and causes the inhibition voltage to be applied to the first word line group and the erase voltage to be applied to the second word line group in a second erase operation interval.

Abstract: A semiconductor memory device includes a source layer, a channel structure, gate electrodes on the source layer and spaced apart on a sidewall of the channel structure, and a common source line. The gate electrodes include a first word line group including first and second gate electrodes and a second word line group including third and fourth gate electrodes. The semiconductor memory device, in response to a voltage of the common source line reaching a target voltage, causes an inhibition voltage to be applied to the second word line group and an erase voltage to be applied to the first word line group in a first erase operation interval, and causes the inhibition voltage to be applied to the first word line group and the erase voltage to be applied to the second word line group in a second erase operation interval.

Abstract: A non-volatile memory device including: a memory cell array including non-volatile memory blocks connected to a plurality of word lines, a plurality of bit lines and a common source line; a common source line driver configured to supply a common source line voltage to the common source line; a page buffer unit configured to supply a bit line voltage to at least one of the plurality of bit lines; a control logic circuit configured to adjust the common source line voltage and the bit line voltage; and a channel initialization circuit, wherein the channel initialization circuit sets the common source line voltage and the bit line voltage to an initialization pulse, and the channel initialization circuit applies the initialization pulse between a plurality of read sections in which a read voltage is applied to at least two of the plurality of word lines.

Abstract: A semiconductor memory device includes a stack structure including electrodes and insulating layers alternately stacked on a substrate, and a vertical channel structure penetrating the stack structure. The vertical channel structure includes a semiconductor pattern and a vertical insulating layer between the semiconductor pattern and the electrodes. The vertical insulating layer includes a charge storage layer, a filling insulating layer, and a tunnel insulating layer. The vertical insulating layer has a cell region between the semiconductor pattern and each electrode and a cell separation region between the semiconductor pattern and each insulating layer. A portion of the charge storage layer of the cell region is in physical contact with the tunnel insulating layer. The filling insulating layer is between the semiconductor pattern and a remaining portion of the charge storage layer of the cell region.

Abstract: Disclosed herein is an inclined thin film solar cell. The inclined thin film solar cell includes a substrate including at least one first surface having a surface inclined at a first angle with respect to the bottom surface of the substrate and at least one second surface located adjacent to the first surface and having a surface which is connected to a next inclined surface and inclined at a second angle, a first electrode famed on a surface of the substrate, a light absorbing layer famed on the first electrode, and a second electrode formed on the light absorbing layer.

Abstract: A non-volatile memory device including: a memory cell array including non-volatile memory blocks connected to a plurality of word lines, a plurality of bit lines and a common source line; a common source line driver configured to supply a common source line voltage to the common source line; a page buffer unit configured to supply a bit line voltage to at least one of the plurality of bit lines; a control logic circuit configured to adjust the common source line voltage and the bit line voltage; and a channel initialization circuit, wherein the channel initialization circuit sets the common source line voltage and the bit line voltage to an initialization pulse, and the channel initialization circuit applies the initialization pulse between a plurality of read sections in which a read voltage is applied to at least two of the plurality of word lines.

Abstract: A three-dimensional semiconductor memory device including a stack structure including gate structures and first dielectric patterns alternately stacked, a vertical channel penetrating the stack structure, and a charge storage layer extending from between the vertical channel and the first gate structures to between the vertical channel and the first dielectric patterns. The gate structures include first gate structures having a top surface and a bottom surface facing each other and having different width. The charge storage layer includes first segments between the vertical channel and the first gate structures, and second segments between the vertical channel and the first dielectric patterns. A thickness of the first segments is greater than a thickness of the second segments. One of the width of the top surface and the width of bottom surface of each first gate structure is the same as that of a first dielectric pattern on the first gate structure.

Abstract: Disclosed herein is an inclined thin film solar cell. The inclined thin film solar cell includes a substrate including at least one first surface having a surface inclined at a first angle with respect to the bottom surface of the substrate and at least one second surface located adjacent to the first surface and having a surface which is connected to a next inclined surface and inclined at a second angle, a first electrode famed on a surface of the substrate, a light absorbing layer famed on the first electrode, and a second electrode formed on the light absorbing layer.

Abstract: A three-dimensional semiconductor memory device including a stack structure including gate structures and first dielectric patterns alternately stacked, a vertical channel penetrating the stack structure, and a charge storage layer extending from between the vertical channel and the first gate structures to between the vertical channel and the first dielectric patterns. The gate structures include first gate structures having a top surface and a bottom surface facing each other and having different width. The charge storage layer includes first segments between the vertical channel and the first gate structures, and second segments between the vertical channel and the first dielectric patterns. A thickness of the first segments is greater than a thickness of the second segments. One of the width of the top surface and the width of bottom surface of each first gate structure is the same as that of a first dielectric pattern on the first gate structure.

Abstract: A semiconductor memory device includes a stack structure including electrodes and insulating layers alternately stacked on a substrate, and a vertical channel structure penetrating the stack structure. The vertical channel structure includes a semiconductor pattern and a vertical insulating layer between the semiconductor pattern and the electrodes. The vertical insulating layer includes a charge storage layer, a filling insulating layer, and a tunnel insulating layer. The vertical insulating layer has a cell region between the semiconductor pattern and each electrode and a cell separation region between the semiconductor pattern and each insulating layer. A portion of the charge storage layer of the cell region is in physical contact with the tunnel insulating layer. The filling insulating layer is between the semiconductor pattern and a remaining portion of the charge storage layer of the cell region.

Abstract: A magnetic sheet having a magnetic material particle comprising a hexaferrite and a nanofiber matrix made of two or more nanofibers, wherein the magnetic material particle is dispersed in the nanofiber matrix. A manufacturing method thereof and a speaker including the magnetic sheet are also provided.