Abstract: Techniques are described for implementing a square-gate source-follower (SGSF) transistor for integration with complementary metal-oxide semiconductor (CMOS) image sensor (CIS) pixels. The SGSF transistor can have an active layer with active regions, including a drain region separated from each of two source regions to form parallel current channels. A square-gate structure layer includes main-gate regions, each disposed above a corresponding one of the current channels, and a side-gate region to couple the main-gate regions. At a particular physical width (W) and current channel length (L), the parallel current channels can act similarly to a conventional linear source-follower having dimensions of 2W and the same L. SGSF implementations can provide a number of features, including higher frame rate, lower power consumption, and lower noise, as compared to those of a conventional source-follower transistor of comparable W and L dimensions.

Abstract: Techniques are described for efficient high-resolution output of an image captured using a high-pixel-count image sensor based on pixel binning followed by luminance-guided umsampling. For example, an image sensor array is configured according to a red-green-blue-luminance (RGBL) CFA pattern, such that at least 50-percent of the imaging pixels of the array are luminance (L) pixels. Pixel binning is used during readout of the array to concurrently generate a downsampled RGB capture frame and a downsampled L capture frame. Following the readout, the L capture frame is upsampled (e.g., by upscaling and interpolation) to generate an L guide frame with 100-percent luminance density. An upsampled RGB frame can then be generated by interpolating the RGB capture frame based both on known neighboring RGB information (e.g., from the RGB capture frame and previously interpolated information), as adjusted based on local luminance information from the L guide frame.

Abstract: A trench-gate source-follower (TGSF) transistor is described, such as for integration with image sensor pixels. The TGSF transistor is at least partially built into a trench etched into a substrate. A contiguous doped region is implanted around the inner walls of the trench to form a buried-trench current channel. A trench-gate is formed to have at least a buried portion that fills the volume of the trench. A gate oxide layer can be disposed between the buried portion of the trench-gate and the buried-trench current channel. Drain and source regions are formed on either end of the trench-gate. Activating the trench-gate causes current to flow between the drain and source regions via the buried-trench current channel around the buried portion of the trench-gate. The geometry of the buried-trench current channel can effectively increase the width of the active region of the source-follower transistor without increasing its physical layout width.

Abstract: A hybrid ferroelectric-metal-oxide-semiconductor field effect transistor (Fe-MOSFET) device is described, such as for incorporation into in-pixel circuitry of an imaging pixel array to provide both reset and dual conversion gain features. The Fe-MOSFET includes source and drain regions implanted in a semiconductor substrate and separated by a channel region. The source region can be the floating diffusion region of a photosensor. A gate structure is deposited on the substrate directly above at least the channel region and an isolating layer is formed on the surface of the substrate to electrically isolate the gate structure from at least the channel region. The isolating layer is split into a Fe segment of ferroelectric material that can be written to different polarization states for conversion gain control, and a dielectric segment that can be used for current channel formation in the channel region.

Abstract: Techniques are described for efficient high-resolution output of an image captured using a high-pixel-count image sensor based on pixel binning followed by luminance-guided umsampling. For example, an image sensor array is configured according to a red-green-blue-luminance (RGBL) CFA pattern, such that at least 50-percent of the imaging pixels of the array are luminance (L) pixels. Pixel binning is used during readout of the array to concurrently generate a downsampled RGB capture frame and a downsampled L capture frame. Following the readout, the L capture frame is upsampled (e.g., by upscaling and interpolation) to generate an L guide frame with 100-percent luminance density. An upsampled RGB frame can then be generated by interpolating the RGB capture frame based both on known neighboring RGB information (e.g., from the RGB capture frame and previously interpolated information), as adjusted based on local luminance information from the L guide frame.

Abstract: Techniques are described for implementing a split-select-block (split-SEL) complementary metal-oxide semiconductor (CMOS) image sensor (CIS) pixel physical architecture, such as for reducing noise in low-light application contexts. The split-SEL CIS pixel physical architecture can include a pixel block with one or more photodiodes. Above the photodiodes, there can be: a first oxide diffusion region with a reset block and a gain block disposed thereon; and a second oxide diffusion region with a select block disposed thereon. Below the photodiodes, there can be a third oxide diffusion region with a source follower (SF) block (e.g., a square-gate SF transistor) disposed thereon. A trace can be routed through the set of photodiodes to couple the source of the SF block with the select block. The architecture permits an appreciable increase in the physical gate length and/or other features.

Abstract: Techniques are described for efficient staggered high-dynamic-range (HDR) output of an image captured using a high-pixel-count image sensor based on pixel binning followed by luminance-guided upsampling. For example, an image sensor array is configured according to a red-green-blue-luminance (RGBL) CFA pattern, such that at least 50-percent of the imaging pixels of the array are luminance (L) pixels. In each image capture time window, multiple (e.g., three) luminance-enhanced (LE) component images are generated. Each LE component image is generated by exposing the image sensor to incident illumination for a respective amount of time, using pixel binning during readout to generate appreciably downsampled color and luminance capture frames, generating an upsampled luminance guide frame from the luminance capture frame, and using the upsampled luminance guide frame to guide upsampling (e.g., and remosaicking) of the color capture frame.

Abstract: Techniques are described for sampled bandgap reference generation for CMOS image sensor (CIS) applications. For example, the CIS includes a pixel array, one or more pixel analog to digital converters (ADCs), and a sampled bandgap reference generator, all integrated in close proximity on a chip. The ADCs rely on stable reference levels from the bandgap reference generator for performing pixel conversions for the pixel array. Embodiments of the sampled bandgap reference generator can operate according to reference generation cycles. Each cycle can include a first portion, in which an active core dynamically stabilizes the bandgap reference level; and a second portion, in which the core is deactivated, and the bandgap reference level is output based on a sampled level obtained during the preceding first portion of the cycle. The cycle timing can be controlled to achieve sufficient dynamic stabilization of the reference levels, while mitigating photon emissions from the core.

Abstract: A hybrid ferroelectric-metal-oxide-semiconductor field effect transistor (Fe-MOSFET) device is described, such as for incorporation into in-pixel circuitry of an imaging pixel array to provide both reset and dual conversion gain features. The Fe-MOSFET includes source and drain regions implanted in a semiconductor substrate and separated by a channel region. The source region can be the floating diffusion region of a photosensor. A gate structure is deposited on the substrate directly above at least the channel region and an isolating layer is formed on the surface of the substrate to electrically isolate the gate structure from at least the channel region. The isolating layer is split into a Fe segment of ferroelectric material that can be written to different polarization states for conversion gain control, and a dielectric segment that can be used for current channel formation in the channel region.

Abstract: Techniques are described for implementing a square-gate source-follower (SGSF) transistor for integration with complementary metal-oxide semiconductor (CMOS) image sensor (CIS) pixels. The SGSF transistor can have an active layer with active regions, including a drain region separated from each of two source regions to form parallel current channels. A square-gate structure layer includes main-gate regions, each disposed above a corresponding one of the current channels, and a side-gate region to couple the main-gate regions. At a particular physical width (W) and current channel length (L), the parallel current channels can act similarly to a conventional linear source-follower having dimensions of 2W and the same L. SGSF implementations can provide a number of features, including higher frame rate, lower power consumption, and lower noise, as compared to those of a conventional source-follower transistor of comparable W and L dimensions.

Abstract: A saddle-gate source follower transistor is described, such as for integration with in-pixel circuitry of complementary metal-oxide semiconductor (CMOS) image sensor (CIS) pixels. The saddle-gate source-follower transistor structure can include a channel region having a three-dimensional geometry defined on its axial sides by trenches. A gate oxide layer is formed over the top and axial sides of the channel region, and a saddle-gate structure is formed on the gate oxide layer. As such, the saddle-gate structure includes a seat portion extending over the top of the channel region, and first and second fender portions extending over the first and second axial sides of the channel region, such that the first and second fender portions are buried below an upper surface of the semiconductor substrate (e.g., buried into trenches formed in side isolation regions).

Abstract: An image sensor includes a pixel array comprising a plurality of pixels, a color filter array comprising a plurality of color filter clusters overlying the pixel array, and readout circuitry configured to concurrently provide the pixels sharing the common filter cluster and having a first exposure time to a readout line for digital data conversion. Each of the color filter clusters includes a group of same color filters, and pixels sharing a common color filter cluster have different exposure times.

Abstract: An image sensor includes a pixel array comprising a plurality of pixels, a color filter array comprising a plurality of color filter clusters overlying the pixel array, and readout circuitry configured to concurrently provide the pixels sharing the common filter cluster and having a first exposure time to a readout line for digital data conversion. Each of the color filter clusters includes a group of same color filters, and pixels sharing a common color filter cluster have different exposure times.

Abstract: A calibration current load is selectively coupled to an output of a pulse frequency modulated (PFM) DC-DC converter during a calibration operation to increase charge supplied from a battery supplying an input voltage to the converter. A voltage across a sense resistor in series with the battery is integrated during a measurement interval while the calibration current load is coupled to the output. A charge drawn per pulse from the battery is determined based on the sense resistor, the integrated voltage and the number of pulses during the measurement interval. Alternatively, a first PFM frequency is determined with a first calibration current load coupled to the converter output. A second PFM frequency is determined with a second calibration current load. The charge drawn per pulse from the battery is determined based on the first and second PFM frequencies and the first and second calibration current loads.

Abstract: The charge drawn from a battery during each switching event (pulse) of a pulse frequency modulated DC-DC converter is determined during a calibration period. based on differences in pulse rate with different current loading. Another approach calibration approach determines charge drawn from the battery by measuring voltage across a sense resistor while measuring the total pulse rate and while adding sufficient load current to ensure that the voltage is much larger than the residual offset of the measurement system. During operation, the system counts number of pulses are counted and the total charge drawn from the battery is determined based, at least in part, on the charge transferred per pulse during calibration, the operational mode, the battery voltage during calibration and operationally and the output voltage. Based on the total charge drawn and temperature (for temperature dependent battery types), the battery state of charge is estimated.

Abstract: A calibration current load is selectively coupled to an output of a pulse frequency modulated (PFM) DC-DC converter during a calibration operation to increase charge supplied from a battery supplying an input voltage to the converter. A voltage across a sense resistor in series with the battery is integrated during a measurement interval while the calibration current load is coupled to the output. A charge drawn per pulse from the battery is determined based on the sense resistor, the integrated voltage and the number of pulses during the measurement interval. Alternatively, a first PFM frequency is determined with a first calibration current load coupled to the converter output. A second PFM frequency is determined with a second calibration current load. The charge drawn per pulse from the battery is determined based on the first and second PFM frequencies and the first and second calibration current loads.

Abstract: The charge drawn from a battery during each switching event (pulse) of a pulse frequency modulated DC-DC converter is determined during a calibration period. based on differences in pulse rate with different current loading. Another approach calibration approach determines charge drawn from the battery by measuring voltage across a sense resistor while measuring the total pulse rate and while adding sufficient load current to ensure that the voltage is much larger than the residual offset of the measurement system. During operation, the system counts number of pulses are counted and the total charge drawn from the battery is determined based, at least in part, on the charge transferred per pulse during calibration, the operational mode, the battery voltage during calibration and operationally and the output voltage. Based on the total charge drawn and temperature (for temperature dependent battery types), the battery state of charge is estimated.

Abstract: In one embodiment, an apparatus includes a controller to control a voltage regulator. The controller may have a first comparator circuit to compare a first reference voltage to a feedback voltage. In turn, the first comparator circuit may include: a first comparator having a first input terminal to receive the feedback voltage and a second input terminal to receive the reference voltage and an output node to output an error signal based on the comparison; and a first pre-charge circuit coupled between the first input terminal and the output node configured to pre-charge a first portion of a compensation network to a pre-charge level. The first controller may further include a second comparator circuit coupled to the first comparator circuit compare the error signal to a ramp signal and to generate a first control output to control a power train of the voltage regulator in a first mode of operation.

Abstract: An integrated circuit (IC) includes a plurality of pads adapted to send or receive signals, and a plurality of mixed signal interface blocks, each of which is coupled to a corresponding pad in the plurality of pads. Furthermore, each mixed signal interface block in the plurality of mixed signal interface blocks is adapted to be configurable to provide selected functionality independently of the other mixed signal interface blocks.

Abstract: In one embodiment, an apparatus includes a controller to control a voltage regulator. The controller may have a first comparator circuit to compare a first reference voltage to a feedback voltage. In turn, the first comparator circuit may include: a first comparator having a first input terminal to receive the feedback voltage and a second input terminal to receive the reference voltage and an output node to output an error signal based on the comparison; and a first pre-charge circuit coupled between the first input terminal and the output node configured to pre-charge a first portion of a compensation network to a pre-charge level. The first controller may further include a second comparator circuit coupled to the first comparator circuit compare the error signal to a ramp signal and to generate a first control output to control a power train of the voltage regulator in a first mode of operation.