Abstract: An integrated circuit (IC) includes a plurality of pads adapted to send or receive signals, and a plurality of mixed signal interface blocks, each of which is coupled to a corresponding pad in the plurality of pads. Furthermore, each mixed signal interface block in the plurality of mixed signal interface blocks is adapted to be configurable to provide selected functionality independently of the other mixed signal interface blocks.

Abstract: An integrated circuit (IC) includes a plurality of pads adapted to send or receive signals, and a plurality of mixed signal interface blocks, each of which is coupled to a corresponding pad in the plurality of pads. Furthermore, each mixed signal interface block in the plurality of mixed signal interface blocks is adapted to be configurable to provide selected functionality independently of the other mixed signal interface blocks.

Abstract: A motor control apparatus to control a motor external to the motor control apparatus includes a microcontroller unit (MCU). The MCU includes mixed signal motor control circuitry adapted to perform back electromotive force (EMF) motor control in a first mode of operation. The mixed signal motor control circuitry is further adapted to perform field oriented control (FOC) in a second mode of operation.

Abstract: An integrated circuit (IC) includes a plurality of pads adapted to send or receive signals, and a plurality of mixed signal interface blocks, each of which is coupled to a corresponding pad in the plurality of pads. Furthermore, each mixed signal interface block in the plurality of mixed signal interface blocks is adapted to be configurable to provide selected functionality independently of the other mixed signal interface blocks.

Abstract: A circuit includes a comparator including a first input, a second input, and an output. The circuit further includes a plurality of capacitive sampling circuits configured to be selectively coupled to the first and second inputs. Each of the plurality of capacitive sampling circuits includes first and second capacitors, and includes first and second conversion switches configured to selectively couple the first and second capacitors to the first and second inputs, respectively. The first and second conversion switches of a selected one of the plurality of capacitive sampling circuits are closed to couple the selected one to the first and second inputs of the comparator during a conversion phase.

Abstract: An integrated circuit (IC) includes a plurality of pads adapted to send or receive signals, and a plurality of mixed signal interface blocks, each of which is coupled to a corresponding pad in the plurality of pads. Furthermore, each mixed signal interface block in the plurality of mixed signal interface blocks is adapted to be configurable to provide selected functionality independently of the other mixed signal interface blocks.

Abstract: Techniques are disclosed relating to supplying a power supply voltage to a gate driver. In one embodiment, an apparatus is disclosed that includes a first transistor configured to raise a voltage at a node and a second transistor configured to lower the voltage at the node. The apparatus further includes a first driver configured to receive a first power supply voltage, and to use the first power supply voltage to control a gate voltage of the first transistor. The apparatus further includes a second driver configured to receive a second power supply voltage, and to use the second power supply voltage to control a gate voltage of the second transistor. In such an embodiment, the apparatus includes a first regulator coupled to the first driver and configured to generate the first power supply voltage based on the second power supply voltage.

Abstract: A circuit includes a comparator including a first input, a second input, and an output. The circuit further includes a plurality of capacitive sampling circuits configured to be selectively coupled to the first and second inputs. Each of the plurality of capacitive sampling circuits includes first and second capacitors, and includes first and second conversion switches configured to selectively couple the first and second capacitors to the first and second inputs, respectively. The first and second conversion switches of a selected one of the plurality of capacitive sampling circuits are closed to couple the selected one to the first and second inputs of the comparator during a conversion phase.

Abstract: A motor control apparatus to control a motor external to the motor control apparatus includes a microcontroller unit (MCU). The MCU includes mixed signal motor control circuitry adapted to perform back electromotive force (EMF) motor control in a first mode of operation. The mixed signal motor control circuitry is further adapted to perform field oriented control (FOC) in a second mode of operation.

Abstract: An integrated circuit (IC) includes a plurality of pads adapted to communicate signals with a circuit external to the IC, and a first mixed signal interface block coupled to a first pad in the plurality of pads, where the first mixed signal interface block is adapted to receive a first trigger signal from the circuit external to the IC and to provide a second trigger signal. The IC further includes a second mixed signal interface block coupled to a second pad in the plurality of pads, where the second mixed signal interface block is adapted to receive and track a first input signal from the circuit external to the IC in a first mode of operation of the IC.

Abstract: An input digital signal is converted to an analog signal using a main digital to analog converter (DAC) and a sub DAC. An offset value is subtracted from the input digital signal to generate an offset adjusted digital signal. The main DAC converts the offset adjusted digital signal to a first analog signal. A second digital signal is generated based on the offset value and a correction factor determined, at least in part, during calibration of the main DAC. The sub DAC converts the second digital to a second analog signal, which when combined with the first analog signal, provides an analog representation of the input digital signal.

Abstract: An integrated circuit (IC) includes a plurality of pads adapted to send or receive signals, and a plurality of mixed signal interface blocks, each of which is coupled to a corresponding pad in the plurality of pads. Furthermore, each mixed signal interface block in the plurality of mixed signal interface blocks is adapted to be configurable to provide selected functionality independently of the other mixed signal interface blocks.

Abstract: An integrated circuit (IC) includes a plurality of pads adapted to communicate signals with a circuit external to the IC, and a first mixed signal interface block coupled to a first pad in the plurality of pads, where the first mixed signal interface block is adapted to receive a first trigger signal from the circuit external to the IC and to provide a second trigger signal. The IC further includes a second mixed signal interface block coupled to a second pad in the plurality of pads, where the second mixed signal interface block is adapted to receive and track a first input signal from the circuit external to the IC in a first mode of operation of the IC.

Abstract: An input digital signal is converted to an analog signal using a main digital to analog converter (DAC) and a sub DAC. An offset value is subtracted from the input digital signal to generate an offset adjusted digital signal. The main DAC converts the offset adjusted digital signal to a first analog signal. A second digital signal is generated based on the offset value and a correction factor determined, at least in part, during calibration of the main DAC. The sub DAC converts the second digital to a second analog signal, which when combined with the first analog signal, provides an analog representation of the input digital signal.

Abstract: Techniques are disclosed relating to charging and discharging gates of transistors. In one embodiment, an apparatus includes first and second drivers. The first driver is configured to discharge a gate of a first transistor, and to send a charge indication to the second driver in response to reaching a Miller plateau for the first transistor. The second driver is configured to charge a gate of a second transistor above a threshold voltage in response to receiving the charge indication. In some embodiments, the second driver is configured to begin charging the gate of the second transistor to a voltage below the threshold voltage when the first driver begins discharging the gate of the first transistor begins, and to wait to charge the gate of the second transistor above the threshold voltage until the charge indication has been received.

Abstract: Techniques are disclosed relating to charging and discharging a gate of transistor. In one embodiment, an apparatus is disclosed that includes a driver configured to discharge a gate of a transistor. The driver is configured to discharge the gate at a first rate until reaching a Miller plateau for the transistor, and to discharge the gate at a second rate after reaching the Miller plateau. In such an embodiment, the first rate is greater than the second rate. In some embodiments, the driver is also configured to charge the gate of the transistor at a third rate until reaching a Miller plateau for the transistor, and to charge the gate at a fourth rate after reaching the Miller plateau, the third rate being greater than the fourth rate. In some embodiments, the apparatus is a class D amplifier.

Abstract: Techniques are disclosed relating to supplying a power supply voltage to a gate driver. In one embodiment, an apparatus is disclosed that includes a first transistor configured to raise a voltage at a node and a second transistor configured to lower the voltage at the node. The apparatus further includes a first driver configured to receive a first power supply voltage, and to use the first power supply voltage to control a gate voltage of the first transistor. The apparatus further includes a second driver configured to receive a second power supply voltage, and to use the second power supply voltage to control a gate voltage of the second transistor. In such an embodiment, the apparatus includes a first regulator coupled to the first driver and configured to generate the first power supply voltage based on the second power supply voltage.

Abstract: Techniques are disclosed relating to charging and discharging gates of transistors. In one embodiment, an apparatus includes first and second drivers. The first driver is configured to discharge a gate of a first transistor, and to send a charge indication to the second driver in response to reaching a Miller plateau for the first transistor. The second driver is configured to charge a gate of a second transistor above a threshold voltage in response to receiving the charge indication. In some embodiments, the second driver is configured to begin charging the gate of the second transistor to a voltage below the threshold voltage when the first driver begins discharging the gate of the first transistor begins, and to wait to charge the gate of the second transistor above the threshold voltage until the charge indication has been received.

Abstract: Techniques are disclosed relating to charging and discharging a gate of transistor. In one embodiment, an apparatus is disclosed that includes a driver configured to discharge a gate of a transistor. The driver is configured to discharge the gate at a first rate until reaching a Miller plateau for the transistor, and to discharge the gate at a second rate after reaching the Miller plateau. In such an embodiment, the first rate is greater than the second rate. In some embodiments, the driver is also configured to charge the gate of the transistor at a third rate until reaching a Miller plateau for the transistor, and to charge the gate at a fourth rate after reaching the Miller plateau, the third rate being greater than the fourth rate. In some embodiments, the apparatus is a class D amplifier.

Abstract: A DC-DC digital pulse width modulated power supply is disclosed for generating a DC regulated output voltage. A digital control node has a digital control voltage disposed thereon for controlling the operation of the supply, wherein the digital control voltage has a substantially zero voltage when the output voltage of the supply is at a desired regulation, the digital control voltage having a resolution defined by a least significant bit (LSB). An input node receives a DC analog reference voltage defining the output voltage of the supply. A difference device determines the difference between the analog reference voltage and the output voltage to generate said digital control voltage. An LSB variation device varies the size of the LSB without varying the value of the digital control voltage for a substantially zero difference between the analog reference voltage and the output voltage.