Patents by Inventor Jishnu Bhattacharjee

Jishnu Bhattacharjee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6922440
    Abstract: An apparatus and method for adaptively introducing a compensating signal latency related to a signal latency of a data symbol decision circuit. Adaptive timing control circuitry, including an interpolating mixer implemented as a tapped delay line with correlated tap coefficients, introduces a latency adaptively and substantially matching the latency of the data decision circuit for use within an adaptive equalizer, thereby minimizing the mean-squared error of such decision circuit. This adaptive latency is used in generating the feedback error signal which, in turn, can be used by the feedforward equalizer for dynamically adjusting its adaptive filter tap coefficients.
    Type: Grant
    Filed: December 17, 2002
    Date of Patent: July 26, 2005
    Assignee: Scintera Networks, Inc.
    Inventors: Qian Yu, Venugopal Balasubramonian, Jishnu Bhattacharjee, Debanjan Mukherjee, Abhijit Phanse, Abhijit G. Shanbhag, Edem Ibragimov
  • Publication number: 20050110476
    Abstract: A bandgap reference includes a current source providing a current that is proportional to the sum of a first voltage having a positive-to-absolute-temperature (PTAT) temperature dependency and a second voltage having a complementary-to-absolute-temperature (CTAT) dependency. The bandgap reference further includes a variable resistor comprising a fixed resistor that may be selectively combined with one or more of a plurality of selectable resistors, wherein the first voltage is inversely proportional to the resistance of the variable resistor.
    Type: Application
    Filed: November 26, 2003
    Publication date: May 26, 2005
    Inventors: Debanjan Mukherjee, Jishnu Bhattacharjee, Abhijit Phanse
  • Publication number: 20050110570
    Abstract: A linear interpolator is provided that includes differential pairs of transistors biased such that a first input voltage may be multiplied by a factor r wherein 0?r?1 and such that a second input voltage may be multiplied by the complement factor (1-r). By combining the multiplied input voltages, a linear interpolation is provided based upon the factor r.
    Type: Application
    Filed: November 26, 2003
    Publication date: May 26, 2005
    Inventors: Jishnu Bhattacharjee, Debanjan Mukherjee, Abhijit Phanse
  • Publication number: 20050110569
    Abstract: A digitally controlled transconductance cell includes a differential transistor pair coupled to load elements (either passive or active with resistive or impedance loads) and a variable bias current source, where the transconductance or gain is digitally varied by changing the aspect ratio of the transistors and the bias current.
    Type: Application
    Filed: November 26, 2003
    Publication date: May 26, 2005
    Inventors: Jishnu Bhattacharjee, Debanjan Mukherjee, Abhijit Phanse
  • Publication number: 20050114428
    Abstract: Systems and methods provide analog delay elements, which may be utilized in isolation or in a cascade. For example, a delay element may include a broadband amplifier and a passive, programmable filter, which may provide a desired magnitude and group delay response over a wide frequency range while being tolerant of process variations.
    Type: Application
    Filed: November 26, 2003
    Publication date: May 26, 2005
    Inventors: Debanjan Mukherjee, Jishnu Bhattacharjee, Qian Yu, Abhijit Phanse
  • Publication number: 20050110566
    Abstract: Systems and methods provide automatic gain control, such as by employing analog and digital techniques. For example, overall gain may be controlled through coarse and fine control signals provided to gain stages, with the overall gain monitored via a power detector circuit.
    Type: Application
    Filed: November 26, 2003
    Publication date: May 26, 2005
    Inventors: Jishnu Bhattacharjee, Debanjan Mukherjee, Abhijit Phanse
  • Publication number: 20050104705
    Abstract: An integrated circuit including a differentially excited symmetric microstrip inductor formed over multiple layers while maintaining both electrical and geometrical symmetry.
    Type: Application
    Filed: November 19, 2003
    Publication date: May 19, 2005
    Inventors: Debanjan Mukherjee, Jishnu Bhattacharjee, Abhijit Phanse
  • Publication number: 20050104158
    Abstract: An inductor for an integrated circuit made of a plurality of stacked, electrically coupled, metal layers. Each metal layer includes an inductor formed of a spiral pattern, which except for the top and bottom inductors, are electrically coupled to the spiral inductor formed on the metal layer above and below with an electrical path or via formed between each metal layer. The top and bottom inductors are electrically coupled to the inductor directly below and above, respectively.
    Type: Application
    Filed: November 19, 2003
    Publication date: May 19, 2005
    Inventors: Jishnu Bhattacharjee, Madabusi Govindarajan, Debanjan Mukherjee, Abhijit Phanse, Prashant Choudhary
  • Publication number: 20040202258
    Abstract: An apparatus and method for adaptively introducing a compensating signal latency related to a signal latency of a data symbol decision circuit. Adaptive timing control circuitry, including an interpolating mixer implemented as a tapped delay line with correlated tap coefficients, introduces a latency adaptively and substantially matching the latency of the data decision circuit for use within an adaptive equalizer, thereby minimizing the mean-squared error of such decision circuit. This adaptive latency is used in generating the feedback error signal which, in turn, can be used by the feedforward equalizer for dynamically adjusting its adaptive filter tap coefficients.
    Type: Application
    Filed: February 27, 2004
    Publication date: October 14, 2004
    Inventors: Qian Yu, Venugopal Balasubramonian, Jishnu Bhattacharjee, Debanjan Mukherjee, Abhijit Phanse, Abhijit G. Shanbhag, Edem Ibragimov, Fabian Giroud
  • Publication number: 20040114700
    Abstract: An apparatus and method for adaptively introducing a compensating signal latency related to a signal latency of a data symbol decision circuit. Adaptive timing control circuitry, including an interpolating mixer implemented as a tapped delay line with correlated tap coefficients, introduces a latency adaptively and substantially matching the latency of the data decision circuit for use within an adaptive equalizer, thereby minimizing the mean-squared error of such decision circuit. This adaptive latency is used in generating the feedback error signal which, in turn, can be used by the feedforward equalizer for dynamically adjusting its adaptive filter tap coefficients.
    Type: Application
    Filed: December 17, 2002
    Publication date: June 17, 2004
    Inventors: Qian Yu, Venugopal Balasubramonian, Jishnu Bhattacharjee, Debanjan Mukherjee, Abhijit Phanse, Abhijit G. Shanbhag, Edem Ibragimov
  • Publication number: 20040091036
    Abstract: An adaptive signal equalizer with a feedforward filter in which the feedback error signal and corresponding incoming data signal are dynamically aligned in time using signal interpolation, and further, to control the precursor/postcursor filter taps configuration, thereby producing more adaptive filter tap coefficient signals for significantly improved and robust signal equalization.
    Type: Application
    Filed: November 8, 2002
    Publication date: May 13, 2004
    Inventors: Venugopal Balasubramonian, Jishnu Bhattacharjee, Edem Ibragimov, Debanjan Mukherjee, Abhijit Phanse, Abhijit G. Shanbhag, Qian Yu
  • Publication number: 20040091041
    Abstract: An adaptive coefficient signal generator for use in an adaptive signal equalizer with fractionally-spaced feedback. The signals representing the feedback tap coefficients are generated in conjunction with a timing interpolation parameter such that the fractionally-spaced feedback circuitry dynamically emulates symbol-spaced feedback circuitry.
    Type: Application
    Filed: December 17, 2002
    Publication date: May 13, 2004
    Inventors: Abhijit G. Shanbhag, Qian Yu, Abhijit Phanse, Jishnu Bhattacharjee, Debanjan Mukherjee, Fabian Giroud, Venugopal Balasubramonian
  • Publication number: 20040091040
    Abstract: An adaptive coefficient signal generator for use in an adaptive signal equalizer with fractionally-spaced feedback. The signals representing the feedback tap coefficients are generated in conjunction with a timing interpolation parameter such that the fractionally-spaced feedback circuitry dynamically emulates symbol-spaced feedback circuitry.
    Type: Application
    Filed: November 8, 2002
    Publication date: May 13, 2004
    Inventors: Abhijit G. Shanbhag, Qian Yu, Abhijit Phanse, Jishnu Bhattacharjee, Debanjan Mukherjee, Fabian Giroud, Venugopal Balasubramonian
  • Publication number: 20040091037
    Abstract: An adaptive signal equalizer with a feedforward filter in which the feedback error signal and corresponding incoming data signal are dynamically aligned in time using signal interpolation, and further, to control the precursor/postcursor filter taps configuration, thereby producing more adaptive filter tap coefficient signals for significantly improved and robust signal equalization.
    Type: Application
    Filed: December 17, 2002
    Publication date: May 13, 2004
    Inventors: Venugopal Balasubramonian, Jishnu Bhattacharjee, Edem Ibragimov, Debanjan Mukherjee, Abhijit Phanse, Abhijit G. Shanbhag, Qian Yu