Abstract: A semiconductor structure includes a substrate that includes a first region, a second region, and a third region; a first electrode layer disposed over the first region and the second region; a first dielectric layer disposed over the substrate; a second electrode layer disposed on the first dielectric layer over the third region and the second region; a second dielectric layer disposed over the substrate; a third electrode layer disposed on the second dielectric layer over the second region and over a portion of each of the third and first regions; and a first plug disposed over the first region and a second plug disposed over the third region. The first plug is electrically connected with one of the first, second and third electrode layers, and the second plug is electrically connected with the other two electrode layers.

Abstract: Provided are a semiconductor structure and a forming method thereof, and a photomask layout. One form of a semiconductor structure includes: a base, including a substrate and a plurality of fins arranged in parallel on the substrate, the substrate including a transistor cell area, and in the transistor cell area, in a direction perpendicular to an extending direction of the fin, the fin closest to a boundary of the transistor cell area being used as an edge fin, and the edge fin having an outer side wall facing the boundary of the transistor cell area; and a gate structure, spanning the fin and covering a part of a top and a part of a side wall of the fin, and the gate structure exposing at least a part of an outer side wall of any of the edge fins.

Abstract: A semiconductor structure and a method for forming same are provided.

Abstract: A semiconductor structure formation method and a mask are provided.

Abstract: A semiconductor structure and a forming method thereof are provided.

Abstract: A process manufacturing method, a method for adjusting a threshold voltage, a device, and a storage medium are provided.

Abstract: This disclosure relates to a packaging structure and a packaging method. The packaging structure includes: a substrate; an interconnecting structure, bonded to the substrate, the interconnecting structure is electrically connected to the substrate; a chipset, including a plurality of first chips stacked along a longitudinal direction, the first chip adjacent to the interconnecting structure is used as a bottom chip, each of the rest of the first chips is used as a top chip, the bottom chip is electrically connected to the interconnecting structure, adjacent first chips along the longitudinal direction are electrically connected, and a portion of the bottom chip is exposed from the top chip; a conductive post, arranged on the interconnecting structure on a side of the chipset and electrically connected to the interconnecting structure; and a second chip, bonded to the bottom chip exposed from the top chip and to the conductive post.

Abstract: This disclosure relates to a packaging structure and a packaging method. The structure includes: a substrate; a first chip, including a first surface and a second surface opposite to each other; a second chip, including a third surface, where the third surface includes a third bonding region bonded to the second bonding region, and a remaining region of the third surface is used as a fourth bonding region; a conductive post, arranged in the fourth bonding region; and a chipset, bonded to the first bonding region of the first chip, where the second bonding region is exposed from a projection of the chipset on the first chip. The chipset includes one or more third chips stacked along a longitudinal direction, adjacent third chips along the longitudinal direction are electrically connected, and the third chip adjacent to the first chip is electrically connected to the first chip.

Abstract: This disclosure relates to packaging method and a packaging structure. The packaging structure includes: a substrate, including a bonding surface, a chipset, bonded to the bonding surface and including a plurality of first chips stacked along a longitudinal direction, where the first chip adjacent to the substrate is used as a bottom chip, each of the rest of the first chips is used as a top chip; and a second chip, bonded to the bottom chip exposed from the top chip and to the bonding surface on a side of the chipset, where the second chip, the bottom chip, the top chip, and the substrate are electrically connected, and a projection of the second chip and a projection of the bottom chip on a projection plane parallel to the bonding surface partially overlap. The present disclosure helps improve a speed of communication between chips.

Abstract: A semiconductor structure and a forming method thereof are provided.

Abstract: The method includes providing a to-be-etched layer including an first region and a second region adjoining the first region, forming a first mask layer on the to-be-etched layer, forming a patterned core layer on the first mask layer of the first region, forming a sidewall spacer on the core layer and the first mask layer, forming a first sacrificial layer on the sidewall spacer on the surface of the first mask layer of the second region, forming a second sacrificial layer on the sidewall spacer, removing the first sacrificial layer, the sidewall spacer on the surface of the first mask layer of the second region, and the sidewall spacer on a top of the core layer, removing the core layer, etching the first mask layer of the first region to form a first trench, and etching the first mask layer of the second region to form a second trench.

Abstract: Semiconductor structures and methods for forming the same are provided. In one form, a semiconductor structure includes: a substrate; a first dielectric layer, located on the substrate; a trench, located in the first dielectric layer; a conductive layer, located on a bottom and a sidewall of the trench and configured as a resistor structure; and a second dielectric layer, configured to be filled in the trench where the conductive layer is formed. By means of embodiments and implementations of the present disclosure, an equivalent conductive sectional area of the resistor structure is increased, and a transverse area occupied by the resistor structure is reduced, thereby miniaturizing the device.

Abstract: A semiconductor structure and its fabrication method are provided. The semiconductor structure includes: a substrate including a base substrate with a first device region and a second device region; a first active region on the first device region and a second active region on the second device region; an isolation layer between the first active region and the second active region; and a first gate electrode and a second gate electrode on the substrate. The first active region includes a first functional region and a first shared region. The first gate electrode is located on the device region and on a portion of a surface of the first active region. The second gate electrode is located on the second device region and on a portion of a surface of the second active region; and the second gate electrode also extends to a surface of the first shared area.

Abstract: Semiconductor structures and methods for forming the same are provided. In one form, a semiconductor structure includes: a substrate; a bottom dielectric layer, located on the substrate; a bottom interconnect layer, located in the bottom dielectric layer; a top dielectric layer, located on the bottom dielectric layer and the bottom interconnect layer; a conductive plug, located in the top dielectric layer on a top of the bottom interconnect layer and having a bottom in direct contact with the bottom interconnect layer and a sidewall in direct contact with the top dielectric layer; a top interconnect layer, located in the top dielectric layer above the conductive plug and in contact with the conductive plug; and a top adhesion layer, located between the top interconnect layer and the top dielectric layer. By means of embodiments and implementations of the present disclosure, electrical connection performance of a semiconductor structure is optimized.

Abstract: A semiconductor structure is provided. The semiconductor structure including: a substrate, where the substrate includes a first region and a second region adjacent to the first region; a plurality of fins formed over the first region of the substrate; an isolation layer over the substrate between adjacent fins of the plurality of fins, where a top of the isolation layer is lower than a top surface of a fin of the plurality of fins, the isolation layer over the second region and the second region of the substrate together contain a power rail opening, and the substrate contains a through-hole at a bottom of the power rail opening; and a first metal layer in the power rail opening and the through-hole, where a back surface of the first metal layer is above a back surface of the substrate.

Abstract: A method for forming a semiconductor device includes providing a to-be-etched layer, forming a first mask layer on the to-be-etched layer, forming a patterned core layer on the first mask layer of a first region, forming a sidewall spacer material layer on the core layer and the first mask layer, removing the sidewall spacer material layer on a top surface of the core layer, removing the core layer and the first mask layer at a bottom of the core layer to form a first trench, removing the sidewall spacer material layer on the first mask layer of a second region, forming a first patterned layer exposing the first mask layer of the second region, and using the first patterned layer as a mask to remove the first mask layer of the second region to form a second trench.

Abstract: A semiconductor structure and a forming method thereof are provided.

Abstract: A semiconductor structure is provided. The semiconductor structure includes: a substrate; discrete channel structures on the substrate in device regions; a power rail line, located in the substrate of a power rail region; a gate structure, extending across the channel structures; source/drain doped regions, located in the channel structures on two sides of the gate structure; an interlayer dielectric layer, located at a side portion of the gate structure; a power rail contact plug, penetrating a partial thickness of the interlayer dielectric layer at a top of the power rail line, the power rail contact plug is in full contact with a top surface of the power rail line in a longitudinal direction; and a source/drain contact layer, located in the interlayer dielectric layer and in contact with the source/drain doped region, on a projection surface parallel to the substrate, the source/drain contact layer extends across the power rail line.

Abstract: Semiconductor structures and fabrication methods are provided. An exemplary fabrication method includes providing a to-be-etched layer; forming a first sacrificial film on the to-be-etched layer; and forming a plurality of discrete first sidewall spacers and sidewall trenches on the first sacrificial film. Each sidewall trench is located between two adjacent first sidewall spacers; the first sidewall trenches include a first sidewall trench and a second sidewall trench, and a width of the second sidewall trench is greater than that of the first sidewall trench. The method also includes forming a second sidewall spacer in the first sidewall trench to fill the first sidewall trench; and etching the first sacrificial film using the first sidewall spacers and the second sidewall spacer as an etching mask to form a plurality of discrete first sacrificial layers on the to-be-etched layer.

Abstract: A semiconductor structure and a forming method thereof are provided.