Patents by Inventor Jisong JIN

Jisong JIN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12376328
    Abstract: A semiconductor structure is provided. The semiconductor structure includes: a substrate; discrete channel structures on the substrate in device regions; a power rail line, located in the substrate of a power rail region; a gate structure, extending across the channel structures; source/drain doped regions, located in the channel structures on two sides of the gate structure; an interlayer dielectric layer, located at a side portion of the gate structure; a power rail contact plug, penetrating a partial thickness of the interlayer dielectric layer at a top of the power rail line, the power rail contact plug is in full contact with a top surface of the power rail line in a longitudinal direction; and a source/drain contact layer, located in the interlayer dielectric layer and in contact with the source/drain doped region, on a projection surface parallel to the substrate, the source/drain contact layer extends across the power rail line.
    Type: Grant
    Filed: March 10, 2023
    Date of Patent: July 29, 2025
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Jisong Jin, Subhash Kuchanuri, Abraham Yoo
  • Patent number: 12341022
    Abstract: Semiconductor device is provided. The semiconductor device includes a to-be-etched layer having a plurality of first regions and a plurality of second regions that are alternately arranged along a first direction, where the second region includes a second trench region; a first mask layer on the plurality of first regions and the plurality of second regions of the to-be-etched layer; a second mask layer on the first mask layer; a first trench penetrating the first mask layer and the second mask layer over a first region of the plurality of first regions; a mask sidewall spacer on sidewall surfaces of the first trench; and second trenches over the plurality of second trench regions of the plurality of second regions, where a sidewall surface of the second trench exposes a corresponding mask sidewall spacer of an adjacent first trench.
    Type: Grant
    Filed: June 24, 2022
    Date of Patent: June 24, 2025
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Jisong Jin
  • Publication number: 20250191936
    Abstract: A package structure includes a substrate; a chip bridge including a frontside and a backside that is bonded to the substrate; a redistribution layer bonded to the frontside of the chip bridge and including one or more stacked interconnection layers, an interconnection layer including an interconnect via and an interconnection metal layer on the interconnect via, and the interconnect via being in contact with the chip bridge; solder pads between the frontside of the chip bridge and the substrate and electrically connecting the chip bridge with the redistribution layer; a first chip bonded to the redistribution layer and electrically connected to the chip bridge; and a chip structure bonded to the redistribution layer on a side of the first chip along a lateral direction, the chip structure being electrically connected to the redistribution layer, and also electrically connected to the first chip through the chip bridge.
    Type: Application
    Filed: December 5, 2024
    Publication date: June 12, 2025
    Inventors: Jisong JIN, Fengping CAI, Xiaoli ZHAO
  • Publication number: 20250079391
    Abstract: Packaging structure and packaging method are provided. The packaging structure includes a substrate, including a bonding surface; an interconnection chip, bonded to the bonding surface of the substrate, the interconnection chip including a front side and a back side of a first chip opposite to each other, and the back side of the first chip facing the substrate and being electrically connected to the substrate; and a device chip, bonded to the interconnection chip, the device chip including a front side and a back side of a second chip opposite to each other, the front side of the second chip facing and being electrically connected to the interconnection chip, and the back side of the second chip being electrically connected to the interconnection chip through the front side of the second chip.
    Type: Application
    Filed: July 10, 2024
    Publication date: March 6, 2025
    Inventor: Jisong JIN
  • Publication number: 20250046776
    Abstract: This disclosure relates to a packaging structure and a packaging method. The packaging method includes: providing a bearing substrate, including a bearing face; providing a first chip, including a first face and a second face that is opposite to the first face; providing a chipset, where the chipset includes a third face and a fourth face opposite to the third face, and the chipset includes a plurality of second chips stacked in a direction perpendicular to the bearing substrate, and is electrically connected between adjacent second chips in the direction perpendicular to the bearing substrate; attaching the first chip onto the bearing substrate; attaching the chipset onto the bearing substrate; providing an interconnect chip, where the interconnect chip includes a bonding face and a back face facing away from the bonding face; bonding the interconnect chip on the first chip and the chipset.
    Type: Application
    Filed: July 31, 2024
    Publication date: February 6, 2025
    Applicant: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventor: Jisong JIN
  • Publication number: 20250040159
    Abstract: This disclosure relates to a metal-insulator-metal capacitor structure and a method for forming the same. The metal-insulator-metal capacitor structure includes: a first capacitor dielectric layer, located on a first electrode layer; a second electrode layer, located on the first capacitor dielectric layer in a first capacitor region; and one or more capacitor stacks, located on the second electrode layer in the first capacitor region. Each of the capacitor stacks includes a second capacitor dielectric layer and a third electrode layer located on the second capacitor dielectric layer. Projection overlay regions exist between the third electrode layer and the second electrode layer and between the adjacent third electrode layers. The one or more second capacitor dielectric layers are further located on the first capacitor dielectric layer in the second capacitor region disclosure.
    Type: Application
    Filed: July 25, 2024
    Publication date: January 30, 2025
    Applicant: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventor: Jisong JIN
  • Publication number: 20250015081
    Abstract: Semiconductor structures and fabrication methods are provided. The semiconductor structure includes a substrate including a first region; a first polarization layer on the first region; and a first gate structure on the first polarization layer. A material of the first polarization layer includes a semiconductor compound material containing first polarization atoms.
    Type: Application
    Filed: September 23, 2024
    Publication date: January 9, 2025
    Inventors: Jisong JIN, Abraham YOO
  • Publication number: 20240313042
    Abstract: A semiconductor structure includes: a base, a first and a second electrode layer, where the first electrode layer is located on the base and includes a first comb handle part and a plurality of first comb tooth parts connected to the first comb handle part and arranged in parallel, one end of the first comb handle part is configured to access an input signal, and the other end is configured to access an output signal; and the second electrode layer is located on the base and located on the same layer with the first electrode layer, and includes a second comb handle part and a plurality of second comb tooth parts connected to the second comb handle part and arranged in parallel, the second comb tooth parts and the first comb tooth parts are parallel in a crossed manner, and the second comb handle part is configured to be grounded.
    Type: Application
    Filed: May 31, 2023
    Publication date: September 19, 2024
    Applicant: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventors: Yichao WU, Jisong JIN
  • Patent number: 12096696
    Abstract: A semiconductor structure and a fabrication method of the semiconductor structure are provided in the present disclosure. The semiconductor structure includes a base substrate, a bottom electrode layer on the substrate, a magnetic tunnel junction layer on the bottom electrode layer, and a top electrode layer on the magnetic tunnel junction layer. An opening is formed at least exposing a portion of one of an upper surface and a lower surface of the magnetic tunnel junction layer.
    Type: Grant
    Filed: March 17, 2021
    Date of Patent: September 17, 2024
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Jisong Jin
  • Patent number: 12087582
    Abstract: Semiconductor structures and fabrication methods are provided. The method includes providing a to-be-etched layer having first regions, second regions and third regions; forming a first core layer on a first region; forming a first sidewall spacer on sidewalls of the first core layer; forming a sacrificial layer covering a portion of the first sidewall spacer on the to-be-etched layer, having a plurality of initial first openings and with a portion of the initial first opening exposing a portion of the first sidewall spacer on the second region; removing the portion of the first sidewall spacer exposed by the portion of the initial first opening to form a first opening; forming a second sidewall spacer in the first opening; and forming second openings in the sacrificial layer. The second openings expose one of or both a portion of the first sidewall spacer and a portion of the second sidewall spacer.
    Type: Grant
    Filed: June 10, 2021
    Date of Patent: September 10, 2024
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Jisong Jin
  • Patent number: 12080596
    Abstract: A semiconductor structure and a forming method thereof are provided, and the forming method includes: providing a base; forming, on the base, a plurality of conductive function layers extending in a first direction and sequentially arranged in a second direction, a bottom dielectric layer located on the base between the conductive function layers, and a blocking structure located in the conductive function layer, the blocking structure segmenting the conductive function layers located on two sides of the blocking structure in the first direction; forming a top dielectric layer covering the bottom dielectric layer, the conductive function layers, and the blocking structure; etching the top dielectric layer located above a junction of the blocking structure and the conductive function layer and a part of the blocking structure located at a side wall of the conductive function layer, to form a via running through the top dielectric layer and exposing a part of a top and a part of a side wall of the conductive fu
    Type: Grant
    Filed: April 6, 2021
    Date of Patent: September 3, 2024
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventors: Jisong Jin, Abraham Yoo
  • Publication number: 20240276889
    Abstract: Provided are a magnetic random access memory cell and a magnetic random access memory. In one form, a memory cell includes: a spin-orbit torque (SOT) layer, through which a write current flows when performing a write operation on the magnetic random access memory cell; a magnetic tunnel junction, located on the SOT layer; a first bottom plug, located on a bottom of the SOT layer and contacting one end of the SOT layer, and a second bottom plug, located on the bottom of the SOT layer and spaced apart from the first bottom plug, the second bottom plug contacting the other end of the SOT layer, and an arrangement direction of the second bottom plug and the first bottom plug forming an acute included angle with a magnetic moment direction of the magnetic tunnel junction.
    Type: Application
    Filed: July 7, 2023
    Publication date: August 15, 2024
    Applicant: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventor: Jisong JIN
  • Publication number: 20240274466
    Abstract: In one form, a method includes: providing a base, where a bottom film layer structure is formed on the base and includes a plurality of discrete first regions and a plurality of second regions located among the first regions; forming top conductive layers on the bottom film layer structure of the first regions, where openings are enclosed between the adjacent top conductive layers and the bottom film layer structure; forming grooves in the bottom film layer structure at bottoms of the openings, where bottoms of the grooves are lower than bottoms of the top conductive layers; and forming a first dielectric layer on the top conductive layers, where the first dielectric layer is further located in the grooves, seals tops of the openings and encloses air gaps together with the openings, and bottoms of the air gaps are lower than the bottoms of the top conductive layers.
    Type: Application
    Filed: May 31, 2023
    Publication date: August 15, 2024
    Applicant: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventors: Yichao WU, Jisong JIN
  • Publication number: 20240274175
    Abstract: Provided are a magnetic random access memory cell and a magnetic random access memory. One form of a memory cell includes: a spin-orbit torque (SOT) layer, through which a write current flows when performing a write operation on the magnetic random access memory cell, a direction of the write current being a first direction, and a direction parallel to the SOT layer and perpendicular to the first direction being a second direction; and a magnetic tunnel junction, located on the SOT layer, the magnetic tunnel junction including substructures symmetrical with respect to the second direction, and a magnetic moment direction of the substructure forming an acute included angle with the first direction.
    Type: Application
    Filed: July 7, 2023
    Publication date: August 15, 2024
    Applicant: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventor: Jisong JIN
  • Publication number: 20240266289
    Abstract: Semiconductor structure and forming method thereof are provided. The method includes providing a substrate. The substrate includes a first side and a second side, and the substrate includes a first region and a second region. The method also includes forming a device layer over the first side of the first region, where the device layer includes a device structure; forming a first electrical connection structure over the device layer; forming a second electrical connection structure over the first side of the second region; and forming a first connecting structure in in the first region. The method also includes forming a third electrical connection structure over the second side of the first region; and forming a second connecting structure in the second region. The second connecting structure is electrically connected to the third electrical connection structure, and the second connecting structure is electrically connected to the second electrical connection structure.
    Type: Application
    Filed: February 2, 2024
    Publication date: August 8, 2024
    Inventor: Jisong JIN
  • Publication number: 20240250087
    Abstract: A semiconductor structure includes a substrate including a first region. The first region includes a plurality of first active regions arranged along a first direction and a first isolation region between the adjacent first active regions. The semiconductor structure also includes a plurality of first fins on the substrate, parallel to the first direction and arranged along a second direction. The second direction is perpendicular to the first direction. The first fins span the adjacent first active regions and the first isolation region between the first active regions. The semiconductor structure also includes a plurality of first gate structures in the first isolation region. The first gate structures span the first fins along the second direction. The semiconductor structure also includes a plurality of first electrical interconnection structures, electrically connected to the first gate structures.
    Type: Application
    Filed: May 19, 2021
    Publication date: July 25, 2024
    Inventor: Jisong JIN
  • Publication number: 20240186233
    Abstract: A packaging structure and a packaging method are provided. The packaging method includes: providing a carrier; forming a first redistribution structure on the carrier, the first redistribution structure including a first area and a second area; forming a conductive pillar on the first redistribution structure in the first area, the conductive pillar being electrically connected to the first redistribution structure; providing a device chip, including a first side and a second side opposite to the first side; bonding the second side of the device chip to the first redistribution structure in the second area, the device chip being electrically connected to the first redistribution structure; providing a substrate including a bonding surface; and bonding the first side of the device chip and the conductive pillar to the bonding surface, the device chip being electrically connected to the substrate, and the conductive pillar being electrically connected to the substrate.
    Type: Application
    Filed: November 21, 2023
    Publication date: June 6, 2024
    Applicant: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventor: Jisong JIN
  • Publication number: 20240186253
    Abstract: A packaging structure and a packaging method are provided The packaging method includes: bonding a first interconnect chip to a carrier plate in a first area; bonding a first side of a device chip to the carrier plate in a second area, a first chip area of the device chip being adjacent to the first interconnect chip; bonding a second interconnect chip to the first interconnect chip and the first chip area, the second interconnect chip being electrically connected to the first interconnect chip and the device chip, and the second interconnect chip exposing a second chip area; removing the carrier plate; and bonding the first side of the device chip and a side of the first interconnect chip to a bonding surface of a substrate, the first side of the device chip and the first interconnect chip being electrically connected to the substrate.
    Type: Application
    Filed: November 21, 2023
    Publication date: June 6, 2024
    Applicant: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventor: Jisong JIN
  • Publication number: 20240178203
    Abstract: A packaging structure and a packaging method are provided. The packaging method includes: providing a carrier; providing a plurality of device chips, a device chip including a first side and a second side facing away from each other, and an interconnection structure being formed on the first side; attaching the plurality of device chips to the carrier, the second side of the device chip facing the carrier, forming a first packaging layer covering a side wall of the device chip and filling between the device chips on the carrier, the first packaging layer exposing the first side of the device chip; forming a first redistribution structure on the first packaging layer and the device chip; bonding an interconnect chip to the first redistribution structure; and forming a second packaging layer covering the interconnect chip on the first redistribution structure.
    Type: Application
    Filed: September 28, 2023
    Publication date: May 30, 2024
    Applicant: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventor: Jisong JIN
  • Publication number: 20240178186
    Abstract: A packaging structure and a packaging method are provided. The packaging method includes: providing a carrier; providing a plurality of device chips, a device chip including a first side and a second side, and a first interconnection structure being formed on the first side; attaching the plurality of device chips to the carrier; forming a first packaging layer covering a side wall of the device chip and filling between device chips on the carrier; providing an interconnect chip, a second interconnection structure being formed on the interconnect chip, and the second interconnection structure exposing a surface of the interconnect chip; bonding the interconnect chip to the device chip and the first packaging layer, the second interconnection structure of the interconnect chip facing and contacting the first interconnection structure of the device chip; and forming a second packaging layer covering the interconnect chip on the first packaging layer.
    Type: Application
    Filed: September 28, 2023
    Publication date: May 30, 2024
    Applicant: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventor: Jisong JIN