Patents by Inventor Jiutao Li

Jiutao Li has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6974965
    Abstract: A method for fabricating chalcogenide materials on substrates, which reduces and/or eliminates agglomeration of materials on the chalcogenide materials; and system and devices for performing the method, semiconductor devices so produced, and machine readable media containing the method. One method disclosed includes forming a first layer, forming a second layer on the first layer, forming a third layer on the second layer, wherein the third layer is essentially transparent to irradiation, and irradiating the second layer through the third layer to cause the second layer to diffuse into the first layer thereby creating an integral layer of materials from the first and second layers.
    Type: Grant
    Filed: January 16, 2004
    Date of Patent: December 13, 2005
    Assignee: Micron Technology, Inc.
    Inventor: Jiutao Li
  • Patent number: 6955940
    Abstract: A method of forming a non-volatile resistance variable device includes forming a first conductive electrode material on a substrate. A metal doped chalcogenide comprising material is formed over the first conductive electrode material. Such comprises the metal and AxBy, where “B” is selected from S, Se and Te and mixtures thereof, and where “A” comprises at least one element which is selected from Group 13, Group 14, Group 15, or Group 17 of the periodic table. In one aspect, the chalcogenide comprising material is exposed to and HNO3 solution. In one aspect the outer surface is oxidized effective to form a layer comprising at least one of an oxide of “A” or an oxide of “B”. In one aspect, a passivating material is formed over the metal doped chalcogenide comprising material. A second conductive electrode material is deposited, and a second conductive electrode material of the device is ultimately formed therefrom.
    Type: Grant
    Filed: August 29, 2001
    Date of Patent: October 18, 2005
    Assignee: Micron Technology, Inc.
    Inventors: Kristy A. Campbell, Terry L. Gilton, John T. Moore, Jiutao Li
  • Patent number: 6949453
    Abstract: A method for fabricating chalcogenide materials on substrates, which reduces and/or eliminates agglomeration of materials on the chalcogenide materials; and system and devices for performing the method, semiconductor devices so produced, and machine readable media containing the method. One method disclosed includes forming a first layer, forming a second layer on the first layer, forming a third layer on the second layer, wherein the third layer is essentially transparent to irradiation, and irradiating the second layer through the third layer to cause the second layer to diffuse into the first layer thereby creating an integral layer of materials from the first and second layers.
    Type: Grant
    Filed: October 28, 2002
    Date of Patent: September 27, 2005
    Assignee: Micron Technology, Inc.
    Inventor: Jiutao Li
  • Publication number: 20050157573
    Abstract: A method of forming a non-volatile resistance variable device includes forming a first conductive electrode material on a substrate. A metal doped chalcogenide comprising material is formed over the first conductive electrode material. Such comprises the metal and AxBy, where “B” is selected from S, Se and Te and mixtures thereof, and where “A” comprises at least one element which is selected from Group 13, Group 14, Group 15, or Group 17 of the periodic table. In one aspect, the chalcogenide comprising material is exposed to and HNO3 solution. In one aspect the outer surface is oxidized effective to form a layer comprising at least one of an oxide of “A” or an oxide of “B”. In one aspect, a passivating material is formed over the metal doped chalcogenide comprising material. A second conductive electrode material is deposited, and a second conductive electrode material of the device is ultimately formed therefrom.
    Type: Application
    Filed: March 21, 2005
    Publication date: July 21, 2005
    Inventors: Kristy Campbell, Terry Gilton, John Moore, Jiutao Li
  • Publication number: 20050133688
    Abstract: A microlens structure includes lower lens layers on a substrate. A sputtered layer of glass, such as silicon oxide, is applied over the lower lens layers at an angle away from normal to form upper lens layers that increase the effective focal length of the microlens structure. The upper lens layers can be deposited in an aspherical shape with radii of curvature longer than the lower lens layers. As a result, small microlenses can be provided with longer focal lengths. The microlenses are arranged in arrays for use in imaging devices.
    Type: Application
    Filed: December 22, 2003
    Publication date: June 23, 2005
    Inventors: Jin Li, Jiutao Li, Ulrich Boettiger, Loriston Ford
  • Publication number: 20050103621
    Abstract: Method and apparatus for sputter depositing silver selenide and controlling defect formation in and on a sputter deposited silver selenide film are provided. A method of forming deposited silver selenide comprising both alpha and beta phases is further provided. The methods include depositing silver selenide using sputter powers of less than about 200 W, using sputter power densities of less than about 1 W/cm2, using sputter pressures of less than about 40 mTorr and preferably less than about 10 mTorr, using sputter gasses with molecular weight greater than that of neon, using cooling apparatus having a coolant flow rate at least greater than 2.5 gallons per minute and a coolant temperature less than about 25° C., using a magnetron sputtering system having a magnetron placed a sufficient distance from a silver selenide sputter target so as to maintain a sputter target temperature of less than about 350° C. and preferably below about 250° C.
    Type: Application
    Filed: November 14, 2003
    Publication date: May 19, 2005
    Inventors: Jiutao Li, Allen McTeer
  • Publication number: 20050098428
    Abstract: A method of sputter depositing silver selenide and controlling the stoichiometry and nodular defect formations of a sputter deposited silver-selenide film. The method includes depositing silver-selenide using a sputter deposition process at a pressure of about 0.3 mTorr to about 10 mTorr. In accordance with one aspect of the invention, an RF sputter deposition process may be used preferably at pressures of about 2 mTorr to about 3 mTorr. In accordance with another aspect of the invention, a pulse DC sputter deposition process may be used preferably at pressures of about 4 mTorr to about 5 mTorr.
    Type: Application
    Filed: December 16, 2004
    Publication date: May 12, 2005
    Inventors: Jiutao Li, Keith Hampton, Allen McTeer
  • Patent number: 6890790
    Abstract: The present invention is related to methods and apparatus that allow a chalcogenide glass such as germanium selenide (GexSe1-x) to be doped with a metal such as silver, copper, or zinc without utilizing an ultraviolet (UV) photodoping step to dope the chalcogenide glass with the metal. The chalcogenide glass doped with the metal can be used to store data in a memory device. Advantageously, the systems and methods co-sputter the metal and the chalcogenide glass and allow for relatively precise and efficient control of a constituent ratio between the doping metal and the chalcogenide glass. Further advantageously, the systems and methods enable the doping of the chalcogenide glass with a relatively high degree of uniformity over the depth of the formed layer of chalcogenide glass and the metal. Also, the systems and methods allow a metal concentration to be varied in a controlled manner along the thin film depth.
    Type: Grant
    Filed: June 6, 2002
    Date of Patent: May 10, 2005
    Assignee: Micron Technology, Inc.
    Inventors: Jiutao Li, Allen McTeer, Gregory Herdt, Trung T. Doan
  • Patent number: 6878569
    Abstract: A method for fabricating chalcogenide materials on substrates, which reduces and/or eliminates agglomeration of materials on the chalcogenide materials; and system and devices for performing the method, semiconductor devices so produced, and machine readable media containing the method. One method disclosed includes forming a first layer, forming a second layer on the first layer, forming a third layer on the second layer, wherein the third layer is essentially transparent to irradiation, and irradiating the second layer through the third layer to cause the second layer to diffuse into the first layer thereby creating an integral layer of materials from the first and second layers.
    Type: Grant
    Filed: October 28, 2002
    Date of Patent: April 12, 2005
    Assignee: Micron Technology, Inc.
    Inventor: Jiutao Li
  • Patent number: 6858465
    Abstract: A method of forming a programmable conductor memory cell array is disclosed wherein metal and chalcogenide glass are co-sputtered to fill an array of cell vias in a prepared substrate. The prepared substrate is heated above room temperature before the metal and chalcogenide glass film is deposited, and the heating is maintained throughout the deposition. The resulting metal/chalcogenide glass film has good homogeneity, a desired ratio of components, and has a regular surface.
    Type: Grant
    Filed: August 29, 2003
    Date of Patent: February 22, 2005
    Assignee: Micron Technology, Inc.
    Inventors: Jiutao Li, Allen McTeer
  • Publication number: 20050026433
    Abstract: Methods of forming metal-doped chalcogenide layers and devices containing such doped chalcogenide layers include using a plasma to induce diffusion of metal into a chalcogenide layer concurrently with metal deposition. The plasma contains at least one noble gas of low atomic weight, such as neon or helium. The plasma has a sputter yield sufficient to sputter a metal target and a UV component of its emitted spectrum sufficient to induce diffusion of the sputtered metal into the chalcogenide layer. Using such methods, a conductive layer can be formed on the doped chalcogenide layer in situ. In integrated circuit devices, such as non-volatile chalcogenide memory devices, doping of the chalcogenide layer concurrently with metal deposition and formation of a conductive layer in situ with the doping of the chalcogenide layer reduces contamination concerns and physical damage resulting from moving the device substrate from tool to tool, thus facilitating improved device reliability.
    Type: Application
    Filed: June 22, 2004
    Publication date: February 3, 2005
    Inventors: Jiutao Li, Allen McTeer
  • Patent number: 6825135
    Abstract: A method of forming a programmable conductor memory cell array is disclosed wherein metal and chalcogenide glass are co-sputtered to fill an array of cell vias in a prepared substrate. The prepared substrate is heated above room temperature before the metal and chalcogenide glass film is deposited, and the heating is maintained throughout the deposition. The resulting metal/chalcogenide glass film has good homogeneity, a desired ratio of components, and has a regular surface.
    Type: Grant
    Filed: June 6, 2002
    Date of Patent: November 30, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Jiutao Li, Allen McTeer
  • Publication number: 20040235235
    Abstract: The present invention is related to methods and apparatus that allow a chalcogenide glass such as germanium selenide (GexSe1-x) to be doped with a metal such as silver, copper, or zinc without utilizing an ultraviolet (UV) photodoping step to dope the chalcogenide glass with the metal. The chalcogenide glass doped with the metal can be used to store data in a memory device. Advantageously, the systems and methods co-sputter the metal and the chalcogenide glass and allow for relatively precise and efficient control of a constituent ratio between the doping metal and the chalcogenide glass. Further advantageously, the systems and methods enable the doping of the chalcogenide glass with a relatively high degree of uniformity over the depth of the formed layer of chalcogenide glass and the metal. Also, the systems and methods allow a metal concentration to be varied in a controlled manner along the thin film depth.
    Type: Application
    Filed: June 29, 2004
    Publication date: November 25, 2004
    Inventors: Jiutao Li, Allen McTeer, Gregory Herdt, Trung T. Doan
  • Patent number: 6800504
    Abstract: Methods of forming metal-doped chalcogenide layers and devices containing such doped chalcogenide layers include using a plasma to induce diffusion of metal into a chalcogenide layer concurrently with metal deposition. The plasma contains at least one noble gas of low atomic weight, such as neon or helium. The plasma has a sputter yield sufficient to sputter a metal target and a UV component of its emitted spectrum sufficient to induce diffusion of the sputtered metal into the chalcogenide layer. Using such methods, a conductive layer can be formed on the doped chalcogenide layer in situ. In integrated circuit devices, such as non-volatile chalcogenide memory devices, doping of the chalcogenide layer concurrently with metal deposition and formation of a conductive layer in situ with the doping of the chalcogenide layer reduces contamination concerns and physical damage resulting from moving the device substrate from tool to tool, thus facilitating improved device reliability.
    Type: Grant
    Filed: November 1, 2002
    Date of Patent: October 5, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Jiutao Li, Allen McTeer
  • Publication number: 20040192006
    Abstract: The invention is related to methods and apparatus for providing a resistance variable memory element with improved data retention and switching characteristics. According to one embodiment of the invention, a resistance variable memory element is provided having at least one silver-selenide layer in between two glass layers, wherein at least one of the glass layers is a chalcogenide glass, preferably having a GexSe100−x composition. According to another embodiment of the invention, a resistance variable memory element is provided having at least one silver-selenide layer in between chalcogenide glass layers and further having a silver layer above at least one of said chalcogenide glass layers and a conductive adhesion layer above said silver layer.
    Type: Application
    Filed: April 7, 2004
    Publication date: September 30, 2004
    Inventors: Kristy A. Campbell, Jiutao Li, Allen McTeer, John T. Moore
  • Publication number: 20040180530
    Abstract: A method of filling vias for a PCRAM cell with a metal is described. A PCRAM intermediate structure including a substrate, a first conductor, and an insulator through which a via extends has a metallic material formed within the via and on a surface of the insulator. The metallic material may be deposited on the surface and within the via. A hard mask of a flowable oxide is deposited over the metallic material in the via to protect the metallic material in the via, A subsequent dry sputter etch removes the metallic meterial from the surface of the insulator and a portion of the hard mask. After complete removal of the hard mask, a glass material is recessed over the metallic material in the via. Then, a layer of a metal-containing material is formed over the glass material. Finally, a second conductor is formed on the surface of the insulator.
    Type: Application
    Filed: January 16, 2004
    Publication date: September 16, 2004
    Inventors: Li Li, Jiutao Li
  • Publication number: 20040180533
    Abstract: A method of filling vias for a PCRAM cell with a metal is described. A PCRAM intermediate structure including a substrate, a first conductor, and an insulator through which a via extends has a metallic material formed within the via and on a surface of the insulator. The metallic material may be deposited on the surface and within the via. A hard mask of a flowable oxide is deposited over the metallic material in the via to protect the metallic material in the via. A subsequent dry sputter etch removes the metallic material from the surface of the insulator and a portion of the hard mask. After complete removal of the hard mask, a glass material is recessed over the metallic material in the via. Then, a layer of a metal-containing material is formed over the glass material. Finally, a second conductor is formed on the surface of the insulator.
    Type: Application
    Filed: March 14, 2003
    Publication date: September 16, 2004
    Inventors: Li Li, Jiutao Li
  • Publication number: 20040144968
    Abstract: A method for fabricating chalcogenide materials on substrates, which reduces and/or eliminates agglomeration of materials on the chalcogenide materials; and system and devices for performing the method, semiconductor devices so produced, and machine readable media containing the method. One method disclosed includes forming a first layer, forming a second layer on the first layer, forming a third layer on the second layer, wherein the third layer is essentially transparent to irradiation, and irradiating the second layer through the third layer to cause the second layer to diffuse into the first layer thereby creating an integral layer of materials from the first and second layers.
    Type: Application
    Filed: January 16, 2004
    Publication date: July 29, 2004
    Inventor: Jiutao Li
  • Publication number: 20040144973
    Abstract: A method for fabricating chalcogenide materials on substrates, which reduces and/or eliminates agglomeration of materials on the chalcogenide materials; and system and devices for performing the method, semiconductor devices so produced, and machine readable media containing the method. One method disclosed includes forming a first layer, forming a second layer on the first layer, forming a third layer on the second layer, wherein the third layer is essentially transparent to irradiation, and irradiating the second layer through the third layer to cause the second layer to diffuse into the first layer thereby creating an integral layer of materials from the first and second layers.
    Type: Application
    Filed: January 16, 2004
    Publication date: July 29, 2004
    Inventor: Jiutao Li
  • Patent number: 6734455
    Abstract: A method for fabricating chalcogenide materials on substrates, which reduces and/or eliminates agglomeration of materials on the chalcogenide materials; and system and devices for performing the method, semiconductor devices so produced, and machine readable media containing the method. One method disclosed includes forming a first layer, forming a second layer on the first layer, forming a third layer on the second layer, wherein the third layer is essentially transparent to irradiation, and irradiating the second layer through the third layer to cause the second layer to diffuse into the first layer thereby creating an integral layer of materials from the first and second layers.
    Type: Grant
    Filed: March 15, 2001
    Date of Patent: May 11, 2004
    Assignee: Micron Technology, Inc.
    Inventor: Jiutao Li