Patents by Inventor Joab D. Henderson
Joab D. Henderson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10096353Abstract: A refresh command is communicated to a memory device to initiate an interruptible refresh which contains multiple segment refreshes separated by interrupt boundaries. A command is communicated to the memory device before execution of a segment refresh and the segment refresh is delayed at an interrupt boundary. Alternatively, a first number of commands in a queue is determined. A first number of segment refreshes to execute is determined based on the first number of commands. The first number of segment refreshes to execute is communicated to the memory device to cause execution of the first number of segment refreshes. A second number of commands in the queue is determined. A second number of segment refreshes to execute is determined based on the second number of commands. The second number of segment refreshes to execute is communicated to the memory device to cause execution of the second number of segment refreshes.Type: GrantFiled: November 7, 2013Date of Patent: October 9, 2018Assignee: International Business Machines CorporationInventors: Edgar R. Cordero, Carlos A. Fernandez, Joab D. Henderson, William P. Hovis, Jeffrey A. Sabrowski, Anuwat Saetow, Saravanan Sethuraman
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Patent number: 10067886Abstract: This disclosure includes a method for securing a memory of an electronic system that includes initializing the memory, creating a security key, transmitting the security key to memory, storing the security key in the memory, transmitting the current security key and a a new security key to the memory by the memory controller. If the current security key transmitted is the same as the security key stored in memory, then access to the memory is enabled and the current security key in the memory is replaced with the new security key. If the current security key transmitted is not the same as the security key stored in the memory, then access to the memory is disabled.Type: GrantFiled: November 8, 2017Date of Patent: September 4, 2018Assignee: International Business Machines CorporationInventors: Brian J. Connolly, Joab D. Henderson, Jeffrey A. Sabrowski, Saravanan Sethuraman, Kenneth L. Wright
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Patent number: 9972376Abstract: A refresh command is received from a memory controller. An interruptible refresh containing multiple segment refreshes is initiated. The segment refreshes are separated by interrupt boundaries. A command is received before execution of a segment refresh. The first command is executed and execution of the first segment refresh is delayed at a first interrupt boundary. Alternatively, a first number of segment refreshes to execute is received from a memory controller. The received first number of segment refreshes is executed. A second number of segment refreshes to execute is received from a memory controller. The received second number of segment refreshes is executed. No segment refreshes are executed between the execution of the first number of segment refreshes and the execution of the second number of segment refreshes.Type: GrantFiled: November 7, 2013Date of Patent: May 15, 2018Assignee: International Business Machines CorporationInventors: Edgar R. Cordero, Carlos A. Fernandez, Joab D. Henderson, William P. Hovis, Jeffrey A. Sabrowski, Anuwat Saetow, Saravanan Sethuraman
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Publication number: 20180067874Abstract: This disclosure includes a method for securing a memory of an electronic system that includes initializing the memory, creating a security key, transmitting the security key to memory, storing the security key in the memory, transmitting the current security key and a a new security key to the memory by the memory controller. If the current security key transmitted is the same as the security key stored in memory, then access to the memory is enabled and the current security key in the memory is replaced with the new security key. If the current security key transmitted is not the same as the security key stored in the memory, then access to the memory is disabled.Type: ApplicationFiled: November 8, 2017Publication date: March 8, 2018Inventors: Brian J. Connolly, Joab D. Henderson, Jeffrey A. Sabrowski, Saravanan Sethuraman, Kenneth L. Wright
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Patent number: 9858208Abstract: This disclosure includes a method for securing a memory of an electronic system that includes initializing the memory, creating a security key, transmitting the security key to memory, storing the security key in the memory, transmitting the current security key and a new security key to the memory by the memory controller. If the current security key transmitted is the same as the security key stored in memory, then access to the memory is enabled and the current security key in the memory is replaced with the new security key. If the current security key transmitted is not the same as the security key stored in the memory, then access to the memory is disabled.Type: GrantFiled: March 21, 2013Date of Patent: January 2, 2018Assignee: International Business Machines CorporationInventors: Brian J. Connolly, Joab D. Henderson, Jeffrey A. Sabrowski, Saravanan Sethuraman, Kenneth L. Wright
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Patent number: 9576682Abstract: The method may include accessing, with a first stress test, a plurality of memory modules, the plurality of memory modules coupled in a computer system, the plurality of memory modules including a first module having a first memory characteristic and a second module having a second memory characteristic. The method may include determining for the first module, a first traffic-to-temperature parameter, and determining that the first module was sufficiently stressed in response to determining that the first traffic-to-temperature parameter is within a first traffic-to-temperature range. The method may also include determining, for the second module, a second traffic-to-temperature parameter, and determining that the second module was sufficiently stressed in response to determining that the second traffic-to-temperature parameter is within a second traffic-to-temperature range.Type: GrantFiled: March 20, 2014Date of Patent: February 21, 2017Assignee: International Business Machines CorporationInventors: Diyanesh B. Chinnakkonda Vidyapoornachary, Timothy J. Dell, Joab D. Henderson, Anil B. Lingambudi, Michael D. Pardeik
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Patent number: 9570199Abstract: The method may include accessing, with a first stress test, a plurality of memory modules, the plurality of memory modules coupled in a computer system, the plurality of memory modules including a first module having a first memory characteristic and a second module having a second memory characteristic. The method may include determining for the first module, a first traffic-to-temperature parameter, and determining that the first module was sufficiently stressed in response to determining that the first traffic-to-temperature parameter is within a first traffic-to-temperature range. The method may also include determining, for the second module, a second traffic-to-temperature parameter, and determining that the second module was sufficiently stressed in response to determining that the second traffic-to-temperature parameter is within a second traffic-to-temperature range.Type: GrantFiled: December 29, 2014Date of Patent: February 14, 2017Assignee: International Business Machines CorporationInventors: Diyanesh B. Chinnakkonda Vidyapoornachary, Timothy J. Dell, Joab D. Henderson, Anil B. Lingambudi, Michael D. Pardeik
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Patent number: 9535784Abstract: Exemplary embodiments of the present invention disclose a method and system for monitoring a first Error Correcting Code (ECC) device for failure and replacing the first ECC device with a second ECC device if the first ECC device begins to fail or fails. In a step, an exemplary embodiment performs a loopback test on an ECC device if a specified number of correctable errors is exceeded or if an uncorrectable error occurs. In another step, an exemplary embodiment replaces an ECC device that fails the loopback test with an ECC device that passes a loopback test.Type: GrantFiled: February 17, 2015Date of Patent: January 3, 2017Assignee: International Business Machines CorporationInventors: Edgar R. Cordero, Timothy J. Dell, Joab D. Henderson, Jeffrey A. Sabrowski, Anuwat Saetow, Saravanan Sethuraman
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Patent number: 9442816Abstract: A method, system and computer program product implement memory performance management and enhanced memory reliability of a computer system accounting for system thermal conditions. When a primary memory temperature reaches an initial temperature threshold, reads are suspended to the primary memory and reads are provided to a mirrored memory in a mirrored memory pair, and writes are provided to both the primary memory and the mirrored memory. If the primary memory temperature reaches a second temperature threshold, write operations to the primary memory are also stopped and the primary memory is turned off with DRAM power saving modes such as self timed refresh (STR), and the reads and writes are limited to the mirrored memory in the mirrored memory pair. When the primary memory temperature decreases to below the initial temperature threshold, coherency is recovered by writing a coherent copy from the mirrored memory to the primary memory.Type: GrantFiled: November 30, 2011Date of Patent: September 13, 2016Assignee: International Business Machines CorporationInventors: Edgar R. Cordero, Timothy J. Dell, Joab D. Henderson, Anil B. Lingambudi, Girisankar Paulraj, Diyanesh B. Vidyapoornachary
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Patent number: 9418722Abstract: A method and apparatus for refreshing a row of a memory device prior to a scheduled refresh. A memory array may include a plurality of memory cells. The memory array may be configured to be refreshed at a first refresh time interval. The memory device may also include an intermediate refresh circuit. The intermediate refresh circuit may be configured to detect a triggering event and request a refresh for a row of the memory array in response to detecting a triggering event.Type: GrantFiled: October 8, 2015Date of Patent: August 16, 2016Assignee: International Business Machines CorporationInventors: Edgar R. Cordero, Joab D. Henderson, Kyu-hyoun Kim, Jeffrey A. Sabrowski, Anuwat Saetow
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Patent number: 9349432Abstract: A method and apparatus for modifying a reference voltage between refreshes in a memory device are disclosed. The memory array may include a plurality of memory cells. The memory device may also include a sense amplifier. The sense amplifier may be configured to read data from the plurality of memory cells using a reference voltage. The memory device may also include a sense amplifier reference voltage modification circuit. The sense amplifier reference voltage modification circuit may be configured to detect a triggering event and modify the reference voltage in response to detecting a triggering event.Type: GrantFiled: April 23, 2015Date of Patent: May 24, 2016Assignee: International Business Machines CorporationInventors: Edgar R. Cordero, Joab D. Henderson, Kyu-hyoun Kim, Jeffrey A. Sabrowski, Anuwat Saetow
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Patent number: 9348744Abstract: A method, system and computer program product are provided for implementing enhanced reliability of memory subsystems utilizing a dual port Dynamic Random Access Memory (DRAM) configuration. The DRAM configuration includes a first buffer and a second buffer, each buffer including a validity counter. The validity counter for a receiving buffer is incremented as each respective data row from a transferring buffer is validated through Error Correction Code (ECC), Reliability, Availability, and Serviceability (RAS) logic and transferred to the receiving buffer, while the validity counter for the transferring buffer is decremented. Data are read from or written to either the first buffer or the second buffer based upon a respective count value of the validity counters.Type: GrantFiled: June 23, 2014Date of Patent: May 24, 2016Assignee: International Business Machines CorporationInventors: Edgar R. Cordero, Carlos A. Fernandez, Joab D. Henderson, Jeffrey A. Sabrowski, Anuwat Saetow, Saravanan Sethuraman
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Patent number: 9329648Abstract: An approach is provided in which a subsystem cooling manager detects an increased workload indicator corresponding to a computer subsystem's forthcoming workload requirement. The forthcoming workload requirement corresponds to future computing resources required by the subsystem to support one or more software programs executing on the computer system. The subsystem cooling manager determines that the forthcoming workload requirement exceeds a utilization threshold and in turn, directs one or more cooling systems towards the corresponding subsystem according.Type: GrantFiled: July 17, 2012Date of Patent: May 3, 2016Assignee: International Business Machines CorporationInventors: Diyanesh Babu Vidyapoornachary Chinnakkonda, Edgar Rolando Cordero, Timothy J. Dell, Joab D. Henderson, Anil B. Lingambudi, Girisankar Paulraj
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Patent number: 9305618Abstract: A method, system and memory controller are provided for implementing simultaneous read and write operations in a memory subsystem utilizing a dual port Dynamic Random Access Memory (DRAM) configuration. A DRAM includes a first partition and a second partition. A memory controller determines if memory requirements are above or below a usage threshold. If the memory requirements are below the usage threshold, the memory is partitioned into a read buffer and a write buffer, with writes going to the write buffer and reads coming from the read buffer, data being transferred from the write buffer to the read buffer through an Error Correction Code (ECC) engine. If the memory requirements are above the usage threshold, the entire memory is used for reads and writes.Type: GrantFiled: January 30, 2014Date of Patent: April 5, 2016Assignee: International Business Machines CorporationInventors: Edgar R. Cordero, Carlos A. Fernandez, Joab D. Henderson, Jeffrey A. Sabrowski, Anuwat Saetow, Saravanan Sethuraman
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Patent number: 9305619Abstract: A method, system and memory controller are provided for implementing simultaneous read and write operations in a memory subsystem utilizing a dual port Dynamic Random Access Memory (DRAM) configuration. A DRAM includes a first partition and a second partition. A memory controller determines if memory requirements are above or below a usage threshold. If the memory requirements are below the usage threshold, the memory is partitioned into a read buffer and a write buffer, with writes going to the write buffer and reads coming from the read buffer, data being transferred from the write buffer to the read buffer through an Error Correction Code (ECC) engine. If the memory requirements are above the usage threshold, the entire memory is used for reads and writes.Type: GrantFiled: June 20, 2014Date of Patent: April 5, 2016Assignee: International Business Machines CorporationInventors: Edgar R. Cordero, Carlos A. Fernandez, Joab D. Henderson, Jeffrey A. Sabrowski, Anuwat Saetow, Saravanan Sethuraman
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Patent number: 9251054Abstract: A method, system and computer program product are provided for implementing enhanced reliability of memory subsystems utilizing a dual port Dynamic Random Access Memory (DRAM) configuration. The DRAM configuration includes a first buffer and a second buffer, each buffer including a validity counter. The validity counter for a receiving buffer is incremented as each respective data row from a transferring buffer is validated through Error Correction Code (ECC), Reliability, Availability, and Serviceability (RAS) logic and transferred to the receiving buffer, while the validity counter for the transferring buffer is decremented. Data are read from or written to either the first buffer or the second buffer based upon a respective count value of the validity counters.Type: GrantFiled: March 27, 2014Date of Patent: February 2, 2016Assignee: International Business Machines CorporationInventors: Edgar R. Cordero, Carlos A. Fernandez, Joab D. Henderson, Jeffrey A. Sabrowski, Anuwat Saetow, Saravanan Sethuraman
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Publication number: 20160027494Abstract: A method and apparatus for refreshing a row of a memory device prior to a scheduled refresh. A memory array may include a plurality of memory cells. The memory array may be configured to be refreshed at a first refresh time interval. The memory device may also include an intermediate refresh circuit. The intermediate refresh circuit may be configured to detect a triggering event and request a refresh for a row of the memory array in response to detecting a triggering event.Type: ApplicationFiled: October 8, 2015Publication date: January 28, 2016Inventors: Edgar R. Cordero, Joab D. Henderson, Kyu-hyoun Kim, Jeffrey A. Sabrowski, Anuwat Saetow
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Patent number: 9245604Abstract: A method and apparatus for refreshing a row of a memory device prior to a scheduled refresh. A memory array may include a plurality of memory cells. The memory array may be configured to be refreshed at a first refresh time interval. The memory device may also include an intermediate refresh circuit. The intermediate refresh circuit may be configured to detect a triggering event and request a refresh for a row of the memory array in response to detecting a triggering event.Type: GrantFiled: May 8, 2013Date of Patent: January 26, 2016Assignee: International Business Machines CorporationInventors: Edgar R. Cordero, Joab D. Henderson, Kyu-hyoun Kim, Jeffrey A. Sabrowski, Anuwat Saetow
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Patent number: 9230687Abstract: A method, system and computer program product are provided for implementing ECC (Error Correction Codes) redundancy using reconfigurable logic blocks in a computer system. When a fail is detected when reading from memory, it is determined if the incorrect data is in the data or the ECC component of the data. When incorrect data is found in the ECC component of the data, and an actionable threshold is not reached, a predetermined Reliability, Availability, and Serviceability (RAS) action is taken. When the actionable threshold is reached with incorrect data identified in the ECC component of the data, an analysis process is performed to determine if the ECC logic is faulty. When a fail in the ECC logic is detected, the identified ECC failed logic is replaced with a spare block of logic.Type: GrantFiled: April 22, 2013Date of Patent: January 5, 2016Assignee: International Business Machines CorporationInventors: Edgar R. Cordero, Timothy J. Dell, Joab D. Henderson, Jeffrey A. Sabrowski, Anuwat Saetow, Saravanan Sethuraman
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Patent number: 9224450Abstract: A method and apparatus for modifying a reference voltage between refreshes in a memory device are disclosed. The memory array may include a plurality of memory cells. The memory device may also include a sense amplifier. The sense amplifier may be configured to read data from the plurality of memory cells using a reference voltage. The memory device may also include a sense amplifier reference voltage modification circuit. The sense amplifier reference voltage modification circuit may be configured to detect a triggering event and modify the reference voltage in response to detecting a triggering event.Type: GrantFiled: May 8, 2013Date of Patent: December 29, 2015Assignee: International Business Machines CorporationInventors: Edgar R. Cordero, Joab D. Henderson, Kyu-hyoun Kim, Jeffrey A. Sabrowski, Anuwat Saetow