Abstract: Memory devices and methods are described that include a stack of memory dies and a logic die. Method and devices described include those that provide for repartitioning the stack of memory dies and storing the new partitions in a memory map. Repartitioning in selected configurations allows portions of memory to be removed from use without affecting the rest of the memory device. Additional devices, systems, and methods are disclosed.

Abstract: Memory devices and methods are described that include a stack of memory dies and an attached logic die. Method and devices described provide for power management of portions of a stack of memory dies. Additional devices, systems, and methods are disclosed.

Abstract: Systems and methods are disclosed herein, including those that operate to monitor a first set of operational parameters associated with a memory vault, to adjust a second set of operational parameters associated with the memory vault, and to perform alerting and reporting operations to a host device.

Abstract: Memory devices and methods are described such as those that monitor and adjust characteristics for various different portions of a given memory device. Examples of different portions include tiles, or arrays, or dies. One memory device and method described includes monitoring and adjusting characteristics of different portions of a 3D stack of memory dies. One characteristic that can be adjusted at multiple selected portions includes refresh rate.

Abstract: Systems and methods disclosed herein include those that may receive a memory request including a requested memory address and may send the memory request directly to an address decoder associated with a stacked-die memory vault without knowing whether a repair address is required. If a subsequent analysis of the memory request shows that a repair address is required, an in-process decode of the requested memory address can be halted and decoding of the repair address initiated.

Abstract: Electronic apparatus, systems, and methods of operating and constructing the electronic apparatus and/or systems include an embedded processor disposed in a logic chip to direct, among other functions, self-testing of an electronic device structure in conjunction with a pattern buffer disposed in the logic chip, when the electronic device structure is coupled to the logic chip. Additional apparatus, systems, and methods are disclosed.

Abstract: Memory requests for information from a processor are received in an interface device, and the interface device is coupled to a stack including two or more memory devices. The interface device is operated to select a memory device from a number of memory devices including the stack, and to retrieve some or all of the information from the selected memory device for the processor. Additional apparatus, systems and methods are disclosed.

Abstract: Various embodiments include apparatus, systems, and methods having multiple dice arranged in a stack in which a defective cell may be replaced by a spare cell on the same die or a different die.

Abstract: Apparatus and systems may include a substrate and a first memory device coupled to the substrate using a through wafer interconnect (TWI). An example may include an interface chip having a via to accommodate connection of the memory device to the substrate. Other apparatus, systems, and methods are disclosed.

Abstract: Systems and methods disclosed herein substantially concurrently transfer a plurality of streams of commands, addresses, and/or data across a corresponding plurality of serialized communication link interfaces (SCLIs) between one or more originating devices or destination devices such as a processor and a switch. At the switch, one or more commands, addresses, or data corresponding to each stream can be transferred to a corresponding destination memory vault controller (MVC) associated with a corresponding memory vault. The destination MVC can perform write operations, read operations, and/or memory vault housekeeping operations independently from concurrent operations associated with other MVCs coupled to a corresponding plurality of memory vaults.

Abstract: Apparatus and systems may include a substrate, an interface chip disposed on the substrate, a first memory die having a plurality of memory arrays disposed on the interface chip, the first memory die coupled to a plurality of through wafer interconnects (TWI), and a second memory die having a plurality of memory arrays disposed on the first memory die, the second memory die including a plurality of vias, wherein the plurality of vias are configured to allow the plurality of TWI to pass through the second memory die. The second memory die may be coupled to a second plurality of TWI. In this way, the interface chip may be used to communicatively couple the first memory die and the second memory die using the first and second plurality of TWI. Other apparatus, systems, and methods are included.

Abstract: Apparatus, method and systems are provided such as those that can include a processor module, an interface device disposed above or below the processor module, the interface device including a plurality of routing elements, at least one memory device disposed above or below the interface device and including a plurality of memory arrays, the plurality of memory arrays coupled to the interface device using a plurality of interconnects provided in vias provided in at least one of the memory device and the interface device. In addition, the interface device communicatively can couple the plurality of memory arrays to the processor module using the plurality of routing elements and the interconnects.

Abstract: Apparatus and systems may include a substrate, an interface chip disposed on the substrate, a first memory die having a plurality of memory arrays disposed on the interface chip, the first memory die coupled to a plurality of through wafer interconnects (TWI), and a second memory die having a plurality of memory arrays disposed on the first memory die, the second memory die including a plurality of vias, wherein the plurality of vias are configured to allow the plurality of TWI to pass through the second memory die. The second memory die may be coupled to a second plurality of TWI. In this way, the interface chip may be used to communicatively couple the first memory die and the second memory die using the first and second plurality of TWI. Other apparatus, systems, and methods are disclosed.

Abstract: A computer system and method concurrently process transactions directed to computer devices coupled to a bus agent. The method transmits first and second transaction requests from one or more computer processors across a computer bus to the bus agent. The bus agent transmits the first transaction request to a first computer device coupled to the bus agent. In addition, the bus agent transmits the second transaction request to a second computer device before the bus agent has received a transaction response to the first transaction request from the first computer device, thereby concurrently processing the transaction requests. The bus agent includes plural device managers each uniquely associated with one of the computer devices. Each device manager employs a queue pointer into a transaction queue to track each transaction involving the computer device associated with the device. manager.

Abstract: A computer system and method concurrently process transactions directed to computer devices coupled to a bus agent. The method transmits first and second transaction requests from one or more computer processors across a computer bus to the bus agent. The bus agent transmits the first transaction request to a first computer device coupled to the bus agent. In addition, the bus agent transmits the second transaction request to a second computer device before the bus agent has received a transaction response to the first transaction request from the first computer device, thereby concurrently processing the transaction requests. The bus agent includes plural device managers each uniquely associated with one of the computer devices. Each device manager employs a queue pointer into a transaction queue to track each transaction involving the computer device associated with the device. manager.

Abstract: An interface circuit, which can form part of a memory device or a memory controller, includes a read circuit, a write circuit, and a clocking circuit. The read circuit includes two registers or latches that receive alternate data read from burst EDO or synchronous memory. A multiplexer and read output register provide the data to a CPU or other application. If the memory is burst EDO, then the clocking circuit receives the system clock signal and generates a CAS signal based on positive or negative going edges of the clock signal, depending upon delays inherent in the system in which the present invention is employed. The CAS signal is then used to drive the two read latches. If the memory is synchronous memory, then the clock circuit includes an inverter that inverts the clock signal, and provides the inverted clock signal to the synchronous memory. The inverted clock signal is delayed and then used to drive the two read registers.

Abstract: An interface circuit, which can form part of a memory device or a memory controller, includes a read circuit, a write circuit, and a clocking circuit. The read circuit includes two registers or latches that receive alternate data read from burst EDO or synchronous memory. A multiplexer and read output register provide the data to a CPU or other application. If the memory is burst EDO, then the clocking circuit receives the system clock signal and generates a CAS signal based on positive or negative going edges of the clock signal, depending upon delays inherent in the system in which the present invention is employed. The CAS signal is then used to drive the two read latches. If the memory is synchronous memory, then the clock circuit includes an inverter that inverts the clock signal, and provides the inverted clock signal to the synchronous memory. The inverted clock signal is delayed and then used to drive the two read registers.

Abstract: A computer system and method concurrently process transactions directed to computer devices coupled to a bus agent. The method transmits first and second transaction requests from one or more computer processors across a computer bus to the bus agent. The bus agent transmits the first transaction request to a first computer device coupled to the bus agent. In addition, the bus agent transmits the second transaction request to a second computer device before the bus agent has received a transaction response to the first transaction request from the first computer device, thereby concurrently processing the transaction requests. The bus agent includes plural device managers each uniquely associated with one of the computer devices. Each device manager employs a queue pointer into a transaction queue to track each transaction involving the computer device associated with the device manager.