Patents by Inventor Joe M. Jeddeloh

Joe M. Jeddeloh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Stacked device remapping and repair
    Patent number: 8503258
    Abstract: Various embodiments include apparatus, systems, and methods having multiple dice arranged in a stack in which a defective cell may be replaced by a spare cell on the same die or a different die. Other embodiments are described.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: August 6, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Brent Keeth, Chris G. Martin, Troy A. Manning, Joe M. Jeddeloh, Timothy B. Cowles, Jim Rehmeyer, Paul A. LaBerge
  • Memory devices and methods for managing error regions
    Patent number: 8392771
    Abstract: Memory devices and methods are described that include a stack of memory dies and a logic die. Method and devices described include those that provide for repartitioning the stack of memory dies and storing the new partitions in a memory map. Repartitioning in selected configurations allows portions of memory to be removed from use without affecting the rest of the memory device. Additional devices, systems, and methods are disclosed.
    Type: Grant
    Filed: February 27, 2012
    Date of Patent: March 5, 2013
    Assignee: Micron Technology, Inc.
    Inventor: Joe M. Jeddeloh
  • Memory prefetch systems and methods
    Patent number: 8364901
    Abstract: Systems and methods are disclosed herein, including those that operate to prefetch a programmable number of data words from a selected memory vault in a stacked-die memory system when a pipeline associated with the selected memory vault is empty.
    Type: Grant
    Filed: February 13, 2009
    Date of Patent: January 29, 2013
    Assignee: Micron Technology, Inc.
    Inventor: Joe M. Jeddeloh
  • STACKED DEVICE REMAPPING AND REPAIR
    Publication number: 20130003473
    Abstract: Various embodiments include apparatus, systems, and methods having multiple dice arranged in a stack in which a defective cell may be replaced by a spare cell on the same die or a different die. Other embodiments are described.
    Type: Application
    Filed: September 14, 2012
    Publication date: January 3, 2013
    Applicant: Micron Technology, Inc.
    Inventors: Brent Keeth, Chris G. Martin, Troy A. Manning, Joe M. Jeddeloh, Timothy B. Cowles, Jim Rehmeyer, Paul A. LaBerge
  • Memory device interface methods, apparatus, and systems
    Patent number: 8339827
    Abstract: Apparatus and systems may include an interface chip, a first memory die having at least one memory array disposed on the interface chip, and a second memory die having at least one memory array disposed on the first memory die. The first memory die can include a plurality of vias configure allow a first plurality of through wafer interconnects (TWIs) to couple the interface chip with the second memory die, and the interface chip can be configured to communicatively couple the first memory die and the second memory die. Other apparatus, systems, and methods are disclosed.
    Type: Grant
    Filed: May 4, 2012
    Date of Patent: December 25, 2012
    Assignee: Micron Technology, Inc.
    Inventor: Joe M. Jeddeloh
  • SWITCHED INTERFACE STACKED-DIE MEMORY ARCHITECTURE
    Publication number: 20120320688
    Abstract: Systems and methods disclosed herein include those that may receive a memory request including a requested memory address and may send the memory request directly to an address decoder associated with a stacked-die memory vault without knowing whether a repair address is required. If a subsequent analysis of the memory request shows that a repair address is required, an in-process decode of the requested memory address can be halted and decoding of the repair address initiated.
    Type: Application
    Filed: August 27, 2012
    Publication date: December 20, 2012
    Inventors: Joe M. Jeddeloh, Paul A. LaBerge
  • Error correction in a stacked memory
    Patent number: 8327225
    Abstract: Electronic apparatus, systems, and methods to construct and operate the electronic apparatus and/or systems include a stack of memory dies with user data and/or first level error correction data stored in a stripe across the memory dies. One such stack can include a second level error correction vault, such as a parity vault, to store parity data corresponding to the user data and/or first level error correction data. Additional apparatus, systems, and methods are disclosed.
    Type: Grant
    Filed: January 4, 2010
    Date of Patent: December 4, 2012
    Assignee: Micron Technology, Inc.
    Inventor: Joe M. Jeddeloh
  • Stacked device remapping and repair
    Patent number: 8320206
    Abstract: Various embodiments include apparatus, systems, and methods having multiple dice arranged in a stack in which a defective cell may be replaced by a spare cell on the same die or a different die. Other embodiments are described.
    Type: Grant
    Filed: November 15, 2010
    Date of Patent: November 27, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Brent Keeth, Chris G. Martin, Troy A. Manning, Joe M. Jeddeloh, Timothy B. Cowles, Jim Rehmeyer, Paul A. LaBerge
  • SYSTEMS AND METHODS FOR MONITORING A MEMORY SYSTEM
    Publication number: 20120297241
    Abstract: Systems and methods are disclosed herein, including those that operate to monitor a first set of operational parameters associated with a memory vault, to adjust a second set of operational parameters associated with the memory vault, and to perform alerting and reporting operations to a host device.
    Type: Application
    Filed: July 30, 2012
    Publication date: November 22, 2012
    Inventor: Joe M. Jeddeloh
  • Data transfer management
    Patent number: 8291131
    Abstract: Methods, controllers, and systems for managing data transfer, such as those in solid state drives (SSDs), are described. In some embodiments, the data transfer between a host and a memory is monitored and then assessed to provide an assessment result. A number of storage units of the memory allocated to service another data transfer is adjusted based on the assessment result. Additional methods and systems are also described.
    Type: Grant
    Filed: July 6, 2009
    Date of Patent: October 16, 2012
    Assignee: Micron Technology, Inc.
    Inventor: Joe M. Jeddeloh
  • CONFIGURABLE BANDWIDTH MEMORY DEVICES AND METHODS
    Publication number: 20120257434
    Abstract: Memory devices and methods are described, such as those that include a stack of memory dies and an attached logic die. Method and devices described provide for configuring bandwidth for selected portions of a stack of memory dies. Additional devices, systems, and methods are disclosed.
    Type: Application
    Filed: June 15, 2012
    Publication date: October 11, 2012
    Inventor: Joe M. Jeddeloh
  • VARIABLE MEMORY REFRESH DEVICES AND METHODS
    Publication number: 20120250388
    Abstract: Memory devices and methods are described such as those that monitor and adjust characteristics for various different portions of a given memory device. Examples of different portions include tiles, or arrays, or dies. One memory device and method described includes monitoring and adjusting characteristics of different portions of a 3D stack of memory dies. One characteristic that can be adjusted at multiple selected portions includes refresh rate.
    Type: Application
    Filed: June 11, 2012
    Publication date: October 4, 2012
    Inventor: Joe M. Jeddeloh
  • Interface device for memory in a stack, storage devices and a processor
    Patent number: 8281074
    Abstract: Memory requests for information from a processor are received in an interface device, and the interface device is coupled to a stack including two or more memory devices. The interface device is operated to select a memory device from a number of memory devices including the stack, and to retrieve some or all of the information from the selected memory device for the processor. Additional apparatus, systems and methods are disclosed.
    Type: Grant
    Filed: October 7, 2008
    Date of Patent: October 2, 2012
    Assignee: Micron Technology, Inc.
    Inventor: Joe M. Jeddeloh
  • EMBEDDED PROCESSOR
    Publication number: 20120221911
    Abstract: Electronic apparatus, systems, and methods of operating and constructing the electronic apparatus and/or systems include an embedded processor disposed in a logic chip to direct, among other functions, self-testing of an electronic device structure in conjunction with a pattern buffer disposed in the logic chip, when the electronic device structure is coupled to the logic chip. Additional apparatus, systems, and methods are disclosed.
    Type: Application
    Filed: May 7, 2012
    Publication date: August 30, 2012
    Inventor: Joe M. Jeddeloh
  • MEMEORY DEVICE INTERFACE METHODS, APPARATUS, AND SYSTEMS
    Publication number: 20120218803
    Abstract: Apparatus and systems may include an interface chip, a first memory die having at least one memory array disposed on the interface chip, and a second memory die having at least one memory array disposed on the first memory die. The first memory die can include a plurality of vias configure allow a first plurality of through wafer interconnects (TWIs) to couple the interface chip with the second memory die, and the interface chip can be configured to communicatively couple the first memory die and the second memory die. Other apparatus, systems, and methods are disclosed.
    Type: Application
    Filed: May 4, 2012
    Publication date: August 30, 2012
    Inventor: Joe M. Jeddeloh
  • Switched interface stacked-die memory architecture
    Patent number: 8254191
    Abstract: Systems and methods disclosed herein include those that may receive a memory request including a requested memory address and may send the memory request directly to an address decoder associated with a stacked-die memory vault without knowing whether a repair address is required. If a subsequent analysis of the memory request shows that a repair address is required, an in-process decode of the requested memory address can be halted and decoding of the repair address initiated.
    Type: Grant
    Filed: October 30, 2008
    Date of Patent: August 28, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Joe M. Jeddeloh, Paul A. LaBerge
  • Systems and methods for monitoring a memory system
    Patent number: 8234528
    Abstract: Systems and methods are disclosed herein, including those that operate to monitor a first set of operational parameters associated with a memory vault, to adjust a second set of operational parameters associated with the memory vault, and to perform alerting and reporting operations to a host device.
    Type: Grant
    Filed: September 30, 2011
    Date of Patent: July 31, 2012
    Assignee: Micron Technology, Inc.
    Inventor: Joe M. Jeddeloh
  • MEMORY DEVICES AND METHODS FOR MANAGING ERROR REGIONS
    Publication number: 20120159270
    Abstract: Memory devices and methods are described that include a stack of memory dies and a logic die. Method and devices described include those that provide for repartitioning the stack of memory dies and storing the new partitions in a memory map. Repartitioning in selected configurations allows portions of memory to be removed from use without affecting the rest of the memory device. Additional devices, systems, and methods are disclosed.
    Type: Application
    Filed: February 27, 2012
    Publication date: June 21, 2012
    Inventor: Joe M. Jeddeloh
  • Configurable bandwidth memory devices and methods
    Patent number: 8203901
    Abstract: Memory devices and methods are described, such as those that include a stack of memory dies and an attached logic die. Method and devices described provide for configuring bandwidth for selected portions of a stack of memory dies. Additional devices, systems, and methods are disclosed.
    Type: Grant
    Filed: July 8, 2011
    Date of Patent: June 19, 2012
    Assignee: Micron Technology, Inc.
    Inventor: Joe M. Jeddeloh
  • Variable memory refresh devices and methods
    Patent number: 8199599
    Abstract: Memory devices and methods are described such as those that monitor and adjust characteristics for various different portions of a given memory device. Examples of different portions include tiles, or arrays, or dies. One memory device and method described includes monitoring and adjusting characteristics of different portions of a 3D stack of memory dies. One characteristic that can be adjusted at multiple selected portions includes refresh rate.
    Type: Grant
    Filed: April 18, 2011
    Date of Patent: June 12, 2012
    Assignee: Micron Technology, Inc.
    Inventor: Joe M. Jeddeloh