Patents by Inventor Joe M. Jeddeloh

Joe M. Jeddeloh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Variable memory refresh devices and methods
    Patent number: 8797818
    Abstract: Memory devices and methods are described such as those that monitor and adjust characteristics for various different portions of a given memory device. Examples of different portions include tiles, or arrays, or dies. One memory device and method described includes monitoring and adjusting characteristics of different portions of a 3D stack of memory dies. One characteristic that can be adjusted at multiple selected portions includes refresh rate.
    Type: Grant
    Filed: June 11, 2012
    Date of Patent: August 5, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Joe M. Jeddeloh
  • STACKED-DIE MEMORY SYSTEMS AND METHODS FOR TRAINING STACKED-DIE MEMORY SYSTEMS
    Publication number: 20140204690
    Abstract: Systems and methods are disclosed herein, such as those that operate to control a set of delays associated with one or more data clocks to clock a set of data bits into one or more transmit registers, one or more data strobes to transfer the set of data bits to at least one receive register, and/or a set of memory array timing signals to access a memory array on a die associated with a stacked-die memory vault. Systems and methods herein also include those that perform data eye training operations and/or memory array timing training operations associated with the stacked-die memory vault.
    Type: Application
    Filed: March 21, 2014
    Publication date: July 24, 2014
    Applicant: Micron Technology, Inc.
    Inventor: Joe M. Jeddeloh
  • Stacked device remapping and repair
    Patent number: 8787101
    Abstract: Various embodiments include apparatus, systems, and methods having multiple dice arranged in a stack in which a defective cell may be replaced by a spare cell on the same die or a different die. Other embodiments are described.
    Type: Grant
    Filed: August 5, 2013
    Date of Patent: July 22, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Brent Keeth, Chris G. Martin, Troy A. Manning, Joe M. Jeddeloh, Timothy B. Cowles, Jim Rehmeyer, Paul A. LaBerge
  • Embedded processor
    Patent number: 8775881
    Abstract: Electronic apparatus, systems, and methods of operating and constructing the electronic apparatus and/or systems include an embedded processor disposed in a logic chip to direct, among other functions, self-testing of an electronic device structure in conjunction with a pattern buffer disposed in the logic chip, when the electronic device structure is coupled to the logic chip. Additional apparatus, systems, and methods are disclosed.
    Type: Grant
    Filed: August 26, 2013
    Date of Patent: July 8, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Joe M. Jeddeloh
  • MEMORY PREFETCH SYSTEMS AND METHODS
    Publication number: 20140156946
    Abstract: Systems and methods are disclosed herein, including those that operate to prefetch a programmable number of data words from a selected memory vault in a stacked-die memory system when a pipeline associated with the selected memory vault is empty.
    Type: Application
    Filed: December 9, 2013
    Publication date: June 5, 2014
    Applicant: Micron Technology, Inc.
    Inventor: Joe M. Jeddeloh
  • SWITCHED INTERFACE STACKED-DIE MEMORY ARCHITECTURE
    Publication number: 20140112085
    Abstract: Systems and methods disclosed herein include those that may receive a memory request including a requested memory address and may send the memory request directly to an address decoder associated with a stacked-die memory vault without knowing whether a repair address is required. If a subsequent analysis of the memory request shows that a repair address is required, an in-process decode of the requested memory address can be halted and decoding of the repair address initiated.
    Type: Application
    Filed: December 27, 2013
    Publication date: April 24, 2014
    Applicant: Micron Technology, Inc.
    Inventors: Joe M. Jeddeloh, Paul A. LaBerge
  • CONFIGURABLE BANDWIDTH MEMORY DEVICES AND METHODS
    Publication number: 20140112046
    Abstract: Memory devices and methods are described, such as those that include a stack of memory dies and an attached logic die. Method and devices described provide for configuring bandwidth for selected portions of a stack of memory dies. Additional devices, systems, and methods are disclosed.
    Type: Application
    Filed: December 20, 2013
    Publication date: April 24, 2014
    Applicant: MICRON TECHNOLOGY, INC.
    Inventor: Joe M. Jeddeloh
  • Data transfer management
    Patent number: 8706929
    Abstract: Methods, controllers, and systems for managing data transfer, such as those in solid state drives (SSDs), are described. In some embodiments, the data transfer between a host and a memory is monitored and then assessed to provide an assessment result. A number of storage units of the memory allocated to service another data transfer is adjusted based on the assessment result. Additional methods and systems are also described.
    Type: Grant
    Filed: October 15, 2012
    Date of Patent: April 22, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Joe M. Jeddeloh
  • Stacked-die memory systems and methods for training stacked-die memory systems
    Patent number: 8683164
    Abstract: Systems and methods are disclosed herein, such as those that operate to control a set of delays associated with one or more data clocks to clock a set of data bits into one or more transmit registers, one or more data strobes to transfer the set of data bits to at least one receive register, and/or a set of memory array timing signals to access a memory array on a die associated with a stacked-die memory vault. Systems and methods herein also include those that perform data eye training operations and/or memory array timing training operations associated with the stacked-die memory vault.
    Type: Grant
    Filed: February 4, 2009
    Date of Patent: March 25, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Joe M. Jeddeloh
  • Configurable bandwidth memory devices and methods
    Patent number: 8681523
    Abstract: Memory devices and methods are described, such as those that include a stack of memory dies and an attached logic die. Method and devices described provide for configuring bandwidth for selected portions of a stack of memory dies. Additional devices, systems, and methods are disclosed.
    Type: Grant
    Filed: June 15, 2012
    Date of Patent: March 25, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Joe M. Jeddeloh
  • MEMORY DEVICE INTERFACE METHODS, APPARATUS, AND SYSTEMS
    Publication number: 20140063942
    Abstract: Apparatus and systems for memory system are provided. In an example, an interface chip can include a memory controller configured to couple to a processor and to couple to a plurality of stacked memory arrays using a data bus and a maintenance bus, wherein the data bus is separate from the maintenance bus, the plurality of stacked memory arrays forming two or more memory chips, the memory controller configured to control access to memory locations within the plurality of stacked memory arrays.
    Type: Application
    Filed: October 29, 2013
    Publication date: March 6, 2014
    Applicant: Micron Technology, Inc.
    Inventor: Joe M. Jeddeloh
  • STACKED MEMORY DEVICES, SYSTEMS, AND METHODS
    Publication number: 20140068190
    Abstract: Memory requests for information from a processor are received in an interface device, and the interface device is coupled to a stack including two or more memory devices. The interface device is operated to select a memory device from a number of memory devices including the stack, and to retrieve some or all of the information from the selected memory device for the processor. Additional apparatus, systems and methods are disclosed.
    Type: Application
    Filed: November 11, 2013
    Publication date: March 6, 2014
    Applicant: Micron Technology, Inc.
    Inventor: Joe M. Jeddeloh
  • Switched interface stacked-die memory architecture
    Patent number: 8619481
    Abstract: Systems and methods disclosed herein include those that may receive a memory request including a requested memory address and may send the memory request directly to an address decoder associated with a stacked-die memory vault without knowing whether a repair address is required. If a subsequent analysis of the memory request shows that a repair address is required, an in-process decode of the requested memory address can be halted and decoding of the repair address initiated.
    Type: Grant
    Filed: August 27, 2012
    Date of Patent: December 31, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Joe M. Jeddeloh, Paul A. LaBerge
  • EMBEDDED PROCESSOR
    Publication number: 20130346820
    Abstract: Electronic apparatus, systems, and methods of operating and constructing the electronic apparatus and/or systems include an embedded processor disposed in a logic chip to direct, among other functions, self-testing of an electronic device structure in conjunction with a pattern buffer disposed in the logic chip, when the electronic device structure is coupled to the logic chip. Additional apparatus, systems, and methods are disclosed.
    Type: Application
    Filed: August 26, 2013
    Publication date: December 26, 2013
    Applicant: Micron Technology, Inc.
    Inventor: Joe M. Jeddeloh
  • STACKED DEVICE REMAPPING AND REPAIR
    Publication number: 20130329510
    Abstract: Various embodiments include apparatus, systems, and methods having multiple dice arranged in a stack in which a defective cell may be replaced by a spare cell on the same die or a different die. Other embodiments are described.
    Type: Application
    Filed: August 5, 2013
    Publication date: December 12, 2013
    Applicant: Micron Technology, Inc.
    Inventors: Brent Keeth, Chris G. Martin, Troy A. Manning, Joe M. Jeddeloh, Timothy B. Cowles, Jim Rehmeyer, Paul A. LaBerge
  • Memory prefetch systems and methods
    Patent number: 8607002
    Abstract: Systems and methods are disclosed herein, including those that operate to prefetch a programmable number of data words from a selected memory vault in a stacked-die memory system when a pipeline associated with the selected memory vault is empty.
    Type: Grant
    Filed: January 28, 2013
    Date of Patent: December 10, 2013
    Assignee: Micron Technology, Inc.
    Inventor: Joe M. Jeddeloh
  • Systems and methods for monitoring a memory system
    Patent number: 8601332
    Abstract: Systems and methods are disclosed herein, including those that operate to monitor a first set of operational parameters associated with a memory vault, to adjust a second set of operational parameters associated with the memory vault, and to perform alerting and reporting operations to a host device.
    Type: Grant
    Filed: July 30, 2012
    Date of Patent: December 3, 2013
    Assignee: Micron Technology, Inc.
    Inventor: Joe M. Jeddeloh
  • Memory device interface methods, apparatus, and systems
    Patent number: 8593849
    Abstract: Apparatus and systems for memory system are provided. In an example, a memory system can include a plurality of memory dice and an interface chip. The memory dice can include a first memory die including a memory array coupled to through wafer interconnects (TWIs) and a second memory die, wherein the first memory die is stacked over the second memory die. In an example, the interface chip can be coupled to the TWIs and configured to provide memory commands to selected memory addresses within the plurality of memory dice. In an example, the interface chip can be configured to perform DRAM sequencing.
    Type: Grant
    Filed: November 27, 2012
    Date of Patent: November 26, 2013
    Assignee: Micron Technology, Inc.
    Inventor: Joe M. Jeddeloh
  • Stacked memory devices, systems, and methods
    Patent number: 8583870
    Abstract: Memory requests for information from a processor are received in an interface device, and the interface device is coupled to a stack including two or more memory devices. The interface device is operated to select a memory device from a number of memory devices including the stack, and to retrieve some or all of the information from the selected memory device for the processor. Additional apparatus, systems and methods are disclosed.
    Type: Grant
    Filed: October 1, 2012
    Date of Patent: November 12, 2013
    Assignee: Micron Technology, Inc.
    Inventor: Joe M. Jeddeloh
  • Embedded processor
    Patent number: 8522099
    Abstract: Electronic apparatus, systems, and methods of operating and constructing the electronic apparatus and/or systems include an embedded processor disposed in a logic chip to direct, among other functions, self-testing of an electronic device structure in conjunction with a pattern buffer disposed in the logic chip, when the electronic device structure is coupled to the logic chip. Additional apparatus, systems, and methods are disclosed.
    Type: Grant
    Filed: May 7, 2012
    Date of Patent: August 27, 2013
    Assignee: Micron Technology, Inc.
    Inventor: Joe M. Jeddeloh