Patents by Inventor Joel A. Drewes
Joel A. Drewes has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8565016Abstract: The present invention provides a method of fabricating a portion of a memory cell, the method comprising providing a first conductor in a trench which is provided in an insulating layer and flattening an upper surface of the insulating layer and the first conductor, forming a material layer over the flattened upper surface of the insulating layer and the first conductor and flattening an upper portion of the material layer while leaving intact a lower portion of the material layer over the insulating layer and the first conductor.Type: GrantFiled: May 13, 2008Date of Patent: October 22, 2013Assignee: Micron Technology, Inc.Inventors: Donald L. Yates, Joel A. Drewes
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Patent number: 8368133Abstract: The invention includes a method of forming a semiconductor construction, such as an MRAM construction. A block is formed over a semiconductor substrate. First and second layers are formed over the block, and over a region of the substrate proximate the block. The first and second layers are removed from over the block while leaving portions of the first and second layers over the region proximate the block. At least some of the first layer is removed from under the second layer to form a channel over the region proximate the block. A material, such as a soft magnetic material, is provided within the channel. The invention also includes semiconductor constructions.Type: GrantFiled: February 10, 2011Date of Patent: February 5, 2013Assignee: Micron Technology, Inc.Inventor: Joel A. Drewes
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Publication number: 20110140218Abstract: The invention includes a method of forming a semiconductor construction, such as an MRAM construction. A block is formed over a semiconductor substrate. First and second layers are formed over the block, and over a region of the substrate proximate the block. The first and second layers are removed from over the block while leaving portions of the first and second layers over the region proximate the block. At least some of the first layer is removed from under the second layer to form a channel over the region proximate the block. A material, such as a soft magnetic material, is provided within the channel. The invention also includes semiconductor constructions.Type: ApplicationFiled: February 10, 2011Publication date: June 16, 2011Applicant: MICRON TECHNOLOGY, INC.Inventor: Joel A. Drewes
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Patent number: 7947597Abstract: Some embodiments include methods of titanium deposition in which a silicon-containing surface and an electrically insulative surface are both exposed to titanium-containing material, and in which such exposure forms titanium silicide from the silicon-containing surface while not depositing titanium onto the electrically insulative surface. The embodiments may include atomic layer deposition processes, and may include a hydrogen pre-treatment of the silicon-containing surfaces to activate the surfaces for reaction with the titanium-containing material. Some embodiments include methods of titanium deposition in which a semiconductor material surface and an electrically insulative surface are both exposed to titanium-containing material, and in which a titanium-containing film is uniformly deposited across both surfaces.Type: GrantFiled: March 9, 2010Date of Patent: May 24, 2011Assignee: Micron Technology, Inc.Inventors: Joel A. Drewes, Cem Basceri, Demetrius Sarigiannis
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Patent number: 7902580Abstract: The invention includes a method of forming a semiconductor construction, such as an MRAM construction. A block is formed over a semiconductor substrate. First and second layers are formed over the block, and over a region of the substrate proximate the block. The first and second layers are removed from over the block while leaving portions of the first and second layers over the region proximate the block. At least some of the first layer is removed from under the second layer to form a channel over the region proximate the block. A material, such as a soft magnetic material, is provided within the channel. The invention also includes semiconductor constructions.Type: GrantFiled: September 17, 2009Date of Patent: March 8, 2011Assignee: Micron Technology, Inc.Inventor: Joel A. Drewes
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Patent number: 7884405Abstract: Magneto-resistive random access memory elements include a ferromagnetic layer having uniaxial anisotropy provided by elongate structures formed in the ferromagnetic film. The magnetic dipole aligns with the long axis of each structure. The structures can be formed in a variety of ways. For example, the ferromagnetic film can be applied to a seed layer having a textured surface. Alternatively, the ferromagnetic film can be stressed to generate the textured structure. Chemical mechanical polishing also can be used to generated the structures.Type: GrantFiled: November 26, 2008Date of Patent: February 8, 2011Assignee: Micron Technology, Inc.Inventor: Joel A. Drewes
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Patent number: 7855085Abstract: An MRAM device includes an array of magnetic memory cells having an upper conductive layer and a lower conductive layer separated by a barrier layer. To reduce the likelihood of electrical shorting across the barrier layers of the memory cells, spacers can be formed around the upper conductive layer and, after the layers of the magnetic memory cells have been etched, the memory cells can be oxidized to transform any conductive particles that are deposited along the sidewalls of the memory cells as byproducts of the etching process into nonconductive particles. Alternatively, the lower conductive layer can be repeatedly subjected to partial oxidation and partial etching steps such that only nonconductive particles can be thrown up along the sidewalls of the memory cells as byproducts of the etching process.Type: GrantFiled: September 26, 2006Date of Patent: December 21, 2010Assignee: Micron Technology, Inc.Inventors: Joel A. Drewes, James G. Deak
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Publication number: 20100167542Abstract: Some embodiments include methods of titanium deposition in which a silicon-containing surface and an electrically insulative surface are both exposed to titanium-containing material, and in which such exposure forms titanium silicide from the silicon-containing surface while not depositing titanium onto the electrically insulative surface. The embodiments may include atomic layer deposition processes, and may include a hydrogen pre-treatment of the silicon-containing surfaces to activate the surfaces for reaction with the titanium-containing material. Some embodiments include methods of titanium deposition in which a semiconductor material surface and an electrically insulative surface are both exposed to titanium-containing material, and in which a titanium-containing film is uniformly deposited across both surfaces.Type: ApplicationFiled: March 9, 2010Publication date: July 1, 2010Applicant: MICRON TECHNOLOGY, INC.Inventors: Joel A. Drewes, Cem Basceri, Demetrius Sarigiannis
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Patent number: 7700480Abstract: Some embodiments include methods of titanium deposition in which a silicon-containing surface and an electrically insulative surface are both exposed to titanium-containing material, and in which such exposure forms titanium silicide from the silicon-containing surface while not depositing titanium onto the electrically insulative surface. The embodiments may include atomic layer deposition processes, and may include a hydrogen pre-treatment of the silicon-containing surfaces to activate the surfaces for reaction with the titanium-containing material. Some embodiments include methods of titanium deposition in which a semiconductor material surface and an electrically insulative surface are both exposed to titanium-containing material, and in which a titanium-containing film is uniformly deposited across both surfaces.Type: GrantFiled: April 27, 2007Date of Patent: April 20, 2010Assignee: Micron Technology, Inc.Inventors: Joel A. Drewes, Cem Basceri, Demetrius Sarigiannis
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Patent number: 7662649Abstract: The invention includes deposition apparatuses having reflectors with rugged reflective surfaces configured to disperse light reflected therefrom, and/or having dispersers between lamps and a substrate. The invention also includes optical methods for utilization within a deposition apparatus for assessing the alignment of a substrate within the apparatus and/or for assessing the thickness of a layer of material deposited within the apparatus.Type: GrantFiled: May 31, 2006Date of Patent: February 16, 2010Assignee: Micron Technology, Inc.Inventors: Eric R. Blomiley, Nirmal Ramaswamy, Ross S. Dando, Joel A. Drewes
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Publication number: 20100019298Abstract: The invention includes a method of forming a semiconductor construction, such as an MRAM construction. A block is formed over a semiconductor substrate. First and second layers are formed over the block, and over a region of the substrate proximate the block. The first and second layers are removed from over the block while leaving portions of the first and second layers over the region proximate the block. At least some of the first layer is removed from under the second layer to form a channel over the region proximate the block. A material, such as a soft magnetic material, is provided within the channel. The invention also includes semiconductor constructions.Type: ApplicationFiled: September 17, 2009Publication date: January 28, 2010Applicant: MICRON TECHNOLOGY, INC.Inventor: Joel A. Drewes
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Patent number: 7622388Abstract: The invention includes methods of forming titanium-containing materials, such as, for example, titanium silicide. The invention can use alternating cycles of titanium halide precursor and one or more reductants to form the titanium-containing material. For instance, the invention can utilize alternating cycles of titanium tetrachloride and activated hydrogen to form titanium silicide on a surface of a silicon-containing substrate.Type: GrantFiled: March 7, 2008Date of Patent: November 24, 2009Assignee: Micron Technolyg, Inc.Inventors: Jaydeb Goswami, Joel A. Drewes
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Patent number: 7605417Abstract: The invention includes a method of forming a semiconductor construction, such as an MRAM construction. A block is formed over a semiconductor substrate. First and second layers are formed over the block, and over a region of the substrate proximate the block. The first and second layers are removed from over the block while leaving portions of the first and second layers over the region proximate the block. At least some of the first layer is removed from under the second layer to form a channel over the region proximate the block. A material, such as a soft magnetic material, is provided within the channel. The invention also includes semiconductor constructions.Type: GrantFiled: May 30, 2007Date of Patent: October 20, 2009Assignee: Micron Technology, Inc.Inventor: Joel A. Drewes
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Patent number: 7585371Abstract: In one implementation, a substrate susceptor for receiving a semiconductor substrate for selective epitaxial silicon-comprising depositing thereon, where the depositing comprises measuring emissivity of the susceptor from at least one susceptor location in a non-contacting manner, includes a body having a front substrate receiving side, a back side, and a peripheral edge. At least one susceptor location from which emissivity is to be measured is received on at least one of the front substrate receiving side, the back side, and the edge. Such at least one susceptor location comprises an outermost surface comprising a material upon which selective epitaxial silicon will not deposit upon during selective epitaxial silicon depositing on a semiconductor substrate received by the susceptor for at least an initial thickness of epitaxial silicon depositing on said substrate. Other aspects and implementations are contemplated.Type: GrantFiled: April 8, 2004Date of Patent: September 8, 2009Assignee: Micron Technology, Inc.Inventors: Eric R. Blomiley, Nirmal Ramaswamy, Ross S. Dando, Joel A. Drewes, Danny Dynka
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Patent number: 7517704Abstract: A common pinned layer is shared by multiple memory cells in an MRAM device. The common pinned layer includes a plurality of domain wall traps that prevent the formation of domain walls within a region of the common pinned layer corresponding to a given memory cell. Therefore, the memory cells can advantageously be formed such that the domain walls, to the extent they exist, fall between (rather than within) the memory cells, thereby improving the performance of the MRAM device.Type: GrantFiled: August 31, 2007Date of Patent: April 14, 2009Assignee: Micron Technology, Inc.Inventor: Joel A. Drewes
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Publication number: 20090080240Abstract: Magneto-resistive random access memory elements include a ferromagnetic layer having uniaxial anisotropy provided by elongate structures formed in the ferromagnetic film. The magnetic dipole aligns with the long axis of each structure. The structures can be formed in a variety of ways. For example, the ferromagnetic film can be applied to a seed layer having a textured surface. Alternatively, the ferromagnetic film can be stressed to generate the textured structure. Chemical mechanical polishing also can be used to generated the structures.Type: ApplicationFiled: November 26, 2008Publication date: March 26, 2009Inventor: Joel A. Drewes
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Patent number: 7470552Abstract: Magneto-resistive random access memory elements include a ferromagnetic layer having uniaxial anisotropy provided by elongate structures formed in the ferromagnetic film. The magnetic dipole aligns with the long axis of each structure. The structures can be formed in a variety of ways. For example, the ferromagnetic film can be applied to a seed layer having a textured surface. Alternatively, the ferromagnetic film can be stressed to generate the textured structure. Chemical mechanical polishing also can be used to generated the structures.Type: GrantFiled: February 1, 2007Date of Patent: December 30, 2008Assignee: Micron Technology, Inc.Inventor: Joel A. Drewes
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Publication number: 20080290432Abstract: The present invention provides a method of fabricating a portion of a memory cell, the method comprising providing a first conductor in a trench which is provided in an insulating layer and flattening an upper surface of the insulating layer and the first conductor, forming a material layer over the flattened upper surface of the insulating layer and the first conductor and flattening an upper portion of the material layer while leaving intact a lower portion of the material layer over the insulating layer and the first conductor.Type: ApplicationFiled: May 13, 2008Publication date: November 27, 2008Inventors: Donald L. Yates, Joel A. Drewes
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Publication number: 20080268633Abstract: Some embodiments include methods of titanium deposition in which a silicon-containing surface and an electrically insulative surface are both exposed to titanium-containing material, and in which such exposure forms titanium suicide from the silicon-containing surface while not depositing titanium onto the electrically insulative surface. The embodiments may include atomic layer deposition processes, and may include a hydrogen pre-treatment of the silicon-containing surfaces to activate the surfaces for reaction with the titanium-containing material. Some embodiments include methods of titanium deposition in which a semiconductor material surface and an electrically insulative surface are both exposed to titanium-containing material, and in which a titanium-containing film is uniformly deposited across both surfaces.Type: ApplicationFiled: April 27, 2007Publication date: October 30, 2008Inventors: Joel A. Drewes, Cem Basceri, Demetrius Sarigiannis
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Publication number: 20080233700Abstract: The invention includes semiconductor processing methods in which openings are formed to extend into a semiconductor substrate, and the substrate is then annealed around the openings to form cavities. The substrate is etched to expose the cavities, and the cavities are substantially filled with insulative material. The semiconductor substrate having the filled cavities therein can be utilized as a semiconductor-on-insulator-type structure, and transistor devices can be formed to be supported by the semiconductor material and to be over the cavities. In some aspects, the transistor devices have channel regions over the filled cavities, and in other aspects the transistor devices have source/drain regions over the filled cavities. The transistor devices can be incorporated into dynamic random access memory, and can be utilized in electronic systems.Type: ApplicationFiled: March 15, 2007Publication date: September 25, 2008Inventors: Eric R. Blomiley, Joel A. Drewes, D.V. Nirmal Ramaswamy