Abstract: Magneto-resistive random access memory elements include a ferromagnetic layer having uniaxial anisotropy provided by elongate structures formed in the ferromagnetic film. The magnetic dipole aligns with the long axis of each structure. The structures can be formed in a variety of ways. For example, the ferromagnetic film can be applied to a seed layer having a textured surface. Alternatively, the ferromagnetic film can be stressed to generate the textured structure. Chemical mechanical polishing also can be used to generated the structures.

Abstract: The present invention provides atomic layer deposition systems and methods that include at least one compound of the formula (Formula I): Ta(NR1)(NR2R3)3, wherein each R1, R2, and R3 is independently hydrogen or an organic group, with the proviso that at least one of R1, R2, and R3 is a silicon-containing organic group. Such systems and methods can be useful for depositing tantalum silicon nitride layers on substrates.

Abstract: The present invention provides a method of fabricating a portion of a memory cell, the method comprising providing a first conductor in a trench which is provided in an insulating layer and flattening an upper surface of the insulating layer and the first conductor, forming a material layer over the flattened upper surface of the insulating layer and the first conductor and flattening an upper portion of the material layer while leaving intact a lower portion of the material layer over the insulating layer and the first conductor.

Abstract: Some embodiments include methods of titanium deposition in which a silicon-containing surface and an electrically insulative surface are both exposed to titanium-containing material, and in which such exposure forms titanium suicide from the silicon-containing surface while not depositing titanium onto the electrically insulative surface. The embodiments may include atomic layer deposition processes, and may include a hydrogen pre-treatment of the silicon-containing surfaces to activate the surfaces for reaction with the titanium-containing material. Some embodiments include methods of titanium deposition in which a semiconductor material surface and an electrically insulative surface are both exposed to titanium-containing material, and in which a titanium-containing film is uniformly deposited across both surfaces.

Abstract: The invention includes semiconductor processing methods in which openings are formed to extend into a semiconductor substrate, and the substrate is then annealed around the openings to form cavities. The substrate is etched to expose the cavities, and the cavities are substantially filled with insulative material. The semiconductor substrate having the filled cavities therein can be utilized as a semiconductor-on-insulator-type structure, and transistor devices can be formed to be supported by the semiconductor material and to be over the cavities. In some aspects, the transistor devices have channel regions over the filled cavities, and in other aspects the transistor devices have source/drain regions over the filled cavities. The transistor devices can be incorporated into dynamic random access memory, and can be utilized in electronic systems.

Abstract: A passivated magneto-resistive bit structure is disclosed in which surfaces subjects to oxidation or corrosion are protected. In one embodiment, a bit structure is encapsulated by means of an etch stop barrier material. In another embodiment an etch stop barrier material protects the top of a bit structure and dielectric spacers protect the side walls.

Abstract: An enhanced giant magnetoresistive device, and a method of manufacturing the same. The enhanced giant magnetoresistive (GMR) device includes a substrate over which is formed a seed layer. A buffer-oxide layer is formed over the seed layer. Formed over the buffer-oxide layer is a GMR stack. The GMR stack is formed as a three layer sandwich in which the two outside layers are fabricated from ferromagnetic materials, and the inner layer or spacer layer is formed from non-magnetic, conducting materials. The GMR stack may also take the form of spin valves, and/or other GMR stacks. The buffer-oxide layer may be various thicknesses and provide desirable texturing or non-waviness, both of which may allow for a thin spacer layer. Further, the buffer-oxide layer may be configured to prevent Néel-type-orange-peel coupling from dominating RKKY coupling in the GMR device, which may allow for a thin spacer layer.

Abstract: The present invention provides a method of fabricating a portion of a memory cell, the method comprising providing a first conductor in a trench which is provided in an insulating layer and flattening an upper surface of the insulating layer and the first conductor, forming a material layer over the flattened upper surface of the insulating layer and the first conductor and flattening an upper portion of the material layer while leaving intact a lower portion of the material layer over the insulating layer and the first conductor.

Abstract: A multilayer dielectric tunnel barrier structure and a method for its formation which may be used in non-volatile magnetic memory elements comprises an ALD deposited first nitride junction layer formed from one or more nitride monolayers i.e., AlN, an ALD deposited intermediate oxide junction layer formed from one or more oxide monolayers i.e., AlxOy, disposed on the first nitride junction layer, and an ALD deposited second nitride junction layer formed from one or more nitride monolayers i.e., AlN, disposed on top of the intermediate oxide junction layer. The multilayer tunnel barrier structure is formed by using atomic layer deposition techniques to provide improved tunneling characteristics while also providing anatomically smooth barrier interfaces.

Abstract: The invention includes methods of forming titanium-containing materials, such as, for example, titanium silicide. The invention can use alternating cycles of titanium halide precursor and one or more reductants to form the titanium-containing material. For instance, the invention can utilize alternating cycles of titanium tetrachloride and activated hydrogen to form titanium silicide on a surface of a silicon-containing substrate.

Abstract: The present invention provides a method of fabricating a portion of a memory cell, the method comprising providing a first conductor in a trench which is provided in an insulating layer and flattening an upper surface of the insulating layer and the first conductor, forming a material layer over the flattened upper surface of the insulating layer and the first conductor and flattening an upper portion of the material layer while leaving intact a lower portion of the material layer over the insulating layer and the first conductor.

Abstract: A method and apparatus are disclosed for inhibiting diffusion of mobile atoms from an antiferromagnetic layer toward a tunnel oxide layer and through a ferromagnetic layer which is pinned by the antiferromagnetic layer. Diffusion of the mobile atoms is inhibited by an oxide layer provided between the anti-ferromagnetic layer and the ferromagnetic layer. Alternatively, the ferromagnetic layer can have boron atoms located on or in the layer to fill interstices.

Abstract: The invention includes methods of forming titanium-containing materials, such as, for example, titanium silicide. The invention can use alternating cycles of titanium halide precursor and one or more reductants to form the titanium-containing material. For instance, the invention can utilize alternating cycles of titanium tetrachloride and activated hydrogen to form titanium silicide on a surface of a silicon-containing substrate.

Abstract: An MRAM device includes an array of magnetic memory cells having an upper conductive layer and a lower conductive layer separated by a barrier layer. To reduce the likelihood of electrical shorting across the barrier layers of the memory cells, spacers can be formed around the upper conductive layer and, after the layers of the magnetic memory cells have been etched, the memory cells can be oxidized to transform any conductive particles that are deposited along the sidewalls of the memory cells as byproducts of the etching process into nonconductive particles. Alternatively, the lower conductive layer can be repeatedly subjected to partial oxidation and partial etching steps such that only nonconductive particles can be thrown up along the sidewalls of the memory cells as byproducts of the etching process.

Abstract: The present invention is generally directed to a method of forming a pseudo SOI substrate and semiconductor devices. In one illustrative embodiment, the method comprises forming a plurality of trenches in a semiconducting substrate comprised of silicon, each of the trenches having a depth, forming a layer of insulating material within each of the plurality of trenches, the layer of insulating material having a thickness that is less than the depth of the trenches, and performing an anneal process on the substrate in a hydrogen environment to cause the silicon substrate material to merge above the layer of insulating material within the plurality of trenches to thereby define a pseudo SOI substrate.

Abstract: A common pinned layer is shared by multiple memory cells in an MRAM device. The common pinned layer includes a plurality of domain wall traps that prevent the formation of domain walls within a region of the common pinned layer corresponding to a given memory cell. Therefore, the memory cells can advantageously be formed such that the domain walls, to the extent they exist, fall between (rather than within) the memory cells, thereby improving the performance of the MRAM device.

Abstract: A pseudo-spin valve for memory applications, such as magnetoresistive random access memory (MRAM), and methods for fabricating the same, are disclosed. Advantageously, memory devices with the advantageous pseudo-spin valve configuration can be fabricated without cobalt-iron and without anti-ferromagnetic layers, thereby promoting switching repeatability.

Abstract: The invention includes a method of forming a semiconductor construction, such as an MRAM construction. A block is formed over a semiconductor substrate. First and second layers are formed over the block, and over a region of the substrate proximate the block. The first and second layers are removed from over the block while leaving portions of the first and second layers over the region proximate the block. At least some of the first layer is removed from under the second layer to form a channel over the region proximate the block. A material, such as a soft magnetic material, is provided within the channel. The invention also includes semiconductor constructions.

Abstract: The present invention is generally directed to a method of forming a pseudo SOI substrate and semiconductor devices. In one illustrative embodiment, the method comprises forming a plurality of trenches in a semiconducting substrate comprised of silicon, each of the trenches having a depth, forming a layer of insulating material within each of the plurality of trenches, the layer of insulating material having a thickness that is less than the depth of the trenches, and performing an anneal process on the substrate in a hydrogen environment to cause the silicon substrate material to merge above the layer of insulating material within the plurality of trenches to thereby define a pseudo SOI substrate.

Abstract: A common pinned layer is shared by multiple memory cells in an MRAM device. The common pinned layer includes a plurality of domain wall traps that prevent the formation of domain walls within a region of the common pinned layer corresponding to a given memory cell. Therefore, the memory cells can advantageously be formed such that the domain walls, to the extent they exist, fall between (rather than within) the memory cells, thereby improving the performance of the MRAM device.