Patents by Inventor Joel A. Drewes

Joel A. Drewes has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20050237790
    Abstract: The invention relates to improving the switching reliability of a magnetic memory cell in a magnetic random access memory (MRAM). Embodiments of the invention add an antiferromagnet to a magnetic memory cell. An antiferromagnetic layer can be formed adjacent to a soft layer in the MRAM on a side of the soft layer that is opposite to a hard layer of the MRAM. One embodiment further includes an additional interlayer of non-antiferromagnetic material between the antiferromagnetic layer and the soft layer.
    Type: Application
    Filed: April 11, 2005
    Publication date: October 27, 2005
    Inventors: Romney Katti, Joel Drewes, Timothy Vogt
  • Publication number: 20050223993
    Abstract: The invention includes deposition apparatuses having reflectors with rugged reflective surfaces configured to disperse light reflected therefrom, and/or having dispersers between lamps and a substrate. The invention also includes optical methods for utilization within a deposition apparatus for assessing the alignment of a substrate within the apparatus and/or for assessing the thickness of a layer of material deposited within the apparatus.
    Type: Application
    Filed: April 8, 2004
    Publication date: October 13, 2005
    Inventors: Eric Blomiley, Nirmal Ramaswamy, Ross Dando, Joel Drewes
  • Publication number: 20050223985
    Abstract: The invention includes deposition apparatuses configured to monitor the temperature of a semiconductor wafer substrate by utilizing conduits which channel radiation from the substrate to a detector/signal processor system. In particular aspects, the temperature of the substrate can be measured while the substrate is spinning within a reaction chamber. The invention also includes deposition apparatuses in which flow of mixed gases is controlled by mass flow controllers provided downstream of the location where the gases are mixed and/or where flow of gases is measured with mass flow measurement devices provided downstream of the location where the gases are mixed. Additionally, the invention encompasses deposition apparatuses in which mass flow controllers and/or mass flow measurement devices are provided upstream of a header which splits a source gas into multiple paths directed toward multiple different reaction chambers.
    Type: Application
    Filed: April 8, 2004
    Publication date: October 13, 2005
    Inventors: Eric Blomiley, Nirmal Ramaswamy, Ross Dando, Joel Drewes, Alan Colwell, Eduardo Tovar
  • Publication number: 20050226040
    Abstract: A magneto-resistive memory comprising magneto-resistive memory cells is disclosed, comprising a pinned magnetic layer and a free magnetic layer. The two magnetic layers are formed having widened regions at the ends of the layers. As such, the shape made out by the magneto-resisitve memory, from a top-view perspective, is wide at the ends and narrower at the mid-, forming an I shape in one preferred embodiment. The end portions of the free magnetic layer are allowed to magnetically couple to the end portions of the pinned magnetic layer such that magnetic coupling is shifted to these widened regions and coupling in the mid-portion between the widened regions is minimized. Thus, the influence of the pinned magnetic layer on the magnetization orientation of the mid-portion of the free magnetic layer is substantially eliminated, allowing for increased predictability in switching behavior and increased write selectivity of memory cells.
    Type: Application
    Filed: June 7, 2005
    Publication date: October 13, 2005
    Inventors: Theodore Zhu, Yong Lu, Anthony Arrott, Joel Drewes
  • Publication number: 20050223994
    Abstract: In one implementation, a substrate susceptor for receiving a semiconductor substrate for selective epitaxial silicon-comprising depositing thereon, where the depositing comprises measuring emissivity of the susceptor from at least one susceptor location in a non-contacting manner, includes a body having a front substrate receiving side, a back side, and a peripheral edge. At least one susceptor location from which emissivity is to be measured is received on at least one of the front substrate receiving side, the back side, and the edge. Such at least one susceptor location comprises an outermost surface comprising a material upon which selective epitaxial silicon will not deposit upon during selective epitaxial silicon depositing on a semiconductor substrate received by the susceptor for at least an initial thickness of epitaxial silicon depositing on said substrate. Other aspects and implementations are contemplated.
    Type: Application
    Filed: April 8, 2004
    Publication date: October 13, 2005
    Inventors: Eric Blomiley, Nirmal Ramaswamy, Ross Dando, Joel Drewes, Danny Dynka
  • Publication number: 20050217585
    Abstract: This invention includes substrate susceptors which receive substrates to be deposited upon. In one implementation, a substrate susceptor includes a body having a substrate receiving side. The substrate receiving side has a face having a substrate receiving recess formed therein. The recess has an outer peripheral sidewall. At least three projections extend outwardly from a portion of the face. The projections respectively comprise a radially inner sidewall which extends outwardly from the recess outer peripheral sidewall to a projection upper surface. Other aspects and implementations are contemplated.
    Type: Application
    Filed: April 1, 2004
    Publication date: October 6, 2005
    Inventors: Eric Blomiley, Joel Drewes, Nirmal Ramaswamy, Ross Dando
  • Publication number: 20050217569
    Abstract: The invention includes methods of depositing elemental silicon-comprising materials over a semiconductor substrate, and methods of cleaning an internal wall of a chamber. In one implementation, a semiconductor substrate is positioned within a chamber for deposition. The chamber comprises an infrared radiation transparent wall. An elemental silicon-comprising material is deposited on the semiconductor substrate. During such depositing, a deposit is formed on the infrared radiation transparent wall within the chamber. After such depositing, a plasma is generated within the chamber with a cleaning gas from at least one plasma generating electrode received external of the chamber proximate the infrared radiation transparent wall effective to remove at least some of the deposit from the infrared radiation transparent wall within the chamber. Other aspects and implementations are contemplated.
    Type: Application
    Filed: April 1, 2004
    Publication date: October 6, 2005
    Inventors: Nirmal Ramaswamy, Eric Blomiley, Joel Drewes
  • Publication number: 20050207217
    Abstract: The present invention provides a method of fabricating a portion of a memory cell, the method comprising providing a first conductor in a trench which is provided in an insulating layer and flattening an upper surface of the insulating layer and the first conductor, forming a material layer over the flattened upper surface of the insulating layer and the first conductor and flattening an upper portion of the material layer while leaving intact a lower portion of the material layer over the insulating layer and the first conductor.
    Type: Application
    Filed: May 23, 2005
    Publication date: September 22, 2005
    Inventors: Donald Yates, Joel Drewes
  • Patent number: 6933112
    Abstract: An optical assay device for the detection of an analyte of interest in a sample comprising a support containing channels, an optically functional layer positioned on the support such that the optically functional layer and the support allow for laminar flow of the sample through layers of the device, an attachment layer positioned on the optically functional layer, and an analyte specific receptive layer positioned on the attachment layer.
    Type: Grant
    Filed: September 29, 2000
    Date of Patent: August 23, 2005
    Assignee: Thermo Biostar Inc.
    Inventors: Joel A. Drewes, Gregory R. Bogart, Jeffrey B. Etter, Jeffrey W. Steaffens, Rachel M. Ostroff, Mark Crosby
  • Publication number: 20050173698
    Abstract: A multilayer dielectric tunnel barrier structure and a method for its formation which may be used in non-volatile magnetic memory elements comprises an ALD deposited first nitride junction layer formed from one or more nitride monolayers i.e., AlN, an ALD deposited intermediate oxide junction layer formed from one or more oxide monolayers i.e., AlxOy, disposed on the first nitride junction layer, and an ALD deposited second nitride junction layer formed from one or more nitride monolayers i.e., AlN, disposed on top of the intermediate oxide junction layer. The multilayer tunnel barrier structure is formed by using atomic layer deposition techniques to provide improved tunneling characteristics while also providing anatomically smooth barrier interfaces.
    Type: Application
    Filed: April 15, 2005
    Publication date: August 11, 2005
    Inventor: Joel Drewes
  • Patent number: 6927466
    Abstract: The invention provides an magnetic memory element having improved switching properties and zero field offset, and a manufacturing method thereof. The element comprises a first magnetic layer overlying a conductive layer and a nonmagnetic layer overlying the first magnetic layer. Next, a second magnetic layer is provided over the nonmagnetic layer, wherein the second magnetic layer comprises an antiferromagnetic layer overlying a ferromagnetic free layer to apply a small bias to the ferromagnetic free layer. Then, the first magnetic, nonmagnetic and second magnetic layers are patterned to form the memory element.
    Type: Grant
    Filed: August 5, 2003
    Date of Patent: August 9, 2005
    Assignee: Micron Technology, Inc.
    Inventor: Joel A. Drewes
  • Publication number: 20050158952
    Abstract: A MRAM cell structure is disclosed as containing an additional ferromagnetic layer and coupling layer between the third ferromagnetic layer and the anti-ferromagnetic layer. The additional ferromagnetic layer affects the demagnetization field to which the free layer is exposed, thereby reducing any bias introduced to the free layer. Further, by adjusting the thickness of the additional ferromagnetic layer, the effects of Neel coupling on the free layer are reduced.
    Type: Application
    Filed: February 7, 2005
    Publication date: July 21, 2005
    Inventor: Joel Drewes
  • Patent number: 6906950
    Abstract: A magneto-resistive memory comprising magneto-resistive memory cells is disclosed, comprising a pinned magnetic layer and a free magnetic layer. The two magnetic layers are formed having widened regions at the ends of the layers. As such, the shape made out by the magneto-resisitve memory, from a top-view perspective, is wide at the ends and narrower at the mid-, forming an I shape in one preferred embodiment. The end portions of the free magnetic layer are allowed to magnetically couple to the end portions of the pinned magnetic layer such that magnetic coupling is shifted to these widened regions and coupling in the mid-portion between the widened regions is minimized. Thus, the influence of the pinned magnetic layer on the magnetization orientation of the mid-portion of the free magnetic layer is substantially eliminated, allowing for increased predictability in switching behavior and increased write selectivity of memory cells.
    Type: Grant
    Filed: July 7, 2004
    Date of Patent: June 14, 2005
    Assignee: Micron Technology, Inc.
    Inventors: Theodore Zhu, Yong Lu, Anthony Arrott, Joel Drewes
  • Patent number: 6902940
    Abstract: A magnetic memory element has reduced demagnetization coupling between a pinned layer and a free layer. The element includes a pinned ferromagnetic layer and a free ferromagnetic layer which are separated by a barrier layer. The pinned layer is pinned by an antiferromagnetic layer. An offset ferromagnetic layer is provided on a side of the antiferromagnetic layer opposite the pinned ferromagnetic layer to reduce demagnetization coupling between the free ferromagnetic layer and the pinned ferromagnetic layer.
    Type: Grant
    Filed: August 21, 2003
    Date of Patent: June 7, 2005
    Assignee: Micron Technology, Inc.
    Inventor: Joel A. Drewes
  • Patent number: 6903399
    Abstract: The invention relates to improving the switching reliability of a magnetic memory cell in a magnetic random access memory (MRAM). Embodiments of the invention add an antiferromagnet to a magnetic memory cell. An antiferromagnetic layer can be formed adjacent to a soft layer in the MRAM on a side of the soft layer that is opposite to a hard layer of the MRAM. One embodiment further includes an additional interlayer of non-antiferromagnetic material between the antiferromagnetic layer and the soft layer.
    Type: Grant
    Filed: January 16, 2004
    Date of Patent: June 7, 2005
    Assignee: Micron Technology, Inc.
    Inventors: Romney R. Katti, Joel A. Drewes, Timothy J. Vogt
  • Patent number: 6900489
    Abstract: A magnetic memory element has reduced Néel coupling between a pinned layer and a free layer. The magnetic memory element includes a first pinned ferromagnet and a free ferromagnet which are separated by a barrier layer. The magnetic field direction of the pinned layer is fixed, for example, by an antiferromagnetic exchange layer. An additional ferromagnetic layer, provided in coupling relationship with the first pinned ferromagnet, offsets Néel coupling between the free ferromagnetic layer and the first pinned ferromagnet.
    Type: Grant
    Filed: April 29, 2003
    Date of Patent: May 31, 2005
    Assignee: Micron Technology, Inc.
    Inventor: Joel A. Drewes
  • Patent number: 6900455
    Abstract: A multilayer dielectric tunnel barrier structure and a method for its formation which may be used in non-volatile magnetic memory elements comprises an ALD deposited first nitride junction layer formed from one or more nitride monolayers i.e., AlN, an ALD deposited intermediate oxide junction layer formed from one or more oxide monolayers i.e., AlxOy, disposed on the first nitride junction layer, and an ALD deposited second nitride junction layer formed from one or more nitride monolayers i.e., AlN, disposed on top of the intermediate oxide junction layer. The multilayer tunnel barrier structure is formed by using atomic layer deposition techniques to provide improved tunneling characteristics while also providing anatomically smooth barrier interfaces.
    Type: Grant
    Filed: October 1, 2003
    Date of Patent: May 31, 2005
    Assignee: Micron Technology, Inc.
    Inventor: Joel A. Drewes
  • Publication number: 20050099844
    Abstract: The invention relates to methods and apparatus that allow data to be stored in a magnetic memory cell, such as a giant magneto-resistance (GMR) cell, of a magnetoresistive random access memory (MRAM). Embodiments of the invention advantageously wind a word line around a magnetic memory cell to increase the magnetic field induced by the word line. The word line can be formed by connecting a segment in a first layer to a segment in a second layer with the memory cell disposed between the first layer and the second layer. Advantageously, embodiments of the invention can include relatively narrow magnetic memory cells, and/or bit lines, have relatively high write selectivity, and can use relatively low word currents to store data. In one MRAM, current is passed through a word line by allowing current to flow through a corresponding word row line and a corresponding word column line.
    Type: Application
    Filed: December 13, 2004
    Publication date: May 12, 2005
    Applicant: Micron Technology, Inc.
    Inventors: William Witcraft, Hongyue Liu, Joel Drewes
  • Patent number: 6885073
    Abstract: A MRAM cell structure is disclosed as containing an additional ferromagnetic layer and coupling layer between the third ferromagnetic layer and the anti-ferromagnetic layer. The additional ferromagnetic layer affects the demagnetization field to which the free layer is exposed, thereby reducing any bias introduced to the free layer. Further, by adjusting the thickness of the additional ferromagnetic layer, the effects of Neel coupling on the free layer are reduced.
    Type: Grant
    Filed: April 2, 2003
    Date of Patent: April 26, 2005
    Assignee: Micron Technology, Inc.
    Inventor: Joel A. Drewes
  • Patent number: 6881993
    Abstract: A method and apparatus are disclosed for inhibiting diffusion of mobile atoms from an antiferromagnetic layer toward a tunnel oxide layer and through a ferromagnetic layer which is pinned by the antiferromagnetic layer. Diffusion of the mobile atoms is inhibited by an oxide layer provided between the anti-ferromagnetic layer and the ferromagnetic layer. Alternatively, the ferromagnetic layer can have boron atoms located on or in the layer to fill interstices.
    Type: Grant
    Filed: August 28, 2002
    Date of Patent: April 19, 2005
    Assignee: Micron Technology, Inc.
    Inventors: Joel A. Drewes, Terry Gafron