Patents by Inventor Joel A. Drewes

Joel A. Drewes has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20050079638
    Abstract: An MRAM device includes an array of magnetic memory cells having an upper conductive layer and a lower conductive layer separated by a barrier layer. To reduce the likelihood of electrical shorting across the barrier layers of the memory cells, spacers can be formed around the upper conductive layer and, after the layers of the magnetic memory cells have been etched, the memory cells can be oxidized to transform any conductive particles that are deposited along the sidewalls of the memory cells as byproducts of the etching process into nonconductive particles. Alternatively, the lower conductive layer can be repeatedly subjected to partial oxidation and partial etching steps such that only nonconductive particles can be thrown up along the sidewalls of the memory cells as byproducts of the etching process.
    Type: Application
    Filed: October 14, 2003
    Publication date: April 14, 2005
    Inventors: Joel Drewes, James Deak
  • Patent number: 6870714
    Abstract: A metal manganese oxide buffer layer is used to seed a barrier layer in a magnetic tunnel junction memory element having pinned and free magnetic layers. An alumina tunnel barrier layer is formed on the oxidized metal manganese layer with the barrier layer and oxidized metal manganese layer being between the pinned or free ferromagnetic layers.
    Type: Grant
    Filed: March 12, 2003
    Date of Patent: March 22, 2005
    Assignee: Micron Technology, Inc.
    Inventor: Joel A. Drewes
  • Publication number: 20050047263
    Abstract: A method and apparatus are disclosed for inhibiting diffusion of mobile atoms from an antiferromagnetic layer toward a tunnel oxide layer and through a ferromagnetic layer which is pinned by the antiferromagnetic layer. Diffusion of the mobile atoms is inhibited by an oxide layer provided between the anti-ferromagnetic layer and the ferromagnetic layer. Alternatively, the ferromagnetic layer can have boron atoms located on or in the layer to fill interstices.
    Type: Application
    Filed: October 14, 2004
    Publication date: March 3, 2005
    Inventors: Joel Drewes, Terry Gafron
  • Publication number: 20050041463
    Abstract: A common pinned layer is shared by multiple memory cells in an MRAM device. The common pinned layer includes a plurality of domain wall traps that prevent the formation of domain walls within a region of the common pinned layer corresponding to a given memory cell. Therefore, the memory cells can advantageously be formed such that the domain walls, to the extent they exist, fall between (rather than within) the memory cells, thereby improving the performance of the MRAM device.
    Type: Application
    Filed: August 22, 2003
    Publication date: February 24, 2005
    Inventor: Joel Drewes
  • Patent number: 6852550
    Abstract: This invention relates to MRAM technology and new MRAM memory element designs. Specifically, this invention relates to the use of ferromagnetic layers of different sizes in an MRAM element. This reduces magnetic coupling between a pinned layer and a sense layer and provides a more effective memory element.
    Type: Grant
    Filed: July 14, 2003
    Date of Patent: February 8, 2005
    Assignee: Micron Technology, Inc.
    Inventors: Mark E. Tuttle, Joel A. Drewes
  • Patent number: 6849464
    Abstract: A multilayer dielectric tunnel barrier structure and a method for its formation which may be used in non-volatile magnetic memory elements comprises an ALD deposited first nitride junction layer formed from one or more nitride monolayers i.e., AlN, an ALD deposited intermediate oxide junction layer formed from one or more oxide monolayers i.e., AlxOy, disposed on the first nitride junction layer, and an ALD deposited second nitride junction layer formed from one or more nitride monolayers i.e., AlN, disposed on top of the intermediate oxide junction layer. The multilayer tunnel barrier structure is formed by using atomic layer deposition techniques to provide improved tunneling characteristics while also providing anatomically smooth barrier interfaces.
    Type: Grant
    Filed: June 10, 2002
    Date of Patent: February 1, 2005
    Assignee: Micron Technology, Inc.
    Inventor: Joel A. Drewes
  • Publication number: 20050003561
    Abstract: Magneto-resistive random access memory elements include a ferromagnetic layer having uniaxial anisotropy provided by elongate structures formed in the ferromagnetic film. The magnetic dipole aligns with the long axis of each structure. The structures can be formed in a variety of ways. For example, the ferromagnetic film can be applied to a seed layer having a textured surface. Alternatively, the ferromagnetic film can be stressed to generate the textured structure. Chemical mechanical polishing also can be used to generated the structures.
    Type: Application
    Filed: July 2, 2003
    Publication date: January 6, 2005
    Inventor: Joel Drewes
  • Publication number: 20040240264
    Abstract: A magneto-resistive memory comprising magneto-resistive memory cells is disclosed, comprising a pinned magnetic layer and a free magnetic layer. The two magnetic layers are formed having widened regions at the ends of the layers. As such, the shape made out by the magneto-resisitve memory, from a top-view perspective, is wide at the ends and narrower at the mid-, forming an I shape in one preferred embodiment. The end portions of the free magnetic layer are allowed to magnetically couple to the end portions of the pinned magnetic layer such that magnetic coupling is shifted to these widened regions and coupling in the mid-portion between the widened regions is minimized. Thus, the influence of the pinned magnetic layer on the magnetization orientation of the mid-portion of the free magnetic layer is substantially eliminated, allowing for increased predictability in switching behavior and increased write selectivity of memory cells.
    Type: Application
    Filed: July 7, 2004
    Publication date: December 2, 2004
    Inventors: Theodore Zhu, Yong Lu, Anthony Arrott, Joel Drewes
  • Publication number: 20040234815
    Abstract: A metal manganese oxide buffer layer is used to seed a barrier layer in a magnetic tunnel junction memory element having pinned and free magnetic layers. An alumina tunnel barrier layer is formed on the oxidized metal manganese layer with the barrier layer and oxidized metal manganese layer being between the pinned or free ferromagnetic layers.
    Type: Application
    Filed: June 29, 2004
    Publication date: November 25, 2004
    Inventor: Joel A. Drewes
  • Publication number: 20040227244
    Abstract: A passivated magneto-resistive bit structure is disclosed in which surfaces subjects to oxidation or corrosion are protected. In one embodiment, a bit structure is encapsulated by means of an etch stop barrier material. In another embodiment an etch stop barrier material protects the top of a bit structure and dielectric spacers protect the side walls.
    Type: Application
    Filed: June 21, 2004
    Publication date: November 18, 2004
    Applicant: Micron Technology, Inc.
    Inventors: Harry Liu, Lonny Berg, William L. Larson, Shaoping Li, Theodore Zhu, Joel Drewes
  • Publication number: 20040217403
    Abstract: A magnetic memory element has reduced Néel coupling between a pinned layer and a free layer. The magnetic memory element includes a first pinned ferromagnet and a free ferromagnet which are separated by a barrier layer. The magnetic field direction of the pinned layer is fixed, for example, by an antiferromagnetic exchange layer. An additional ferromagnetic layer, provided in coupling relationship with the first pinned ferromagnet, offsets Néel coupling between the free ferromagnetic layer and the first pinned ferromagnet.
    Type: Application
    Filed: May 6, 2004
    Publication date: November 4, 2004
    Inventor: Joel A. Drewes
  • Publication number: 20040217399
    Abstract: A magnetic memory element has reduced Néel coupling between a pinned layer and a free layer. The magnetic memory element includes a first pinned ferromagnet and a free ferromagnet which are separated by a barrier layer. The magnetic field direction of the pinned layer is fixed, for example, by an antiferromagnetic exchange layer. An additional ferromagnetic layer, provided in coupling relationship with the first pinned ferromagnet, offsets Néel coupling between the free ferromagnetic layer and the first pinned ferromagnet.
    Type: Application
    Filed: April 29, 2003
    Publication date: November 4, 2004
    Inventor: Joel A. Drewes
  • Patent number: 6806546
    Abstract: A passivated magneto-resistive bit structure is disclosed in which surfaces subjects to oxidation or corrosion are protected. In one embodiment, a bit structure is encapsulated by means of an etch stop barrier material. In another embodiment an etch stop barrier material protects the top of a bit structure and dielectric spacers protect the side walls.
    Type: Grant
    Filed: February 14, 2002
    Date of Patent: October 19, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Harry Liu, Lonny Berg, William L Larson, Shaoping Li, Theodore Zhu, Joel Drewes
  • Publication number: 20040202018
    Abstract: The invention relates to methods and apparatus that allow data to be stored in a magnetic memory cell, such as a giant magneto-resistance (GMR) cell, of a magnetoresistive random access memory (MRAM). Embodiments of the invention advantageously wind a word line around a magnetic memory cell to increase the magnetic field induced by the word line. The word line can be formed by connecting a segment in a first layer to a segment in a second layer with the memory cell disposed between the first layer and the second layer. Advantageously, embodiments of the invention can include relatively narrow magnetic memory cells, and/or bit lines, have relatively high write selectivity, and can use relatively low word currents to store data. In one MRAM, current is passed through a word line by allowing current to flow through a corresponding word row line and a corresponding word column line.
    Type: Application
    Filed: April 30, 2004
    Publication date: October 14, 2004
    Applicant: Micron Technology, Inc.
    Inventors: William Frank Witcraft, Hongyue Liu, Joel A. Drewes
  • Publication number: 20040195639
    Abstract: A MRAM cell structure is disclosed as containing an additional ferromagnetic layer and coupling layer between the third ferromagnetic layer and the anti-ferromagnetic layer. The additional ferromagnetic layer affects the demagnetization field to which the free layer is exposed, thereby reducing any bias introduced to the free layer. Further, by adjusting the thickness of the additional ferromagnetic layer, the effects of Neel coupling on the free layer are reduced.
    Type: Application
    Filed: April 2, 2003
    Publication date: October 7, 2004
    Inventor: Joel A. Drewes
  • Publication number: 20040183099
    Abstract: The invention relates to improving the switching reliability of a magnetic memory cell in a magnetic random access memory (MRAM). Embodiments of the invention add an antiferromagnet to a magnetic memory cell. An antiferromagnetic layer can be formed adjacent to a soft layer in the MRAM on a side of the soft layer that is opposite to a hard layer of the MRAM. One embodiment further includes an additional interlayer of non-antiferromagnetic material between the antiferromagnetic layer and the soft layer.
    Type: Application
    Filed: January 16, 2004
    Publication date: September 23, 2004
    Inventors: Romney R. Katti, Joel A. Drewes, Timothy J. Vogt
  • Publication number: 20040180237
    Abstract: A metal manganese oxide buffer layer is used to seed a barrier layer in a magnetic tunnel junction memory element having pinned and free magnetic layers. An alumina tunnel barrier layer is formed on the oxidized metal manganese layer with the barrier layer and oxidized metal manganese layer being between the pinned or free ferromagnetic layers.
    Type: Application
    Filed: March 12, 2003
    Publication date: September 16, 2004
    Inventor: Joel A. Drewes
  • Patent number: 6781173
    Abstract: This invention relates to MRAM technology and new MRAM memory element designs. Specifically, this invention relates to the use of ferromagnetic layers of different sizes in an MRAM element. This reduces magnetic coupling between a pinned layer and a sense layer and provides a more effective memory element.
    Type: Grant
    Filed: August 29, 2002
    Date of Patent: August 24, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Mark E. Tuttle, Joel A. Drewes
  • Publication number: 20040150059
    Abstract: The invention provides an magnetic memory element having improved switching properties and zero field offset, and a manufacturing method thereof. The element comprises a first magnetic layer overlying a conductive layer and a nonmagnetic layer overlying the first magnetic layer. Next, a second magnetic layer is provided over the nonmagnetic layer, wherein the second magnetic layer comprises an antiferromagnetic layer overlying a ferromagnetic free layer to apply a small bias to the ferromagnetic free layer. Then, the first magnetic, nonmagnetic and second magnetic layers are patterned to form the memory element.
    Type: Application
    Filed: February 2, 2004
    Publication date: August 5, 2004
    Inventor: Joel A. Drewes
  • Publication number: 20040145943
    Abstract: A magneto-resistive memory comprising magneto-resistive memory cells is disclosed, comprising a pinned magnetic layer and a free magnetic layer. The two magnetic layers are formed having widened regions at the ends of the layers. As such, the shape made out by the magneto-resisitve memory, from a top-view perspective, is wide at the ends and narrower at the mid-, forming an I shape in one preferred embodiment. The end portions of the free magnetic layer are allowed to magnetically couple to the end portions of the pinned magnetic layer such that magnetic coupling is shifted to these widened regions and coupling in the mid-portion between the widened regions is minimized. Thus, the influence of the pinned magnetic layer on the magnetization orientation of the mid-portion of the free magnetic layer is substantially eliminated, allowing for increased predictability in switching behavior and increased write selectivity of memory cells.
    Type: Application
    Filed: January 29, 2003
    Publication date: July 29, 2004
    Inventors: Theodore Zhu, Yong Lu, Anthony Arrott, Joel Drewes