Patents by Inventor Joerg Appenzeller
Joerg Appenzeller has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230290891Abstract: A cross-coupled tunnel diode (XTD) device with large peak-to-valley current ratio (PVCR) is disclosed. A memory cell circuit comprising XTD devices is also disclosed. The XTD device includes an N-type semiconductor coupled to a P-type semiconductor. A first gate is disposed on the N-type semiconductor and a second gate is disposed on the P-type semiconductor. The first gate is coupled to the output terminal, which is further coupled to the P-type semiconductor. The second gate is coupled to the input terminal, which is coupled to the N-type semiconductor. As reverse bias voltage increases, band-to-band tunneling from valence band to conduction band initially generates increasing current, but the rising bias voltage closes the band to band tunneling window, creating a gated negative differential resistance behavior. The current drops off as the bias voltage further increases. In some examples, a ratio of peak-to-valley current ratio may exceed 103 or 105.Type: ApplicationFiled: March 9, 2022Publication date: September 14, 2023Inventors: Peng Wu, Joerg Appenzeller
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Publication number: 20200388754Abstract: A method of switching a phase-change device (Device), including changing phase of the Device from a semiconducting 2H phase to a new 2Hd phase with a higher conductivity, the Device having an active material with a thickness including a phase transition material to thereby transition the Device from a high resistive state (HRS) to a low resistive state (LRS) by application of a set voltage and further to return the Device from the LRS back to the HRS by application of a reset voltage.Type: ApplicationFiled: August 25, 2020Publication date: December 10, 2020Applicants: Purdue Research Foundation, Government of the U.S. as Represented by Secretary of CommerceInventors: Joerg Appenzeller, Feng Zhang, Yuqi Zhu, Albert V. Davydov, Sergiy Krylyuk, Huairuo Zhang, Leonid A. Bendersky
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Patent number: 10756263Abstract: A method of switching a phase-change device (Device), including changing phase of the Device from a semiconducting 2H phase to a new 2Hd phase with a higher conductivity, the Device having an active material with a thickness including a phase transition material to thereby transition the Device from a high resistive state (HRS) to a low resistive state (LRS) by application of a set voltage and further to return the Device from the LRS back to the HRS by application of a reset voltage.Type: GrantFiled: August 23, 2018Date of Patent: August 25, 2020Assignee: Purdue Research FoundationInventors: Joerg Appenzeller, Feng Zhang, Yuqi Zhu, Albert V. Davydov, Sergiy Krylyuk, Huairuo Zhang, Leonid A. Bendersky
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Patent number: 10505109Abstract: A resistive random access memory (Device) is disclosed. The Device includes a substrate, a first electrode formed atop the substrate, a tunneling barrier layer formed atop the first electrode, an active material formed atop the tunneling barrier layer, an isolation layer formed atop the active material, and a second electrode formed atop the isolation layer, the first electrode and the second electrode provide electrical connectivity to external components, where the active material is a phase change material which undergoes phase transition in the presence of an electric field, Joule heating, or a combination thereof.Type: GrantFiled: May 23, 2018Date of Patent: December 10, 2019Assignee: Purdue Research FoundationInventors: Joerg Appenzeller, Feng Zhang, Yuqi Zhu
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Publication number: 20190363252Abstract: A resistive random access memory (Device) is disclosed. The Device includes a substrate, a first electrode formed atop the substrate, a tunneling barrier layer formed atop the first electrode, an active material formed atop the tunneling barrier layer, an isolation layer formed atop the active material, and a second electrode formed atop the isolation layer, the first electrode and the second electrode provide electrical connectivity to external components, where the active material is a phase change material which undergoes phase transition in the presence of an electric field, Joule heating, or a combination thereof.Type: ApplicationFiled: May 23, 2018Publication date: November 28, 2019Applicant: Purdue Research FoundationInventors: Joerg Appenzeller, Feng Zhang, Yuqi Zhu
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Publication number: 20190363250Abstract: A method of switching a phase-change device (Device), including changing phase of the Device from a semiconducting 2H phase to a new 2Hd phase with a higher conductivity, the Device having an active material with a thickness including a phase transition material to thereby transition the Device from a high resistive state (HRS) to a low resistive state (LRS) by application of a set voltage and further to return the Device from the LRS back to the HRS by application of a reset voltage.Type: ApplicationFiled: August 23, 2018Publication date: November 28, 2019Applicants: Purdue Research Foundation, National Institute of Standards and TechnologyInventors: Joerg Appenzeller, Feng Zhang, Yuqi Zhu, Albert V. Davydov, Sergiy Krylyuk, Huairuo Zhang, Leonid A. Bendersky
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Patent number: 9190135Abstract: Illustrative embodiments provide a FETRAM that is significantly improved over the operation of conventional FeRAM technology. In accordance with at least one disclosed embodiment, a CMOS-processing compatible memory cell provides an architecture enabling a non-destructive read out operation using organic ferroelectric PVDF-TrFE as the memory storage unit and silicon nanowire as the memory read out unit.Type: GrantFiled: August 3, 2012Date of Patent: November 17, 2015Assignee: PURDUE RESEARCH FOUNDATIONInventors: Joerg Appenzeller, Saptarshi Das
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Patent number: 9041440Abstract: A frequency tripler device is disclosed. The frequency tripler device includes a first graphene based field effect transistor (FET) of a first dopant type, having a gate, a drain, and a source, and a second graphene based FET of a second dopant type, having a gate, a drain, and a source, the gate of the first FET coupled to the gate of the second FET and coupled to an input signal having an alternating current (AC) signal of a first frequency, the combination of the first and second FETs generates an output signal with a dominant AC signal of a frequency of about three times the first frequency.Type: GrantFiled: March 3, 2014Date of Patent: May 26, 2015Assignee: Purdue Research FoundationInventors: Joerg Appenzeller, Hong-yan Chen
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Publication number: 20140292381Abstract: A frequency tripler device is disclosed. The frequency tripler device includes a first graphene based field effect transistor (FET) of a first dopant type, having a gate, a drain, and a source, and a second graphene based FET of a second dopant type, having a gate, a drain, and a source, the gate of the first FET coupled to the gate of the second FET and coupled to an input signal having an alternating current (AC) signal of a first frequency, the combination of the first and second FETs generates an output signal with a dominant AC signal of a frequency of about three times the first frequency.Type: ApplicationFiled: March 3, 2014Publication date: October 2, 2014Applicant: PURDUE RESEARCH FOUNDATIONInventors: Joerg Appenzeller, Hong-yan Chen
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Patent number: 8835238Abstract: A semiconductor structure is provided, which includes multiple sections arranged along a longitudinal axis. Preferably, the semiconductor structure comprises a middle section and two terminal sections located at opposite ends of the middle section. A semiconductor core having a first dopant concentration preferably extends along the longitudinal axis through the middle section and the two terminal sections. A semiconductor shell having a second, higher dopant concentration preferably encircles a portion of the semiconductor core at the two terminal sections, but not at the middle section, of the semiconductor structure. It is particularly preferred that the semiconductor structure is a nanostructure having a cross-sectional dimension of not more than 100 nm.Type: GrantFiled: January 15, 2014Date of Patent: September 16, 2014Assignee: International Business Machines CorporationInventors: Joerg Appenzeller, Supratik Guha, Emanuel Tutuc
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Patent number: 8765539Abstract: A semiconductor structure is provided, which includes multiple sections arranged along a longitudinal axis. Preferably, the semiconductor structure comprises a middle section and two terminal sections located at opposite ends of the middle section. A semiconductor core having a first dopant concentration preferably extends along the longitudinal axis through the middle section and the two terminal sections. A semiconductor shell having a second, higher dopant concentration preferably encircles a portion of the semiconductor core at the two terminal sections, but not at the middle section, of the semiconductor structure. It is particularly preferred that the semiconductor structure is a nanostructure having a cross-sectional dimension of not more than 100 nm.Type: GrantFiled: January 15, 2014Date of Patent: July 1, 2014Assignee: International Business Machines CorporationInventors: Joerg Appenzeller, Supratik Guha, Emanuel Tutuc
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Publication number: 20140127870Abstract: A semiconductor structure is provided, which includes multiple sections arranged along a longitudinal axis. Preferably, the semiconductor structure comprises a middle section and two terminal sections located at opposite ends of the middle section. A semiconductor core having a first dopant concentration preferably extends along the longitudinal axis through the middle section and the two terminal sections. A semiconductor shell having a second, higher dopant concentration preferably encircles a portion of the semiconductor core at the two terminal sections, but not at the middle section, of the semiconductor structure. It is particularly preferred that the semiconductor structure is a nanostructure having a cross-sectional dimension of not more than 100 nm.Type: ApplicationFiled: January 15, 2014Publication date: May 8, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Joerg Appenzeller, Supratik Guha, Emanuel Tutuc
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Publication number: 20140127888Abstract: A semiconductor structure is provided, which includes multiple sections arranged along a longitudinal axis. Preferably, the semiconductor structure comprises a middle section and two terminal sections located at opposite ends of the middle section. A semiconductor core having a first dopant concentration preferably extends along the longitudinal axis through the middle section and the two terminal sections. A semiconductor shell having a second, higher dopant concentration preferably encircles a portion of the semiconductor core at the two terminal sections, but not at the middle section, of the semiconductor structure. It is particularly preferred that the semiconductor structure is a nanostructure having a cross-sectional dimension of not more than 100 nm.Type: ApplicationFiled: January 15, 2014Publication date: May 8, 2014Applicant: International Business Machines CorporationInventors: Joerg Appenzeller, Supratik Guha, Emanuel Tutuc
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Patent number: 8637361Abstract: A semiconductor structure is provided, which includes multiple sections arranged along a longitudinal axis. Preferably, the semiconductor structure comprises a middle section and two terminal sections located at opposite ends of the middle section. A semiconductor core having a first dopant concentration preferably extends along the longitudinal axis through the middle section and the two terminal sections. A semiconductor shell having a second, higher dopant concentration preferably encircles a portion of the semiconductor core at the two terminal sections, but not at the middle section, of the semiconductor structure. It is particularly preferred that the semiconductor structure is a nanostructure having a cross-sectional dimension of not more than 100 nm.Type: GrantFiled: March 7, 2011Date of Patent: January 28, 2014Assignee: International Business Machines CorporationInventors: Joerg Appenzeller, Supratik Guha, Emanuel Tutuc
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Patent number: 8637374Abstract: A self-aligned carbon-nanotube field effect transistor semiconductor device comprises a carbon-nanotube deposited on a substrate, a source and a drain formed at a first end and a second end of the carbon-nanotube, respectively, and a gate formed substantially over a portion of the carbon-nanotube, separated from the carbon-nanotube by a dielectric film.Type: GrantFiled: February 8, 2012Date of Patent: January 28, 2014Assignee: International Business Machines CorporationInventors: Joerg Appenzeller, Phaedon Avouris, Kevin K. Chan, Philip G. Collins, Richard Martel, Hon-Sum Philip Wong
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Patent number: 8362582Abstract: A semiconductor structure is provided, which includes multiple sections arranged along a longitudinal axis. Preferably, the semiconductor structure comprises a middle section and two terminal sections located at opposite ends of the middle section. A semiconductor core having a first dopant concentration preferably extends along the longitudinal axis through the middle section and the two terminal sections. A semiconductor shell having a second, higher dopant concentration preferably encircles a portion of the semiconductor core at the two terminal sections, but not at the middle section, of the semiconductor structure. It is particularly preferred that the semiconductor structure is a nanostructure having a cross-sectional dimension of not more than 100 nm.Type: GrantFiled: March 7, 2011Date of Patent: January 29, 2013Assignee: International Business Machines CorporationInventors: Joerg Appenzeller, Supratik Guha, Emanuel Tutuc
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Publication number: 20120314476Abstract: Illustrative embodiments provide a FETRAM that is significantly improved over the operation of conventional FeRAM technology. In accordance with at least one disclosed embodiment, a CMOS-processing compatible memory cell (see definition above) provides an architecture enabling a non-destructive read out operation using organic ferroelectric PVDF-TrFE as the memory storage unit and silicon nanowire as the memory read out unit.Type: ApplicationFiled: August 3, 2012Publication date: December 13, 2012Applicant: PURDUE RESEARCH FOUNDATIONInventors: Joerg APPENZELLER, Saptarshi DAS
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Patent number: 8211741Abstract: Gate electrodes are formed on a semiconducting carbon nanotube, followed by deposition and patterning of a hole-inducing material layer and an electron inducing material layer on the carbon nanotube according to the pattern of a one dimensional circuit layout. Electrical isolation may be provided by cutting a portion of the carbon nanotube, forming a reverse biased junction of a hole-induced region and an electron-induced region of the carbon nanotube, or electrically biasing a region through a dielectric layer between two device regions of the carbon nanotube. The carbon nanotubes may be arranged such that hole-inducing material layer and electron-inducing material layer may be assigned to each carbon nanotube to form periodic structures such as a static random access memory (SRAM) array.Type: GrantFiled: June 28, 2011Date of Patent: July 3, 2012Assignee: International Business Machines CorporationInventors: Joerg Appenzeller, AJ Kleinosowski, Edward J. Nowak, Richard Q. Williams
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Publication number: 20120142158Abstract: A self-aligned carbon-nanotube field effect transistor semiconductor device comprises a carbon-nanotube deposited on a substrate, a source and a drain formed at a first end and a second end of the carbon-nanotube, respectively, and a gate formed substantially over a portion of the carbon-nanotube, separated from the carbon-nanotube by a dielectric film.Type: ApplicationFiled: February 8, 2012Publication date: June 7, 2012Inventors: Joerg Appenzeller, Phaedon Avouris, Kevin K. Chan, Philip G. Collins, Richard Martel, Hon-Sum Philip Wong
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Patent number: 8138491Abstract: A self-aligned carbon-nanotube field effect transistor semiconductor device comprises a carbon-nanotube deposited on a substrate, a source and a drain formed at a first end and a second end of the carbon-nanotube, respectively, and a gate formed substantially over a portion of the carbon-nanotube, separated from the carbon-nanotube by a dielectric film.Type: GrantFiled: August 20, 2009Date of Patent: March 20, 2012Assignee: International Business Machines CorporationInventors: Joerg Appenzeller, Phaedon Avouris, Kevin K. Chan, Philip G. Collins, Richard Martel, Hon-Sum Philip Wong