Abstract: An advanced back-end-of-line (BEOL) metallization structure is disclosed. The structure includes a diffusion barrier or cap layer having a low dielectric constant (low-k), where the cap layer is formed of silicon nitride by a plasma-enhanced chemical vapor deposition (PE CVD) process. The metallization structure also includes an inter-layer dielectric (ILD) formed of a carbon-containing dielectric material having a dielectric constant of less than about 4, and a continuous hardmask layer overlying the ILD which is preferably formed of silicon nitride or silicon carbide. A method for forming the BEOL metallization structure is also disclosed. The method includes a pre-clean or pre-activation step to improve the adhesion of the cap layer to the underlying copper conductors. The pre-clean or pre-activation step comprises exposing the copper surface to a reducing plasma including hydrogen, ammonia, nitrogen and/or noble gases.

Abstract: An advanced back-end-of-line (BEOL) metallization structure is disclosed. The structure includes a bilayer diffusion barrier or cap, where the first cap layer is formed of a dielectric material preferably deposited by a high density plasma chemical vapor deposition (HDP CVD) process, and the second cap layer is formed of a dielectric material preferably deposited by a plasma-enhanced chemical vapor deposition (PE CVD) process. A method for forming the BEOL metallization structure is also disclosed. The invention is particularly useful in interconnect structures comprising low-k dielectric material for the inter-layer dielectric (ILD) and copper for the conductors.

Abstract: An advanced back-end-of-line (BEOL) metallization structure is disclosed. The structure includes a bilayer diffusion barrier or cap, where the first cap layer is formed of a dielectric material preferably deposited by a high density plasma chemical vapor deposition (HDP CVD) process, and the second cap layer is formed of a dielectric material preferably deposited by a plasma-enhanced chemical vapor deposition (PE CVD) process. A method for forming the BEOL metallization structure is also disclosed. The invention is particularly useful in interconnect structures comprising low-k dielectric material for the inter-layer dielectric (ILD) and copper for the conductors.

Abstract: The coating thickness and uniformity of spin-on deposition layers on semiconductor wafers is controlled through the in situ control of the viscosity and homogeneity of the mixture of precursor material and solvent material. The thickness of the deposited material is selected and the viscosity required at a given spin rate for the selected thickness is automatically mixed. Sensing and control apparatus are employed to ensure that the uniformity and viscosity required is maintained before dispensing onto said semiconductor wafer. Low-K dielectric materials of selected thickness are deposited in a uniform coating.

Abstract: An advanced back-end-of-line (BEOL) interconnect structure having a hybrid dielectric is disclosed. The inter-layer dielectric (ILD) for the via level is preferably different from the ILD for the line level. In a preferred embodiment, the via-level ILD is formed of a low-k SiCOH material, and the line-level ILD is formed of a low-k polymeric thermoset material.

Abstract: An advanced back-end-of-line (BEOL) metallization structure is disclosed. The structure includes a diffusion barrier or cap layer having a low dielectric constant (low-k), where the cap layer is formed of silicon nitride by a plasma-enhanced chemical vapor deposition (PE CVD) process. The metallization structure also includes an inter-layer dielectric (ILD) formed of a carbon-containing dielectric material having a dielectric constant of less than about 4, and a continuous hardmask layer overlying the ILD which is preferably formed of silicon nitride or silicon carbide. A method for forming the BEOL metallization structure is also disclosed. The method includes a pre-clean or pre-activation step to improve the adhesion of the cap layer to the underlying copper conductors. The pre-clean or pre-activation step comprises exposing the copper surface to a reducing plasma including hydrogen, ammonia, nitrogen and/or noble gases.

Abstract: A method for forming a planarized dielectric layer upon a semiconductor wafer is disclosed. In an exemplary embodiment of the invention, the method includes applying an adhesion promoter to the wafer, thereby forming an adhesion promoter layer. A dielectric material is applied in a spin-on fashion upon the adhesion promoter layer at a relative humidity of less than 40% and for a thickness setting duration of less than 30 seconds. Then, the dielectric material is dried by baking without additional spinning of the semiconductor wafer.

Abstract: The present invention relates generally to the field of semiconductor device manufacturing, and more specifically to a method for cleaning and preconditioning a dome in a chemical vapor deposition system. During cleaning, the direction of flow of cooling water through an induction coil in the dome is reversed. During preconditioning, the direction of cooling water flow is preferably reversed again, such that it is the same direction as during deposition. The preconditioning portion of the method comprises introducing a hydrogen gas into the CVD chamber, and then introducing a mixture of hydrogen gas and nitrogen gas into the chamber.

Abstract: Novel interconnect structures possessing a relatively low internal stress and dielectric constant for use in semiconductor devices are provided herein. The novel interconnect structures comprise a first layer having a coefficient of thermal expansion greater than about 20 ppm and a first internal stress associated therewith, the first layer having a first set of metallic lines formed therein; a second layer having a coefficient of thermal expansion less than about 20 ppm and a second internal stress associated therewith, the second layer having a second set of metallic lines formed therein; and one or more stress adjustment cap layers formed between the first layer and the second layer, the cap layer(s) having a third internal stress to offset the first stress of the first layer and the second stress of the second layer and inducing a favorable relief of stress on the interconnect structure. Methods for making a semiconductor device having a substantially reduced internal stress are also provided.

Abstract: An integrated circuit structure comprises a main dielectric layer having a top surface. A cavity having sidewalls is formed in the main dielectric layer. A liner is formed on the sidewalls of the cavity. A metal conductor such as copper is formed over the liner filling the lined cavity. A getter layer is formed in the structure which combines with oxygen/moisture to form inert reaction products thereof. The getter layer can be either a conductive material which can be included in the liner or a dielectric layer which can be formed on top of the main dielectric layer, buried in the main dielectric layer or below the main dielectric layer.

Abstract: An advanced back-end-of-line (BEOL) metallization structure is disclosed. The structure includes a bilayer diffusion barrier or cap, where the first cap layer is formed of a dielectric material preferably deposited by a high density plasma chemical vapor deposition (HDP CVD) process, and the second cap layer is formed of a dielectric material preferably deposited by a plasma-enhanced chemical vapor deposition (PE CVD) process. A method for forming the BEOL metallization structure is also disclosed. The invention is particularly useful in interconnect structures comprising low-k dielectric material for the inter-layer dielectric (ILD) and copper for the conductors.

Abstract: An advanced back-end-of-line (BEOL) metallization structure is disclosed. The structure includes a diffusion barrier or cap layer having a low dielectric constant (low-k). The cap layer is formed of amorphous nitrogenated hydrogenated silicon cabride, and has a dielectric constant (k) of less than about 5. A method for forming the BEOL metallization structure is also disclosed, where the cap layer is deposited using a plasma-enhanced chemical vapor deposition (PE CVD) process. The invention is particularly useful in interconnect structure comprising low-k dielectric material for the inter-layer dielectric (ILD) and copper for the conductors.

Abstract: An advanced back-end-of-line (BEOL) metallization structure is disclosed. The structure includes a diffusion barrier or cap layer having a low dielectric constant (low-k), where the cap layer is formed of silicon nitride by a plasma-enhanced chemical vapor deposition (PE CVD) process. The metallization structure also includes an inter-layer dielectric (ILD) formed of a carbon-containing dielectric material having a dielectric constant of less than about 4, and a continuous hardmask layer overlying the ILD which is preferably formed of silicon nitride or silicon carbide. A method for forming the BEOL metallization structure is also disclosed. The method includes a pre-clean or pre-activation step to improve the adhesion of the cap layer to the underlying copper conductors. The pre-clean or pre-activation step comprises exposing the copper surface to a reducing plasma including hydrogen, ammonia, nitrogen and/or noble gases.

Abstract: A method for removing a dielectric layer formed upon a semiconductor substrate is disclosed. In an exemplary embodiment of the invention, the method includes subjecting the dielectric layer to a dry etch process and subjecting an adhesion promoter layer underneath the dielectric layer to a wet etch process.

Abstract: A method for forming a planarized dielectric layer upon a semiconductor wafer is disclosed. In an exemplary embodiment of the invention, the method includes applying an adhesion promoter to the wafer, thereby forming an adhesion promoter layer. A dielectric material is applied in a spin-on fashion upon the adhesion promoter layer at a relative humidity of less than 40% and for a thickness setting duration of less than 30 seconds. Then, the dielectric material is dried by baking without additional spinning of the semiconductor wafer.

Abstract: The present invention relates generally to the field of semiconductor device manufacturing, and more specifically to a method for cleaning and preconditioning a dome in a chemical vapor deposition system. During cleaning, the direction of flow of cooling water through an induction coil in the dome is reversed. During preconditioning, the direction of cooling water flow is preferably reversed again, such that it is the same direction as during deposition. The preconditioning portion of the method comprises introducing a hydrogen gas into the CVD chamber, and then introducing a mixture of hydrogen gas and nitrogen gas into the chamber.

Abstract: A method and structure for improving a coating on a substrate comprises a chamber further comprising a rotatable holder, which holds the substrate; a supply of coating material for coating the substrate in the chamber; a window in the wall of the chamber; and a supply of liquid for coating at least a portion of the window on the interior side of the chamber. The chamber is preferably adapted to house the window in multiple configurations. A camera (or other optical detector), which is positioned outside of the chamber, monitors the substrate through the window.

Abstract: The adhesion of a silicon carbide containing film to a surface is enhanced by employing a transition film of silicon nitride, silicon dioxide and/or silicon oxynitride.

Abstract: A SiCr microfuse, deletable either by electrical voltage pulses or by laser pulses, for rerouting the various components in an integrated circuit, as where redundancy in array structures is implemented, and the method of fabricating same, at any wiring level of the chip, by utilizing a direct resist masking of the SiCr fuse layer to eliminate problems of mask damage and residual metal adjacent the fuse.

Abstract: A SiCr microfuse, deletable either by electrical voltage pulses or by laser pulses, for rerouting the various components in an integrated circuit, as where redundancy in array structures is implemented, and the method of fabricating same, at any wiring level of the chip, by utilizing a direct resist masking of the SiCr fuse layer to eliminate problems of mask damage and residual metal adjacent the fuse.