Patents by Inventor John A. Fitzsimmons

John A. Fitzsimmons has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Forming semiconductor chip connections
    Patent number: 8236610
    Abstract: Systems and methods are disclosed that enable forming semiconductor chip connections. In one embodiment, the semiconductor chip includes a body having a polyhedron shape with a pair of opposing sides; and a solder member extending along a side that extends between the pair of opposing sides of the polyhedron shape.
    Type: Grant
    Filed: May 26, 2009
    Date of Patent: August 7, 2012
    Assignee: International Business Machines Corporation
    Inventors: Louis Lu-Chen Hsu, Kangguo Cheng, Timothy J. Dalton, Mukta G. Farooq, John A. Fitzsimmons
  • FORMING SEMICONDUCTOR CHIP CONNECTIONS
    Publication number: 20120187561
    Abstract: Systems and methods are disclosed that enable forming semiconductor chip connections. In one embodiment, the semiconductor chip includes a body having a polyhedron shape with a pair of opposing sides; and a solder member extending along a side that extends between the pair of opposing sides of the polyhedron shape.
    Type: Application
    Filed: March 28, 2012
    Publication date: July 26, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Louis Lu-Chen Hsu, Kangguo Cheng, Timothy J. Dalton, Mukta G. Farooq, John A. Fitzsimmons
  • BILAYER TRENCH FIRST HARDMASK STRUCTURE AND PROCESS FOR REDUCED DEFECTIVITY
    Publication number: 20120187546
    Abstract: A method and structure for transferring a lithographic pattern into a substrate includes forming a dielectric hardmask layer over a dielectric substrate. A metal hardmask layer is formed over the dielectric hardmask layer. A protective capping hardmask layer or capping film is formed over the metal hardmask layer, and a lithographic structure for pattern transfer is formed over the capping layer. A pattern is transferred into the dielectric substrate using the defined lithographic structure. The capping hardmask layer can be removed during subsequent processing.
    Type: Application
    Filed: January 24, 2011
    Publication date: July 26, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Hakeem B.S. Akinmade-Yusuff, Samuel Sung Shik Choi, Edward R. Engbrecht, John A. Fitzsimmons
  • Reducing effective dielectric constant in semiconductor devices
    Patent number: 8129286
    Abstract: Method of manufacturing a semiconductor device structure, including the steps of providing a structure having an insulator layer with at least one interconnect, forming a sub lithographic template mask over the insulator layer, and selectively etching the insulator layer through the sub lithographic template mask to form sub lithographic features spanning to a sidewall of the at least one interconnect.
    Type: Grant
    Filed: June 16, 2008
    Date of Patent: March 6, 2012
    Assignee: International Business Machines Corporation
    Inventors: Daniel C. Edelstein, Matthew E. Colburn, Edward C. Cooney, III, Timothy J. Dalton, John A. Fitzsimmons, Jeffrey P. Gambino, Elbert E. Huang, Michael W. Lane, Vincent J. McGahay, Lee M. Nicholson, Satyanarayana V. Nitta, Sampath Purushothaman, Sujatha Sankaran, Thomas M. Shaw, Andrew H. Simon, Anthony K. Stamper
  • COPPER ALLOY VIA BOTTOM LINER
    Publication number: 20110227225
    Abstract: Improved mechanical and adhesive strength and resistance to breakage of copper integrated circuit interconnections is obtained by forming a copper alloy in a copper via/wiring connection in an integrated circuit while minimizing adverse electrical effects of the alloy by confining the alloy to an interfacial region of said via/wiring connection and not elsewhere by a barrier which reduces or substantially eliminates the thickness of alloy in the conduction path. The alloy location and composition are further stabilized by reaction of all available alloying material with copper, copper alloys or other metals and their alloys.
    Type: Application
    Filed: May 26, 2011
    Publication date: September 22, 2011
    Inventors: Daniel C. Edelstein, Edward C. Cooney, III, John A. Fitzsimmons, Jeffrey P. Gambino, Anthony K. Stamper
  • Integrated circuit hard mask processing system
    Patent number: 8018061
    Abstract: An integrated circuit processing system is provided including a substrate having an integrated circuit; an interconnect layer over the integrated circuit; a low-K dielectric layer over the interconnect layer; a hard mask layer over the low-K dielectric layer; a via opening through the hard mask layer and the low-K dielectric layer to the interconnect layer; and an interconnect metal in the via opening.
    Type: Grant
    Filed: September 25, 2009
    Date of Patent: September 13, 2011
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Wuping Liu, Michael Beck, John A. Fitzsimmons
  • ELECTROMIGRATION IMMUNE THROUGH-SUBSTRATE VIAS
    Publication number: 20110193199
    Abstract: A through-substrate via (TSV) structure includes at least two electrically conductive via segments embedded in a substrate and separated from each other by an electrically conductive barrier layer therebetween. The length of each individual conductive via segment is typically equal to, or less than, the Blech length of the conductive material so that the stress-induced back flow force, generated by each conductive barrier layer, cancels the electromigration force in each conductive via segment. Consequently, the TSV structures are immune to electromigration, and provide reliable electrical connections among a chips stacked in 3 dimensions.
    Type: Application
    Filed: February 9, 2010
    Publication date: August 11, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ronald G. Filippi, John A. Fitzsimmons, Kevin Kolvenbach, Ping-Chuan Wang
  • CO-AXIAL RESTRAINT FOR CONNECTORS WITHIN FLIP-CHIP PACKAGES
    Publication number: 20110180920
    Abstract: An assembly can include a microelectronic element such as, for example, a semiconductor element having circuits and semiconductor devices fabricated therein, and a plurality of electrical connectors, e.g., solder balls attached to contacts of the microelectronic element. The connectors can be surrounded by first, inner regions 200 of compressible dielectric material and second, outer regions of dielectric material. In one embodiment, an underfill can contact a face of the microelectronic element between respective connectors or second regions. The second regions can provide restraining force, such that during volume expansion of the connectors, the first regions can compress against the restraining force of the second regions.
    Type: Application
    Filed: January 28, 2010
    Publication date: July 28, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Mukta G. Farooq, John A. Fitzsimmons
  • DEVICE AND METHODOLOGY FOR REDUCING EFFECTIVE DIELECTRIC CONSTANT IN SEMICONDUCTOR DEVICES
    Publication number: 20110111590
    Abstract: Method of manufacturing a structure which includes the steps of providing a structure having an insulator layer with at least one interconnect, forming a sub lithographic template mask over the insulator layer, and selectively etching the insulator layer through the sub lithographic template mask to form sub lithographic features spanning to a sidewall of the plurality of interconnects.
    Type: Application
    Filed: January 12, 2011
    Publication date: May 12, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Daniel C. Edelstein, Matthew E. Colburn, Edward C. Cooney, III, Timothy J. Dalton, John A. Fitzsimmons, Jeffrey P. Gambino, Elbert E. Huang, Michael W. Lane, Vincent J. McGahay, Lee M. Nicholson, Satyanarayana V. Nitta, Sampath Purushothaman, Sujatha Sankaran, Thomas M. Shaw, Andrew H. Simon, Anthony K. Stamper
  • METHOD AND STRUCTURE FOR REWORKING ANTIREFLECTIVE COATING OVER SEMICONDUCTOR SUBSTRATE
    Publication number: 20110101507
    Abstract: A method and a structure for reworking an antireflective coating (ARC) layer over a semiconductor substrate. The method includes providing a substrate having a material layer, forming a planarization layer on the material layer, forming an organic solvent soluble layer on the planarization layer, forming an ARC layer on the organic solvent soluble layer, forming a pattern in the ARC layer, and removing the organic solvent soluble layer and the ARC layer with an organic solvent while leaving the planarization layer unremoved. The structure includes a substrate having a material layer, a planarization layer on the material layer, an organic solvent soluble layer on the planarization layer, and an ARC layer on the organic solvent soluble layer.
    Type: Application
    Filed: November 2, 2009
    Publication date: May 5, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Hakeem Akinmade Yusuff, John A. Fitzsimmons, Ranee Wai-Ling Kwong
  • CLEANING EXHAUST SCREENS IN A MANUFACTURING PROCESS
    Publication number: 20110079255
    Abstract: A method of cleaning an screen in a manufacturing process step that employs a chamber including a drain line having a screen configured and disposed in the chamber above the drain line to trap soluble materials includes detecting a build-up of soluble material on the screen, ceasing a work operation in the chamber, and initiating a screen cleaning operation. The screen cleaning operation includes closing a computer operated valve fluidly connected to the drain line to fluidly isolate a portion of the chamber, automatically introducing an amount of solvent into the chamber once the computer operated valve is closed with the amount of solvent filling the chamber and/or the drain line to fully immerse the screen, and opening the operated valve after a predetermined amount of time to empty the chamber and the drain line of solvent once the soluble materials trapped on the screen are dissolved.
    Type: Application
    Filed: October 1, 2009
    Publication date: April 7, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: John A. Fitzsimmons, Richard O. Henry
  • Device and methodology for reducing effective dielectric constant in semiconductor devices
    Patent number: 7892940
    Abstract: Method of manufacturing a structure which includes the steps of providing a structure having an insulator layer with at least one interconnect, forming a sub lithographic template mask over the insulator layer, and selectively etching the insulator layer through the sub lithographic template mask to form sub lithographic features spanning to a sidewall of the at least one interconnect.
    Type: Grant
    Filed: September 6, 2007
    Date of Patent: February 22, 2011
    Assignee: International Business Machines Corporation
    Inventors: Daniel C. Edelstein, Matthew E. Colburn, Edward C. Cooney, III, Timothy J. Dalton, John A. Fitzsimmons, Jeffrey P. Gambino, Elbert E. Huang, Michael W. Lane, Vincent J. McGahay, Lee M. Nicholson, Satyanarayana V. Nitta, Sampath Purushothaman, Sujatha Sankaran, Thomas M. Shaw, Andrew H. Simon, Anthony K. Stamper
  • Forming Semiconductor Chip Connections
    Publication number: 20100301475
    Abstract: Systems and methods are disclosed that enable forming semiconductor chip connections. In one embodiment, the semiconductor chip includes a body having a polyhedron shape with a pair of opposing sides; and a solder member extending along a side that extends between the pair of opposing sides of the polyhedron shape.
    Type: Application
    Filed: May 26, 2009
    Publication date: December 2, 2010
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Louis Lu-Chen Hsu, Kangguo Cheng, Timothy J. Dalton, Mukta G. Farooq, John A. Fitzsimmons
  • Pad structure to provide improved stress relief
    Patent number: 7755206
    Abstract: A semiconductor interconnection comprises a semiconductor device, a substrate adjacent the semiconductor device, and a plurality of spring contacts on the semiconductor device or the substrate. A plurality of solder connections are on the opposite semiconductor device or substrate. Each spring contact comprises a contact surface and a conductive material on the contact surface. Upon assembly of the semiconductor device and the substrate, the conductive material on the plurality of spring contacts makes contact with each of the plurality of solder connections. The conductive material is in a liquid state at manufacturing or operating temperatures of the semiconductor device. Thus, the conductive material could be a solid at room temperature and transition to a liquid state at the semiconductor's manufacturing or operating temperatures.
    Type: Grant
    Filed: November 29, 2007
    Date of Patent: July 13, 2010
    Assignee: International Business Machines Corporation
    Inventors: Mukta G. Farooq, John A. Fitzsimmons, Thomas J. Fleischman
  • Integrated circuit fabrication process using gas cluster ion beam etching
    Patent number: 7709344
    Abstract: A method comprises depositing a dielectric film layer, a hard mask layer, and a patterned photo resist layer on a substrate. The method further includes selectively etching the dielectric film layer to form sub-lithographic features by reactive ion etch processing and depositing a barrier metal layer and a copper layer. The method further includes etching the barrier metal layer and hard mask layer by gas cluster ion beam (GCIB) processing.
    Type: Grant
    Filed: November 22, 2005
    Date of Patent: May 4, 2010
    Assignee: International Business Machines Corporation
    Inventors: Shyng-Tsong T. Chen, John A. Fitzsimmons, Shom S. Ponoth, Terry A. Spooner
  • Minimizing low-k dielectric damage during plasma processing
    Patent number: 7691736
    Abstract: Embodiments of the invention provide a semiconductor device having dielectric material and its method of manufacture. A method comprises a short (?2 sec) flash activation of an ILD surface followed by flowing a precursor such as silane, DEMS, over the activated ILD surface. The precursor reacts with the activated ILD surface thereby selectively protecting the ILD surface. The protected ILD surface is resistant to plasma processing damage. The protected ILD surface eliminates the requirement of using a hard mask to protect a dielectric from plasma damage.
    Type: Grant
    Filed: February 10, 2006
    Date of Patent: April 6, 2010
    Assignee: Infineon Technologies AG
    Inventors: Michael Beck, John A. Fitzsimmons, Karl Hornik, Darryl Restaino
  • Oxidant and passivant composition and method for use in treating a microelectronic structure
    Patent number: 7670497
    Abstract: A composition that may be used for cleaning a metal containing conductor layer, such as a copper containing conductor layer, within a microelectronic structure includes an aqueous acid, along with an oxidant material and a passivant material contained within the aqueous acid. The composition does not include an abrasive material. The composition is particularly useful for cleaning a residue from a copper containing conductor layer and an adjoining dielectric layer that provides an aperture for accessing the copper containing conductor layer within a microelectronic structure.
    Type: Grant
    Filed: July 6, 2007
    Date of Patent: March 2, 2010
    Assignees: International Business Machines Corporation, Infineon Technologies AG
    Inventors: John A. Fitzsimmons, David L. Rath, Shom Ponoth, Michael Beck
  • INTEGRATED CIRCUIT HARD MASK PROCESSING SYSTEM
    Publication number: 20100013104
    Abstract: An integrated circuit processing system is provided including a substrate having an integrated circuit; an interconnect layer over the integrated circuit; a low-K dielectric layer over the interconnect layer; a hard mask layer over the low-K dielectric layer; a via opening through the hard mask layer and the low-K dielectric layer to the interconnect layer; and an interconnect metal in the via opening.
    Type: Application
    Filed: September 25, 2009
    Publication date: January 21, 2010
    Applicants: CHARTERED SEMICONDUCTOR MANUFACTURING LTD., INFINEON TECHNOLOGIES NORTH AMERICA CORP., INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Wuping Liu, Michael Beck, John A. Fitzsimmons
  • Integrated circuit manufacturing method using hard mask
    Patent number: 7615484
    Abstract: An integrated circuit hard mask processing system is provided including providing a substrate having an integrated circuit; forming an interconnect layer over the integrated circuit; applying a low-K dielectric layer over the interconnect layer; applying a hard mask layer over the low-K dielectric layer; forming a via opening through the hard mask layer and the low-K dielectric layer to the interconnect layer; applying a first fluid and a second fluid in the via opening for removing an overhang of the hard mask layer; depositing an interconnect metal in the via opening; and chemical-mechanical polishing the interconnect metal and the ultra low-K dielectric layer.
    Type: Grant
    Filed: April 24, 2007
    Date of Patent: November 10, 2009
    Assignees: Chartered Semiconductor Manufacturing Ltd., Infineon Technologies North America Corp., International Business Machines Corporation
    Inventors: Wuping Liu, Michael Beck, John A. Fitzsimmons
  • Device and methodology for reducing effective dielectric constant in semiconductor devices
    Patent number: 7592685
    Abstract: Semiconductor structure includes an insulator layer having at least one interconnect feature and at least one gap formed in the insulator layer spanning more than a minimum spacing of interconnects.
    Type: Grant
    Filed: August 31, 2007
    Date of Patent: September 22, 2009
    Assignee: International Business Machines Corporation
    Inventors: Daniel C. Edelstein, Matthew E. Colburn, Edward C. Cooney, III, Timothy J. Dalton, John A. Fitzsimmons, Jeffrey P. Gambino, Elbert E. Huang, Michael W. Lane, Vincent J. McGahay, Lee M. Nicholson, Satyanarayana V. Nitta, Sampath Purushothaman, Sujatha Sankaran, Thomas M. Shaw, Andrew H. Simon, Anthony K. Stamper