Abstract: Methods and structures having pore-closing layers for closing exposed pores in a patterned porous low-k dielectric layer, and optionally a reactive liner on the low-k dielectric. A first reactant is absorbed or retained in exposed pores in the patterned dielectric layer and then a second reactant is introduced into openings such that it enters the exposed pores, while first reactant molecules are simultaneously being outgassed. The second reactant reacts in-situ with the outgassed first reactant molecules at a mouth region of the exposed pores to form the pore-closing layer across the mouth region of exposed pores, while retaining a portion of each pore's porosity to maintain characteristics and properties of the porous low-k dielectric layer. Optionally, the first reactant may be adsorbed onto the low-k dielectric such that upon introduction of the second reactant into the patterned dielectric openings, a reactive liner is also formed on the low-k dielectric.

Abstract: Methods and conductive interconnect structures are provided for preventing cracks in a dielectric layer on a substrate. Substantially half cylindrical or cylindrical trench openings are formed within at least one dielectric layer, which are then filled with a high conductivity metal for forming substantially half cylindrical or cylindrical wires. The rounded bottom portions of the substantially half cylindrical wires, or the rounded bottom and top portions of the substantially half cylindrical wires, avoid any propagation points for starting cracks in the dielectric layer, as compared to conventional rectangular conductors having angled edges, which in fact are propagation points for initiating cracks. The substantially half cylindrical or cylindrical wires also reduce the line-to-line capacitance between neighboring wires, substantially eliminate any high stress points in the dielectric layer, reduce mechanical stresses induced on the IC and increase the overall mechanical strength of the IC.

Abstract: In an embodiment of the invention, a dielectric material comprises a matrix of a material selected from the group consisting essentially of organic materials, inorganic materials and organo-silicate materials; a plurality of pores dispersed throughout the matrix; and a gas filling the pores. The gas is selected from the group consisting essentially of inert gases, depositing gases, and breakdown suppressing gases. The filled pore dielectric material is suitably used in a damascene wiring layer. In further embodiments, a plasma device comprises an integrated circuit (IC) chip substrate; at least one dielectric layer having a thickness on a surface of the substrate, a cavity formed in the dielectric layer, at least two electrodes disposed in the cavity; and a plasma gas filling the cavity. The plasma device can operate as a light source or as a switch.

Abstract: Methods of forming and the integrated circuit device structure formed having vertical interfaces adjacent an existing crack stop around a perimeter of a chip, whereby the vertical interface controls cracks generated during side processing of the device such as dicing, and in service from penetrating the crack stop. The vertical interface is comprised of a material that prevents cracks from damaging the crack stop by deflecting cracks away from penetrating the crack stop, or by absorbing the generated crack energies. Alternatively, the vertical interface may be a material that allows advancing cracks to lose enough energy such that they become incapable of penetrating the crack stop. The present vertical interfaces can be implemented in a number of ways such as, vertical spacers of release material, vertical trenches of release material or vertical channels of the release material.

Abstract: An advanced back-end-of-line (BEOL) metallization structure is disclosed. The structure includes a diffusion barrier or cap layer having a low dielectric constant (low-k), where the cap layer is formed of silicon nitride by a plasma-enhanced chemical vapor deposition (PE CVD) process. The metallization structure also includes an inter-layer dielectric (ILD) formed of a carbon-containing dielectric material having a dielectric constant of less than about 4, and a continuous hardmask layer overlying the ILD which is preferably formed of silicon nitride or silicon carbide. A method for forming the BEOL metallization structure is also disclosed. The method includes a pre-clean or pre-activation step to improve the adhesion of the cap layer to the underlying copper conductors. The pre-clean or pre-activation step comprises exposing the copper surface to a reducing plasma including hydrogen, ammonia, nitrogen and/or noble gases.

Abstract: A method for manufacturing a structure includes providing a structure having an insulator layer with at least one interconnect and forming a sub lithographic template mask on the insulator layer. A selective etching step is used for etching the insulator layer through the sub lithographic template mask to form sub lithographic features near the at least one interconnect. A supra lithographic blocking mask may also be utilized. In another aspect, the method includes forming pinch off sections of sub lithographic size formed in a capping layer on the insulator layer. A semiconductor structure includes an insulator layer having at least one interconnect feature and at least one column formed in the insulator layer. A plurality of sub lithographic features formed on a top portion of the insulator layer and communicating with the at least one column is also provided. The plurality of sub lithographic features have a cross section or diameter less than any of the at least one column.

Abstract: An advanced back-end-of-line (BEOL) interconnect structure having a hybrid dielectric is disclosed. The inter-layer dielectric (ILD) for the via level is preferably different from the ILD for the line level. In a preferred embodiment, the via-level ILD is formed of a low-k SiCOH material, and the line-level ILD is formed of a low-k polymeric thermoset material.

Abstract: An advanced back-end-of-line (BEOL) metallization structure is disclosed. The structure includes a bilayer diffusion barrier or cap, where the first cap layer is formed of a dielectric material preferably deposited by a high density plasma chemical vapor deposition (HDP CVD) process, and the second cap layer is formed of a dielectric material preferably deposited by a plasma-enhanced chemical vapor deposition (PE CVD) process. A method for forming the BEOL metallization structure is also disclosed. The invention is particularly useful in interconnect structure comprising low-k dielectric material for the inter-layer dielectric (ILD) and copper for the conductors.

Abstract: A process for providing regions of substantially lower fluorine content in a fluorine-containing dielectric comprises exposing the fluorine-containing dielectric to a reactive species to form volatile byproducts.

Abstract: A method is disclosed of repairing wirebond damage on semiconductor chips such as high speed semiconductor microprocessors, application specific integrated circuits (ASICs), and other high speed integrated circuit devices, particularly devices using low-k dielectric materials. The method involves surface modification using reactive liquids. In a preferred embodiment, the method comprises applying a silicon-containing liquid reagent precursor such as TEOS to the surface of the chip and allowing the liquid reagent to react with moisture to form a solid dielectric plug or film (50) to produce a barrier against moisture ingress, thereby enhancing the temperature/humidity/bias (THB) performance of such semiconductor devices.

Abstract: An intermediate semiconductor structure and method for low-pressure wire bonding that reduces the propensity of dielectric material to mechanical failure due to any wire bonding stresses. Roughened surfaces such as metal pillars or metal dendrites are provided on a bonding pad, bonding wire or both. These roughened surfaces increase reactivity between the bond wire and the bond pad to form strong bonds. This increased activity as a result of the roughened bonding pad and/or wire surfaces reduce the amount of pressure, temperature and energy required for wire bonding, which in turn, avoids damage to the bonding pad as well as the semiconductor substrate.

Abstract: A structure and method for low-pressure wirebonding, reducing the propensity of dielectric material to mechanical failure due to wirebond stress. A low temperature alloy on the surface of a bond pad allows alloy bond formation to occur between the wire and the bond pad at reduced bond pressures and reduced thermal and ultrasonic energies. Preferred alloys include Au—Sn and Au—In. The Au—Sn alloy may be formed over the Cu bond pad, incorporated in an aluminum bond pad stack, or deposited on a bond pad having Ni—Au capping of Cu or Al bond pads.

Abstract: An advanced back-end-of-line (BEOL) metallization structure is disclosed. The structure includes a bilayer diffusion barrier or cap, where the first cap layer is formed of a dielectric material preferably deposited by a high density plasma chemical vapor deposition (HDP CVD) process, and the second cap layer is formed of a dielectric material preferably deposited by a plasma-enhanced chemical vapor deposition (PE CVD) process. A method for forming the BEOL metallization structure is also disclosed. The invention is particularly useful in interconnect structures comprising low-k dielectric material for the inter-layer dielectric (ILD) and copper for the conductors.

Abstract: A complimentary self-locking wire bond structure and technique is introduced, where the bonding force is focused at the tip of the bond wire and a barb-type construction is utilized to enhance the durability and reduce the insertion forces. The end of wire bond has an “arrowhead” or similar functioning fastener such that the force is focused to a point that pierces the bond pad in a local area. The bond pad may be self-healing, such that the bond pad is made to close over and seal or lock the barb into the underpad layer below the pad, while making electrical contact with the wire bond at the bond pad surface. The bond pad may have a cushioning layer or cavity below it to dampen the piecing force of the pointed barb. A thin metal pad may also be formed over the compliant underpad layer for force absorption.

Abstract: A method for removing a dielectric layer formed upon a semiconductor substrate is disclosed. In an exemplary embodiment of the invention, the method includes subjecting the dielectric layer to a dry etch process and subjecting an adhesion promoter layer underneath the dielectric layer to a wet etch process.

Abstract: An advanced back-end-of-line (BEOL) interconnect structure having a hybrid dielectric is disclosed. The inter-layer dielectric (ILD) for the via level is preferably different from the ILD for the line level. In a preferred embodiment, the via-level ILD is formed of a low-k SiCOH material, and the line-level ILD is formed of a low-k polymeric thermoset material.

Abstract: The coating thickness and uniformity of spin-on deposition layers on semiconductor wafers is controlled through the in situ control of the viscosity and homogeneity of the mixture of precursor material and solvent material. The thickness of the deposited material is selected and the viscosity required at a given spin rate for the selected thickness is automatically mixed. Sensing and control apparatus are employed to ensure that the uniformity and viscosity required is maintained before dispensing onto said semiconductor wafer. Low-K dielectric materials of selected thickness are deposited in a uniform coating.

Abstract: An integrated circuit plasma processing system, apparatus and method for reclaiming material, such as a plasma precursor and potentially useful components among their byproducts, from plasma-enhanced exhaust of a plasma process chamber for subsequent reuse in the chamber. The apparatus provides a recycle feedback loop for a plasma process chamber that provides the high purity materials necessary for microelectronic applications. Since the apparatus is in-situ, no byproducts that are not already present are possible. Accordingly, the apparatus guarantees purity of the recycled material. In addition to cost savings, the invention provides an environmentally friendly plasma process chamber and apparatus with very little production of waste.

Abstract: A method for forming back-end-of-line (BEOL) interconnect structures in disclosed. The method and resulting structure includes etchback for low-k dielectric materials. Specifically, a low dielectric constant material is integrated into a dual or single damascene wiring structure which contains a dielectric material having relatively high dielectric constant (i.e., 4.0 or higher). The damascene structure comprises the higher dielectric constant material immediately adjacent to the metal interconnects, thus benefiting from the mechanical characteristics of these materials, while incorporating the lower dielectric constant material in other areas of the interconnect level.

Abstract: A process for providing regions of substantially lower fluorine content in a fluorine-containing dielectric comprises exposing the fluorine-containing dielectric to a reactive species to form volatile byproducts.