Patents by Inventor John A. Ott

John A. Ott has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190318193
    Abstract: A method for crystal analysis includes identifying a crystalline region on a device where an electronic channeling pattern is needed to be determined, acquiring a whole image for each of a plurality of different positions for the crystalline region using a scanning electron microscope (SEM) as the crystalline region is moved to different positions. Relevant regions are extracted from the whole images. The images of the relevant regions are stitched together to form a composite map of a full electron channeling pattern representative of the crystalline region wherein the electronic channeling pattern is provided due to an increase in effective angular range between a SEM beam and a surface of the crystal region.
    Type: Application
    Filed: June 27, 2019
    Publication date: October 17, 2019
    Inventors: Stephen W. Bedell, Kunal Mukherjee, John A. Ott, Devendra K. Sadana, Brent A. Wacaser
  • Publication number: 20190304348
    Abstract: A display system includes: a first upright oriented vertically; a second upright oriented vertically and offset horizontally from the first upright by a frame separation distance, the first upright and the second upright defining a display opening therebetween; a first clip bracket secured to the first upright with a first clip fastener; and a second clip bracket secured to the second upright with a second clip fastener, each of the first clip bracket and the second clip bracket including a base portion and a clip portion, the base portion and the clip portion defining an insertion slot, a main entrance of the insertion slot of each of the first clip bracket and the second clip bracket facing forward, the clip portion configured to hold a display panel inside the insertion slot, the clip portion configured to hold an edge of the display panel against the base portion.
    Type: Application
    Filed: June 20, 2019
    Publication date: October 3, 2019
    Inventors: Jeffrey Alan Tuttle, John Richard Muse, Paul Ott, Travis Walters
  • Patent number: 10417519
    Abstract: A method for crystal analysis includes identifying a crystalline region on a device where an electronic channeling pattern is needed to be determined, acquiring a whole image for each of a plurality of different positions for the crystalline region using a scanning electron microscope (SEM) as the crystalline region is moved to different positions. Relevant regions are extracted from the whole images. The images of the relevant regions are stitched together to form a composite map of a full electron channeling pattern representative of the crystalline region wherein the electronic channeling pattern is provided due to an increase in effective angular range between a SEM beam and a surface of the crystal region.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: September 17, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Stephen W. Bedell, Kunal Mukherjee, John A. Ott, Devendra K. Sadana, Brent A. Wacaser
  • Patent number: 10388197
    Abstract: A display system includes: a first upright oriented vertically; a second upright oriented vertically and offset horizontally from the first upright by a frame separation distance, the first upright and the second upright defining a display opening therebetween; a first clip bracket secured to the first upright with a first clip fastener; and a second clip bracket secured to the second upright with a second clip fastener, each of the first clip bracket and the second clip bracket including a base portion and a clip portion, the base portion and the clip portion defining an insertion slot, a main entrance of the insertion slot of each of the first clip bracket and the second clip bracket facing forward, the clip portion configured to hold a display panel inside the insertion slot, the clip portion configured to hold an edge of the display panel against the base portion.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: August 20, 2019
    Assignee: Pratt Corrugated Holdings, Inc.
    Inventors: Jeffrey Alan Tuttle, John Richard Muse, Paul Ott, Travis Walters
  • Patent number: 10388522
    Abstract: A method for forming an epitaxial structure includes providing a two-dimensional material on a crystal semiconductor material and opening up portions of the two-dimensional material to expose the crystal semiconductor material. A structure is epitaxially grown in the portions opened up in the crystal semiconductor material such that the epitaxial growth is selective to the exposed crystal semiconductor material relative to the two-dimensional material.
    Type: Grant
    Filed: March 26, 2018
    Date of Patent: August 20, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Cheng-Wei Cheng, Jeehwan Kim, John A. Ott, Devendra K. Sadana
  • Patent number: 10356197
    Abstract: Generally discussed herein are systems, devices, and methods for managing content of an information centric network (ICN). A component of an ICN can include a memory including an extended content store that includes content from at least one other component of the ICN, and first attributes of the content, the first attributes including a content popularity value that indicates a number of requests for the content, and processing circuitry to increment the content popularity value in response to a transmission of a first content packet that includes the content, the first content packet transmitted in response to receiving an interest packet.
    Type: Grant
    Filed: January 24, 2017
    Date of Patent: July 16, 2019
    Assignee: Intel Corporation
    Inventors: Vallabhajosyula S. Somayazulu, Eve M. Schooler, Hassnaa Moustafa, Andrew Stephen Brown, Rath Vannithamby, Srikathyayani Srikanteswara, David John Zage, Ren Wang, Christian Maciocco, David E. Ott, Jeffrey C. Sedayao, David E. Cohen, Sung Lee
  • Publication number: 20190213928
    Abstract: A display system includes: a first upright oriented vertically; a second upright oriented vertically and offset horizontally from the first upright by a frame separation distance, the first upright and the second upright defining a display opening therebetween; a first clip bracket secured to the first upright with a first clip fastener; and a second clip bracket secured to the second upright with a second clip fastener, each of the first clip bracket and the second clip bracket including a base portion and a clip portion, the base portion and the clip portion defining an insertion slot, a main entrance of the insertion slot of each of the first clip bracket and the second clip bracket facing forward, the clip portion configured to hold a display panel inside the insertion slot, the clip portion configured to hold an edge of the display panel against the base portion.
    Type: Application
    Filed: January 8, 2018
    Publication date: July 11, 2019
    Inventors: Jeffrey Alan Tuttle, John Richard Muse, Paul Ott, Travis Walters
  • Publication number: 20190213929
    Abstract: A clip bracket includes: a base portion defining a clearance hole configured to receive a fastener securing the base portion to a structure; and a clip portion connected to the base portion, the base portion and the clip portion defining an insertion slot, a one of the base portion and the clip portion of the clip bracket including an engagement rib defining an effective width of the insertion slot that is less than a nominal width of the insertion slot.
    Type: Application
    Filed: January 31, 2019
    Publication date: July 11, 2019
    Inventors: Jeffrey Alan Tuttle, John Richard Muse, Paul Ott, Travis Walters
  • Publication number: 20190157458
    Abstract: A finFET structure, and method of forming such structure, in which a germanium enriched nanowire is located in the channel region of the FET, while simultaneously having silicon-germanium fin in the source/drain region of the finFET.
    Type: Application
    Filed: January 30, 2019
    Publication date: May 23, 2019
    Inventors: Kevin K. Chan, Pouya Hashemi, Ali Khakifirooz, John A. Ott, Alexander Reznicek
  • Patent number: 10236384
    Abstract: A finFET structure, and method of forming such structure, in which a germanium enriched nanowire is located in the channel region of the FET, while simultaneously having silicon-germanium fin in the source/drain region of the finFET.
    Type: Grant
    Filed: December 8, 2017
    Date of Patent: March 19, 2019
    Assignee: International Business Machines Corporation
    Inventors: Kevin K. Chan, Pouya Hashemi, Ali Khakifirooz, John A. Ott, Alexander Reznicek
  • Patent number: 10127649
    Abstract: A method for crystal analysis includes identifying a crystalline region on a device where an electronic channeling pattern is needed to be determined, acquiring a whole image for each of a plurality of different positions for the crystalline region using a scanning electron microscope (SEM) as the crystalline region is moved to different positions. Relevant regions are extracted from the whole images. The images of the relevant regions are stitched together to form a composite map of a full electron channeling pattern representative of the crystalline region wherein the electronic channeling pattern is provided due to an increase in effective angular range between a SEM beam and a surface of the crystal region.
    Type: Grant
    Filed: January 24, 2017
    Date of Patent: November 13, 2018
    Assignee: International Business Machines Corporation
    Inventors: Stephen W. Bedell, Kunal Mukherjee, John A. Ott, Devendra K. Sadana, Brent A. Wacaser
  • Patent number: 10109737
    Abstract: A method of forming high germanium content silicon germanium alloy fins with controlled insulator layer recessing is provided. A silicon germanium alloy (SiGe) layer having a first germanium content is provided on a surface of an insulator layer using a first condensation process. Following the formation of a hard mask layer portion on the SiGe layer, a second condensation process is performed to convert a portion of the SiGe layer into a SiGe fin of a second germanium content that is greater than the first germanium content and other portions of the SiGe layer into a shell oxide structure located on sidewalls of the SiGe fin. After forming a fin placeholder material, a portion of each shell oxide structure is removed, while maintaining a lower portion of each shell oxide structure at the footprint of the SiGe fin.
    Type: Grant
    Filed: June 5, 2017
    Date of Patent: October 23, 2018
    Assignee: International Business Machines Corporation
    Inventors: Pouya Hashemi, Renee T. Mo, John A. Ott, Alexander Reznicek
  • Publication number: 20180277367
    Abstract: A method for reducing crystalline defects in a semiconductor structure is presented. The method includes epitaxially growing a first crystalline material over a crystalline substrate, epitaxially growing a second crystalline material over the first crystalline material, and patterning and removing portions of the second crystalline material to form openings. The method further includes converting the first crystalline material into a non-crystalline material, depositing a thermally stable material in the openings, depositing a capping layer over the second crystalline material and the thermally stable material to form a substantially enclosed semiconductor structure, and annealing the substantially enclosed semiconductor structure.
    Type: Application
    Filed: March 23, 2017
    Publication date: September 27, 2018
    Inventors: Stephen W. Bedell, Cheng-Wei Cheng, Kunal Mukherjee, John A. Ott, Devendra K. Sadana, Brent A. Wacaser
  • Publication number: 20180277368
    Abstract: A method for reducing crystalline defects in a semiconductor structure is presented. The method includes epitaxially growing a first crystalline material over a crystalline substrate, epitaxially growing a second crystalline material over the first crystalline material, and patterning and removing portions of the second crystalline material to form openings. The method further includes converting the first crystalline material into a non-crystalline material, depositing a thermally stable material in the openings, depositing a capping layer over the second crystalline material and the thermally stable material to form a substantially enclosed semiconductor structure, and annealing the substantially enclosed semiconductor structure.
    Type: Application
    Filed: November 7, 2017
    Publication date: September 27, 2018
    Inventors: Stephen W. Bedell, Cheng-Wei Cheng, Kunal Mukherjee, John A. Ott, Devendra K. Sadana, Brent A. Wacaser
  • Publication number: 20180218900
    Abstract: A method for forming an epitaxial structure includes providing a two-dimensional material on a crystal semiconductor material and opening up portions of the two-dimensional material to expose the crystal semiconductor material. A structure is epitaxially grown in the portions opened up in the crystal semiconductor material such that the epitaxial growth is selective to the exposed crystal semiconductor material relative to the two-dimensional material.
    Type: Application
    Filed: March 26, 2018
    Publication date: August 2, 2018
    Inventors: Cheng-Wei Cheng, Jeehwan Kim, John A. Ott, Devendra K. Sadana
  • Publication number: 20180211378
    Abstract: A method for crystal analysis includes identifying a crystalline region on a device where an electronic channeling pattern is needed to be determined, acquiring a whole image for each of a plurality of different positions for the crystalline region using a scanning electron microscope (SEM) as the crystalline region is moved to different positions. Relevant regions are extracted from the whole images. The images of the relevant regions are stitched together to form a composite map of a full electron channeling pattern representative of the crystalline region wherein the electronic channeling pattern is provided due to an increase in effective angular range between a SEM beam and a surface of the crystal region.
    Type: Application
    Filed: October 30, 2017
    Publication date: July 26, 2018
    Inventors: Stephen W. Bedell, Kunal Mukherjee, John A. Ott, Devendra K. Sadana, Brent A. Wacaser
  • Publication number: 20180211376
    Abstract: A method for crystal analysis includes identifying a crystalline region on a device where an electronic channeling pattern is needed to be determined, acquiring a whole image for each of a plurality of different positions for the crystalline region using a scanning electron microscope (SEM) as the crystalline region is moved to different positions. Relevant regions are extracted from the whole images. The images of the relevant regions are stitched together to form a composite map of a full electron channeling pattern representative of the crystalline region wherein the electronic channeling pattern is provided due to an increase in effective angular range between a SEM beam and a surface of the crystal region.
    Type: Application
    Filed: January 24, 2017
    Publication date: July 26, 2018
    Inventors: Stephen W. Bedell, Kunal Mukherjee, John A. Ott, Devendra K. Sadana, Brent A. Wacaser
  • Patent number: 9984941
    Abstract: A semiconductor material stack of, from bottom to top, a first semiconductor material having a first lattice constant and a second semiconductor material having a second lattice constant that may or may not differ from the first lattice constant and is selected from an III-V compound semiconductor and germanium is provided. The second semiconductor material of the semiconductor material stack is then scanned using an atomic force microscope (AFM) operating in a tapping mode to provide an AFM image of the second semiconductor material of the semiconductor material stack. The resultant AFM image is then analyzed and crystal defects at a topmost surface of the second semiconductor material of the semiconductor material stack can be measured.
    Type: Grant
    Filed: May 31, 2016
    Date of Patent: May 29, 2018
    Assignee: International Business Machines Corporation
    Inventors: Stephen W. Bedell, John A. Ott
  • Publication number: 20180143634
    Abstract: An autonomous path treatment system and associated path treatment method uses a mobile path recording device having a locator, a processor and firmware to capture a sequence of coordinates and directions of travel of a path as the mobile device is moved along the path and generate a path program file. The system also has an autonomous path treatment robot having: a treatment mechanism for treating the path; a controller having a processor and memory storing firmware that when executed obeys steps of the path program file to control the motor and the treatment mechanism to treat the path; and a server configured to execute a path program to process the captured sequence of coordinates and directions into the path program file containing instructions for controlling the autonomous path treatment robot to treat the path based upon the coordinates.
    Type: Application
    Filed: November 9, 2017
    Publication date: May 24, 2018
    Inventors: Michael John Ott, Clinton James Ott, Zachary Dax Olkin, Terry Michael Olkin
  • Patent number: 9972688
    Abstract: A method of reducing defects in epitaxially grown III-V semiconductor material comprising: epitaxially growing a III-V semiconductor on a substrate; patterning and removing portions of the III-V semiconductor to form openings; depositing thermally stable material in the openings; depositing a capping layer over the semiconductor material and thermally stable material to form a substantially enclosed semiconductor; and annealing the substantially enclosed semiconductor.
    Type: Grant
    Filed: November 29, 2016
    Date of Patent: May 15, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: John A. Ott, Devendra K. Sadana, Brent A. Wacaser