Patents by Inventor John A. Ott

John A. Ott has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9859367
    Abstract: A method for forming nanowires includes forming a plurality of epitaxial layers on a substrate, the layers including alternating material layers with high and low Ge concentration and patterning the plurality of layers to form fins. The fins are etched to form recesses in low Ge concentration layers to form pillars between high Ge concentration layers. The pillars are converted to dielectric pillars. A conformal material is formed in the recesses and on the dielectric pillars. The high Ge concentration layers are condensed to form hexagonal Ge wires with (111) facets. The (111) facets are exposed to form nanowires.
    Type: Grant
    Filed: August 29, 2016
    Date of Patent: January 2, 2018
    Assignee: International Business Machines Corporation
    Inventors: Takashi Ando, Pouya Hashemi, John A. Ott, Alexander Reznicek
  • Patent number: 9859091
    Abstract: An automatic method is provided to align a semiconductor crystalline substrate for electron channeling contrast imaging (ECCI) in regions where an electron channeling pattern cannot be reliably obtained but crystalline defects need to be imaged. The automatic semiconductor crystalline substrate alignment method is more reproducible and faster than the current operator intensive process for ECCI alignment routines. Also, the automatic semiconductor crystalline substrate alignment method increases the throughput of ECCI.
    Type: Grant
    Filed: June 20, 2016
    Date of Patent: January 2, 2018
    Assignee: International Business Machines Corporation
    Inventors: Stephen W. Bedell, Kunal Mukherjee, John A. Ott, Devendra K. Sadana, Brent A. Wacaser
  • Publication number: 20170365441
    Abstract: An automatic method is provided to align a semiconductor crystalline substrate for electron channeling contrast imaging (ECCI) in regions where an electron channeling pattern cannot be reliably obtained but crystalline defects need to be imaged. The automatic semiconductor crystalline substrate alignment method is more reproducible and faster than the current operator intensive process for ECCI alignment routines. Also, the automatic semiconductor crystalline substrate alignment method increases the throughput of ECCI.
    Type: Application
    Filed: June 20, 2016
    Publication date: December 21, 2017
    Inventors: Stephen W. Bedell, Kunal Mukherjee, John A. Ott, Devendra K. Sadana, Brent A. Wacaser
  • Patent number: 9820794
    Abstract: Various devices, systems, and methods are capable of killing tumor cells by delivering cell-disrupting agents into a tumor in an inward direction from a peripheral border about the tumor. In some examples, a covering that includes one or more emissive elements encompasses at least a portion of a tumor such that the emissive element is directed inwardly toward the tumor so as to be able to introduce a cell-disrupting agent into the tumor. In further examples, the covering is incorporated into a glove.
    Type: Grant
    Filed: November 21, 2011
    Date of Patent: November 21, 2017
    Assignee: Intermountain Invention Management, LLC
    Inventors: Mark John Ott, Troy J. Orr
  • Patent number: 9812530
    Abstract: Thermal condensation is employed to obtain a finned structure including strained silicon germanium fins having vertical side walls and a germanium content that may be high relative to silicon. A hard mask is used directly on a low-germanium content silicon germanium layer. The hard mask is patterned and fins are formed beneath the hard mask from the silicon germanium layer. Thermal condensation in an oxidizing ambient causes the formation of regions beneath the hard mask that have a high germanium content. The hard mask is trimmed to a target critical dimension. The regions beneath the hard mask and adjoining oxide material are subjected to reactive ion etch, resulting in the formation of high-germanium content fins with planar, vertically extending sidewalls.
    Type: Grant
    Filed: March 13, 2016
    Date of Patent: November 7, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Karthik Balakrishnan, John Bruley, Pouya Hashemi, Ali Khakifirooz, John A. Ott, Alexander Reznicek
  • Publication number: 20170271502
    Abstract: A method of forming high germanium content silicon germanium alloy fins with controlled insulator layer recessing is provided. A silicon germanium alloy (SiGe) layer having a first germanium content is provided on a surface of an insulator layer using a first condensation process. Following the formation of a hard mask layer portion on the SiGe layer, a second condensation process is performed to convert a portion of the SiGe layer into a SiGe fin of a second germanium content that is greater than the first germanium content and other portions of the SiGe layer into a shell oxide structure located on sidewalls of the SiGe fin. After forming a fin placeholder material, a portion of each shell oxide structure is removed, while maintaining a lower portion of each shell oxide structure at the footprint of the SiGe fin.
    Type: Application
    Filed: June 5, 2017
    Publication date: September 21, 2017
    Inventors: Pouya Hashemi, Renee T. Mo, John A. Ott, Alexander Reznicek
  • Patent number: 9761661
    Abstract: A method for forming nanowires includes forming a plurality of epitaxial layers on a substrate, the layers including alternating material layers with high and low Ge concentration and patterning the plurality of layers to form fins. The fins are etched to form recesses in low Ge concentration layers to form pillars between high Ge concentration layers. The pillars are converted to dielectric pillars. A conformal material is formed in the recesses and on the dielectric pillars. The high Ge concentration layers are condensed to form hexagonal Ge wires with (111) facets. The (111) facets are exposed to form nanowires.
    Type: Grant
    Filed: August 29, 2016
    Date of Patent: September 12, 2017
    Assignee: International Business Machines Corporation
    Inventors: Takashi Ando, Pouya Hashemi, John A. Ott, Alexander Reznicek
  • Patent number: 9741532
    Abstract: A multi-beam electron microscope for ECCI is provided. The electron microscope has a platform, on which a crystalline sample is placed. At least a first electron source and a second electron source of the electron microscope are mounted to a housing. The housing is tiltable with respect to a longitudinal direction through a pivot for forming a fulcrum, such that the first electron source and the second electron source are tilted simultaneously and are substantially equally distanced from the platform along a vertical axis when the housing is tilted. The electron microscope also has electron beam focusing assemblies for focusing the electron beams generated by the electron sources onto the crystalline sample to generate backscattered electrons. The electron microscope also has detectors for detecting the backscattered electrons.
    Type: Grant
    Filed: June 17, 2016
    Date of Patent: August 22, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Stephen W. Bedell, Kunal Mukherjee, John A. Ott, Devendra K. Sadana, Brent A. Wacaser
  • Patent number: 9739728
    Abstract: Imaging and processing techniques are employed to identify crystalline defects obtained by ECCI from surrounding topography and is combined with defect counting and automatic classification.
    Type: Grant
    Filed: June 20, 2016
    Date of Patent: August 22, 2017
    Assignee: International Business Machines Corporation
    Inventors: Stephen W. Bedell, Renee T. Mo, Kunal Mukherjee, John A. Ott, Devendra K. Sadana, Brent A. Wacaser
  • Patent number: 9680018
    Abstract: A method of forming high germanium content silicon germanium alloy fins with controlled insulator layer recessing is provided. A silicon germanium alloy (SiGe) layer having a first germanium content is provided on a surface of an insulator layer using a first condensation process. Following the formation of a hard mask layer portion on the SiGe layer, a second condensation process is performed to convert a portion of the SiGe layer into a SiGe fin of a second germanium content that is greater than the first germanium content and other portions of the SiGe layer into a shell oxide structure located on sidewalls of the SiGe fin. After forming a fin placeholder material, a portion of each shell oxide structure is removed, while maintaining a lower portion of each shell oxide structure at the footprint of the SiGe fin.
    Type: Grant
    Filed: September 21, 2015
    Date of Patent: June 13, 2017
    Assignee: International Business Machines Corporation
    Inventors: Pouya Hashemi, Renee T. Mo, John A. Ott, Alexander Reznicek
  • Publication number: 20170162657
    Abstract: A method of reducing defects in epitaxially grown III-V semiconductor material comprising: epitaxially growing a III-V semiconductor on a substrate; patterning and removing portions of the III-V semiconductor to form openings; depositing thermally stable material in the openings; depositing a capping layer over the semiconductor material and thermally stable material to form a substantially enclosed semiconductor; and annealing the substantially enclosed semiconductor.
    Type: Application
    Filed: November 29, 2016
    Publication date: June 8, 2017
    Inventors: JOHN A. OTT, DEVENDRA K. SADANA, BRENT A. WACASER
  • Publication number: 20170117360
    Abstract: A method for forming nanowires includes forming a plurality of epitaxial layers on a substrate, the layers including alternating material layers with high and low Ge concentration and patterning the plurality of layers to form fins. The fins are etched to form recesses in low Ge concentration layers to form pillars between high Ge concentration layers. The pillars are converted to dielectric pillars. A conformal material is formed in the recesses and on the dielectric pillars. The high Ge concentration layers are condensed to form hexagonal Ge wires with (111) facets. The (111) facets are exposed to form nanowires.
    Type: Application
    Filed: August 29, 2016
    Publication date: April 27, 2017
    Inventors: Takashi Ando, Pouya Hashemi, John A. Ott, Alexander Reznicek
  • Publication number: 20170117361
    Abstract: A method for forming nanowires includes forming a plurality of epitaxial layers on a substrate, the layers including alternating material layers with high and low Ge concentration and patterning the plurality of layers to form fins. The fins are etched to form recesses in low Ge concentration layers to form pillars between high Ge concentration layers. The pillars are converted to dielectric pillars. A conformal material is formed in the recesses and on the dielectric pillars. The high Ge concentration layers are condensed to form hexagonal Ge wires with (111) facets. The (111) facets are exposed to form nanowires.
    Type: Application
    Filed: August 29, 2016
    Publication date: April 27, 2017
    Inventors: Takashi Ando, Pouya Hashemi, John A. Ott, Alexander Reznicek
  • Patent number: 9608160
    Abstract: After forming patterned dielectric material structures over a (100) silicon substrate, portions of the silicon substrate that are not covered by the patterned dielectric material structures are removed to provide a plurality of openings within the silicon substrate. Each opening exposes a surface of the silicon substrate having a (111) crystalline plane. A buffer layer is then formed on the exposed surfaces of the patterned dielectric material structures and the silicon substrate. A dual phase Group III nitride structure including a cubic phase region is formed filling a space between each neighboring pair of the patterned dielectric material structures and one of the openings located beneath the space. Finally, at least one Group III nitride layer is epitaxially deposited over the cubic phase region of the dual phase Group III nitride structure.
    Type: Grant
    Filed: February 5, 2016
    Date of Patent: March 28, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Can Bayram, Cheng-Wei Cheng, Tayfun Gokmen, Ning Li, John A. Ott, Devendra K. Sadana, Kuen-Ting Shiu
  • Publication number: 20170084731
    Abstract: A method of forming high germanium content silicon germanium alloy fins with controlled insulator layer recessing is provided. A silicon germanium alloy (SiGe) layer having a first germanium content is provided on a surface of an insulator layer using a first condensation process. Following the formation of a hard mask layer portion on the SiGe layer, a second condensation process is performed to convert a portion of the SiGe layer into a SiGe fin of a second germanium content that is greater than the first germanium content and other portions of the SiGe layer into a shell oxide structure located on sidewalls of the SiGe fin. After forming a fin placeholder material, a portion of each shell oxide structure is removed, while maintaining a lower portion of each shell oxide structure at the footprint of the SiGe fin.
    Type: Application
    Filed: September 21, 2015
    Publication date: March 23, 2017
    Inventors: Pouya Hashemi, Renee T. Mo, John A. Ott, Alexander Reznicek
  • Publication number: 20170053796
    Abstract: A method for forming an epitaxial structure includes providing a two-dimensional material on a crystal semiconductor material and opening up portions of the two-dimensional material to expose the crystal semiconductor material. A structure is epitaxially grown in the portions opened up in the crystal semiconductor material such that the epitaxial growth is selective to the exposed crystal semiconductor material relative to the two-dimensional material.
    Type: Application
    Filed: November 3, 2016
    Publication date: February 23, 2017
    Inventors: Cheng-Wei Cheng, Jeehwan Kim, John A. Ott, Devendra K. Sadana
  • Patent number: 9574287
    Abstract: A method of forming an epitaxial semiconductor material that includes forming a graphene layer on a semiconductor and carbon containing substrate and depositing a metal containing monolayer on the graphene layer. An epitaxial layer of a gallium containing material is formed on the metal containing monolayer. A layered stack of the metal containing monolayer and the epitaxial layer of gallium containing material is cleaved from the graphene layer that is present on the semiconductor and carbon containing substrate.
    Type: Grant
    Filed: September 26, 2013
    Date of Patent: February 21, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Can Bayram, Christos D. Dimitrakopoulos, Keith E. Fogel, Jeehwan Kim, John A. Ott, Devendra K. Sadana
  • Patent number: 9553153
    Abstract: A method of reducing defects in epitaxially grown III-V semiconductor material comprising: epitaxially growing a III-V semiconductor on a substrate; patterning and removing portions of the III-V semiconductor to form openings; depositing thermally stable material in the openings; depositing a capping layer over the semiconductor material and thermally stable material to form a substantially enclosed semiconductor; and annealing the substantially enclosed semiconductor.
    Type: Grant
    Filed: December 2, 2015
    Date of Patent: January 24, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: John A. Ott, Devendra K. Sadana, Brent A. Wacaser
  • Patent number: 9530643
    Abstract: A method for forming an epitaxial structure includes providing a two-dimensional material on a crystal semiconductor material and opening up portions of the two-dimensional material to expose the crystal semiconductor material. A structure is epitaxially grown in the portions opened up in the crystal semiconductor material such that the epitaxial growth is selective to the exposed crystal semiconductor material relative to the two-dimensional material.
    Type: Grant
    Filed: March 12, 2015
    Date of Patent: December 27, 2016
    Assignee: International Business Machines Corporation
    Inventors: Cheng-Wei Cheng, Jeehwan Kim, John A. Ott, Devendra K. Sadana
  • Patent number: 9496263
    Abstract: A method for forming nanowires includes forming a plurality of epitaxial layers on a substrate, the layers including alternating material layers with high and low Ge concentration and patterning the plurality of layers to form fins. The fins are etched to form recesses in low Ge concentration layers to form pillars between high Ge concentration layers. The pillars are converted to dielectric pillars. A conformal material is formed in the recesses and on the dielectric pillars. The high Ge concentration layers are condensed to form hexagonal Ge wires with (111) facets. The (111) facets are exposed to form nanowires.
    Type: Grant
    Filed: October 23, 2015
    Date of Patent: November 15, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Takashi Ando, Pouya Hashemi, John A. Ott, Alexander Reznicek