Patents by Inventor John A. Smythe, III

John A. Smythe, III has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240006478
    Abstract: An example apparatus includes a first source/drain region and a second source/drain region formed in a substrate to form an active area of the apparatus. The first source/drain region and the second source/drain region are separated by a channel. The apparatus includes a gate opposing the channel. A sense line is coupled to the first source/drain region and a storage node is coupled to the second source/drain region. An isolation trench is adjacent to the active area. The trench includes a dielectric material with a conductive bias opposing the conductive bias of the channel in the active area.
    Type: Application
    Filed: September 18, 2023
    Publication date: January 4, 2024
    Inventors: Kamal M. Karda, Haitao Liu, Si-Woo Lee, Fatma Arzum Simsek-Ege, Deepak Chandra Pandey, Chandra V. Mouli, John A. Smythe, III
  • Patent number: 11769795
    Abstract: An example apparatus includes a first source/drain region and a second source/drain region formed in a substrate to form an active area of the apparatus. The first source/drain region and the second source/drain region are separated by a channel. The apparatus includes a gate opposing the channel. A sense line is coupled to the first source/drain region and a storage node is coupled to the second source/drain region. An isolation trench is adjacent to the active area. The trench includes a dielectric material with a conductive bias opposing the conductive bias of the channel in the active area.
    Type: Grant
    Filed: October 12, 2021
    Date of Patent: September 26, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Kamal M. Karda, Haitao Liu, Si-Woo Lee, Fatma Arzum Simsek-Ege, Deepak Chandra Pandey, Chandra V. Mouli, John A. Smythe, III
  • Patent number: 11476251
    Abstract: Systems, methods and apparatus are provided for a three-node access device in vertical three dimensional (3D) memory. An example method includes a method for forming arrays of vertically stacked memory cells, having horizontally oriented access devices and vertically oriented access lines. The method includes depositing alternating layers of a dielectric material and a sacrificial material in repeating iterations to form a vertical stack. An etchant process is used to form a first vertical opening exposing vertical sidewalls in the vertical stack adjacent a first region. The first region is selectively etched to form a first horizontal opening removing the sacrificial material a first horizontal distance back from the first vertical opening.
    Type: Grant
    Filed: August 6, 2020
    Date of Patent: October 18, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Scott E. Sills, John A. Smythe, III, Si-Woo Lee, Gurtej S. Sandhu, Armin Saeedi Vahdat
  • Publication number: 20220223602
    Abstract: Systems, methods, and apparatuses are provided for epitaxial single crystalline silicon growth for a horizontal access device. One example method includes depositing layers of a first dielectric material, a semiconductor material, and a second dielectric material to form a vertical stack, forming first vertical openings to form elongated vertical, pillar columns with first vertical sidewalls in the vertical stack, and forming second vertical openings through the vertical stack to expose second vertical sidewalls. Further, the example method includes selectively removing first portions of the semiconductor material from the second vertical openings to form horizontal openings with a remaining second portion of the semiconductor material at a distal end of the horizontal openings from the second vertical openings, and epitaxially growing single crystalline silicon within the horizontal openings from the distal end of the horizontal openings toward the second vertical openings to fill the horizontal openings.
    Type: Application
    Filed: March 28, 2022
    Publication date: July 14, 2022
    Inventors: Armin Saeedi Vahdat, Gurtej S. Sandhu, Scott E. Sills, Si-Woo Lee, John A. Smythe, III
  • Patent number: 11329051
    Abstract: Systems, methods and apparatus are provided for a three-node access device in vertical three-dimensional (3D) memory. An example method includes a method for forming arrays of vertically stacked memory cells, having horizontally oriented access devices and vertically oriented access lines. The method includes depositing alternating layers of a dielectric material and a sacrificial material to form a vertical stack. Forming a plurality of first vertical openings to form elongated vertical, pillar columns with sidewalls in the vertical stack. Conformally depositing a gate dielectric in the plurality of first vertical openings. Forming a conductive material on the gate dielectric. Removing portions of the conductive material to form a plurality of separate, vertical access lines. Repairing a first side of the gate dielectric exposed where the conductive material was removed. Forming a second vertical opening to expose sidewalls adjacent a first region of the sacrificial material.
    Type: Grant
    Filed: August 28, 2020
    Date of Patent: May 10, 2022
    Assignee: Micron Technology, Inc.
    Inventors: John A. Smythe, III, Gurtej S. Sandhu, Armin Saeedi Vahdat, Si-Woo Lee, Scott E. Sills
  • Publication number: 20220102384
    Abstract: Systems, methods, and apparatuses are provided for epitaxial single crystalline silicon growth for memory arrays. One example method includes forming logic circuitry on a silicon substrate in a first working surface and depositing an isolation material on the first working surface to encapsulate the logic circuitry and to form a second working surface above the first working surface. Further, the example method includes etching the isolation material to form a vertical opening through the isolation material and epitaxially growing single crystalline silicon from the silicon substrate and horizontally on the second working surface in a first, a second, and a third direction to cover the second working surface. The example method further includes removing a portion of the epitaxially grown single crystalline silicon to partition distinct and separate third working surface areas in which to form memory cell components and forming storage nodes above the memory cell components.
    Type: Application
    Filed: September 2, 2021
    Publication date: March 31, 2022
    Inventors: Glen H. Walters, John A. Smythe III, Scott E. Sills, John F. Kaeding
  • Publication number: 20220102356
    Abstract: Systems, methods, and apparatuses are provided for epitaxial single crystalline silicon growth for a horizontal access device. One example method includes depositing layers of a first dielectric material, a semiconductor material, and a second dielectric material to form a vertical stack, forming first vertical openings to form elongated vertical, pillar columns with first vertical sidewalls in the vertical stack, and forming second vertical openings through the vertical stack to expose second vertical sidewalls. Further, the example method includes selectively removing first portions of the semiconductor material from the second vertical openings to form horizontal openings with a remaining second portion of the semiconductor material at a distal end of the horizontal openings from the second vertical openings, and epitaxially growing single crystalline silicon within the horizontal openings from the distal end of the horizontal openings toward the second vertical openings to fill the horizontal openings.
    Type: Application
    Filed: September 29, 2020
    Publication date: March 31, 2022
    Inventors: Armin Saeedi Vahdat, Gurtej S. Sandhu, Scott E. Sills, Si-Woo Lee, John A. Smythe III
  • Patent number: 11289491
    Abstract: Systems, methods, and apparatuses are provided for epitaxial single crystalline silicon growth for a horizontal access device. One example method includes depositing layers of a first dielectric material, a semiconductor material, and a second dielectric material to form a vertical stack, forming first vertical openings to form elongated vertical, pillar columns with first vertical sidewalls in the vertical stack, and forming second vertical openings through the vertical stack to expose second vertical sidewalls. Further, the example method includes selectively removing first portions of the semiconductor material from the second vertical openings to form horizontal openings with a remaining second portion of the semiconductor material at a distal end of the horizontal openings from the second vertical openings, and epitaxially growing single crystalline silicon within the horizontal openings from the distal end of the horizontal openings toward the second vertical openings to fill the horizontal openings.
    Type: Grant
    Filed: September 29, 2020
    Date of Patent: March 29, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Armin Saeedi Vahdat, Gurtej S. Sandhu, Scott E. Sills, Si-Woo Lee, John A. Smythe, III
  • Publication number: 20220068933
    Abstract: Systems, methods and apparatus are provided for a three-node access device in vertical three-dimensional (3D) memory. An example method includes a method for forming arrays of vertically stacked memory cells, having horizontally oriented access devices and vertically oriented access lines. The method includes depositing alternating layers of a dielectric material and a sacrificial material to form a vertical stack. Forming a plurality of first vertical openings to form elongated vertical, pillar columns with sidewalls in the vertical stack. Conformally depositing a gate dielectric in the plurality of first vertical openings. Forming a conductive material on the gate dielectric. Removing portions of the conductive material to form a plurality of separate, vertical access lines. Repairing a first side of the gate dielectric exposed where the conductive material was removed. Forming a second vertical opening to expose sidewalls adjacent a first region of the sacrificial material.
    Type: Application
    Filed: August 28, 2020
    Publication date: March 3, 2022
    Inventors: John A. Smythe III, Gurtej S. Sandhu, Armin Saeedi Vahdat, Si-Woo Lee, Scott E. Sills
  • Publication number: 20220045062
    Abstract: Systems, methods and apparatus are provided for storage node after horizontally oriented, three-node access device formation in vertical three dimensional (3D) memory. An example method includes a method for forming arrays of vertically stacked memory cells, having horizontally oriented access devices and vertically oriented access lines. The method includes depositing alternating layers of a dielectric material and a sacrificial material to form a vertical stack. A plurality of first vertical openings are formed through the vertical stack to form elongated vertical, pillar columns with sidewalls in the vertical stack. A first conductive material is conformally deposited on a gate dielectric material in the first vertical openings. Portions of the first conductive material are removed to form a plurality of separate, vertical access lines along the sidewalls of the elongated vertical, pillar columns.
    Type: Application
    Filed: August 6, 2020
    Publication date: February 10, 2022
    Inventors: Armin Saeedi Vahdat, John A. Smythe III, Si-Woo Lee, Gurtej S. Sandhu, Scott E. Sills
  • Publication number: 20220045069
    Abstract: Systems, methods and apparatus are provided for a three-node access device in vertical three dimensional (3D) memory. An example method includes a method for forming arrays of vertically stacked memory cells, having horizontally oriented access devices and vertically oriented access lines. The method includes depositing alternating layers of a dielectric material and a sacrificial material in repeating iterations to form a vertical stack. An etchant process is used to form a first vertical opening exposing vertical sidewalls in the vertical stack adjacent a first region of the sacrificial material. The first region is selectively etched to form a first horizontal opening removing the sacrificial material a first horizontal distance back from the first vertical opening.
    Type: Application
    Filed: August 6, 2020
    Publication date: February 10, 2022
    Inventors: Scott E. Sills, John A. Smythe, III, Si-Woo Lee, Gurtej S. Sandhu, Armin Saeedi Vahdat
  • Publication number: 20220045060
    Abstract: Systems, methods and apparatus are provided for a three-node access device in vertical three dimensional (3D) memory. An example method includes a method for forming arrays of vertically stacked memory cells, having horizontally oriented access devices and vertically oriented access lines. The method includes depositing alternating layers of a dielectric material and a sacrificial material in repeating iterations to form a vertical stack. An etchant process is used to form a first vertical opening exposing vertical sidewalls in the vertical stack adjacent a first region. The first region is selectively etched to form a first horizontal opening removing the sacrificial material a first horizontal distance back from the first vertical opening.
    Type: Application
    Filed: August 6, 2020
    Publication date: February 10, 2022
    Inventors: Scott E. Sills, John A. Smythe, III, Si-Woo Lee, Gurtej S. Sandhu, Armin Saeedi Vahdat
  • Publication number: 20220045165
    Abstract: An example apparatus includes a first source/drain region and a second source/drain region formed in a substrate to form an active area of the apparatus. The first source/drain region and the second source/drain region are separated by a channel. The apparatus includes a gate opposing the channel. A sense line is coupled to the first source/drain region and a storage node is coupled to the second source/drain region. An isolation trench is adjacent to the active area. The trench includes a dielectric material with a conductive bias opposing the conductive bias of the channel in the active area.
    Type: Application
    Filed: October 12, 2021
    Publication date: February 10, 2022
    Inventors: Kamal M. Karda, Haitao Liu, Si-Woo Lee, Fatma Arzum Simsek-Ege, Deepak Chandra Pandey, Chandra V. Mouli, John A. Smythe, III
  • Publication number: 20220045061
    Abstract: Systems, methods and apparatus are provided for a three-node access device in vertical three dimensional (3D) memory. An example method includes a method for forming arrays of vertically stacked memory cells, having horizontally oriented access devices and vertically oriented access lines. The three-node access devices include a first source/drain region (1) and a second source/drain region (2) separated by a channel and gates (3) opposing the channel, but do not have a direct, electrical body contact to a body region and/or channel of the access devices. The method includes depositing alternating layers of a dielectric material and a sacrificial semiconductor material in repeating iterations to form a vertical stack, a first region of the sacrificial semiconductor material in which to form a first and a second source/drain region separated laterally by a channel region. An etchant process is used to form a first vertical opening exposing vertical sidewalls in the vertical stack adjacent the first region.
    Type: Application
    Filed: August 6, 2020
    Publication date: February 10, 2022
    Inventors: Si-Woo Lee, John A. Smythe, III, Scott E. Sills, Gurtej S. Sandhu, Armin Saeedi Vahdat
  • Patent number: 11239117
    Abstract: Systems, methods, and apparatus are provided for storage node after horizontally oriented, three-node access device formation in vertical three dimensional (3D) memory. An example method includes a method for forming arrays of vertically stacked memory cells, having horizontally oriented access devices and vertically oriented access lines. The method includes depositing alternating layers of a dielectric material and a sacrificial semiconductor material to form a vertical stack. A first vertical opening is formed through the vertical stack to expose a first region of the sacrificial semiconductor material. The first region is selectively removed to form a first horizontal opening in which to replace a sacrificial gate dielectric material, form a source/drain conductive contact material, a channel conductive material, and a digit line conductive contact material of the three-node access device.
    Type: Grant
    Filed: August 27, 2020
    Date of Patent: February 1, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Armin Saeedi Vahdat, John A. Smythe, III, Si-Woo Lee, Gurtej S. Sandhu, Scott E. Sills
  • Patent number: 11227864
    Abstract: Systems, methods and apparatus are provided for storage node after horizontally oriented, three-node access device formation in vertical three dimensional (3D) memory. An example method includes a method for forming arrays of vertically stacked memory cells, having horizontally oriented access devices and vertically oriented access lines. The method includes forming elongated vertical, pillar columns with sidewalls in a vertical stack. A first conductive material is conformally deposited on a gate dielectric material in the first vertical openings. Portions of the first conductive material are removed to form a plurality of separate, vertical access lines along the sidewalls of the elongated vertical, pillar columns. A second vertical opening is formed through the vertical stack to expose a first region of the sacrificial material. A third vertical opening is formed through the vertical stack to in which to form a storage node electrically coupled to the first source/drain material.
    Type: Grant
    Filed: August 6, 2020
    Date of Patent: January 18, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Armin Saeedi Vahdat, John A. Smythe, III, Si-Woo Lee, Gurtej S. Sandhu, Scott E. Sills
  • Patent number: 11171206
    Abstract: An example apparatus includes a first source/drain region and a second source/drain region formed in a substrate to form an active area of the apparatus. The first source/drain region and the second source/drain region are separated by a channel. The apparatus includes a gate opposing the channel. A sense line is coupled to the first source/drain region and a storage node is coupled to the second source/drain region. An isolation trench is adjacent to the active area. The trench includes a dielectric material with a conductive bias opposing the conductive bias of the channel in the active area.
    Type: Grant
    Filed: July 11, 2019
    Date of Patent: November 9, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Kamal M. Karda, Haitao Liu, Si-Woo Lee, Fatma Arzum Simsek-Ege, Deepak Chandra Pandey, Chandra V. Mouli, John A. Smythe, III
  • Patent number: 11081364
    Abstract: Systems, apparatuses, and methods related to reduction of crystal growth resulting from annealing a conductive material are described. An example apparatus includes a conductive material selected to have an electrical resistance that is reduced as a result of annealing. A stabilizing material may be formed over a surface of the conductive material. The stabilizing material may be selected to have properties that include stabilization of the reduced electrical resistance of the conductive material and reduction of a degree of freedom of crystal growth relative to the surface resulting from recrystallization of the conductive material during the annealing.
    Type: Grant
    Filed: February 6, 2019
    Date of Patent: August 3, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Marko Milojevic, John A. Smythe, III
  • Patent number: 10964536
    Abstract: Methods, apparatuses, and systems related to formation of an atomic layer of germanium (Ge) on a substrate material are described. An example method includes introducing, into a semiconductor processing chamber housing a substrate material having a high aspect ratio, a reducing agent, and introducing, into the semiconductor processing chamber, a germanium amidinate precursor. The example method further includes forming an atomic layer of germanium on the substrate material resulting from a reaction of the reducing agent and the germanium amidinate precursor.
    Type: Grant
    Filed: February 6, 2019
    Date of Patent: March 30, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Francois H. Fabreguette, Paul A. Paduano, Gurtej S. Sandhu, John A. Smythe, III, Matthew N. Rocklein
  • Publication number: 20210013305
    Abstract: An example apparatus includes a first source/drain region and a second source/drain region formed in a substrate to form an active area of the apparatus. The first source/drain region and the second source/drain region are separated by a channel. The apparatus includes a gate opposing the channel. A sense line is coupled to the first source/drain region and a storage node is coupled to the second source/drain region. An isolation trench is adjacent to the active area. The trench includes a dielectric material with a conductive bias opposing the conductive bias of the channel in the active area.
    Type: Application
    Filed: July 11, 2019
    Publication date: January 14, 2021
    Inventors: Kamal M. Karda, Haitao Liu, Si-Woo Lee, Fatma Arzum Simsek-Ege, Deepak Chandra Pandey, Chandra V. Mouli, John A. Smythe, III