Patents by Inventor John A. Smythe, III
John A. Smythe, III has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20200251334Abstract: Methods, apparatuses, and systems related to formation of an atomic layer of germanium (Ge) on a substrate material are described. An example method includes introducing, into a semiconductor processing chamber housing a substrate material having a high aspect ratio, a reducing agent, and introducing, into the semiconductor processing chamber, a germanium amidinate precursor. The example method further includes forming an atomic layer of germanium on the substrate material resulting from a reaction of the reducing agent and the germanium amidinate precursor.Type: ApplicationFiled: February 6, 2019Publication date: August 6, 2020Inventors: Francois H. Fabreguette, Paul A. Paduano, Gurtej S. Sandhu, John A. Smythe, III, Matthew N. Rocklein
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Publication number: 20200251349Abstract: Systems, apparatuses, and methods related to reduction of crystal growth resulting from annealing a conductive material are described. An example apparatus includes a conductive material selected to have an electrical resistance that is reduced as a result of annealing. A stabilizing material may be formed over a surface of the conductive material. The stabilizing material may be selected to have properties that include stabilization of the reduced electrical resistance of the conductive material and reduction of a degree of freedom of crystal growth relative to the surface resulting from recrystallization of the conductive material during the annealing.Type: ApplicationFiled: February 6, 2019Publication date: August 6, 2020Inventors: Marko Milojevic, John A. Smythe, III
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Patent number: 9634250Abstract: The present disclosure includes a high density resistive random access memory (RRAM) device, as well as methods of fabricating a high density RRAM device. One method of forming an RRAM device includes forming a resistive element having a metal-metal oxide interface. Forming the resistive element includes forming an insulative material over the first electrode, and forming a via in the insulative material. The via is conformally filled with a metal material, and the metal material is planarized to within the via. A portion of the metal material within the via is selectively treated to create a metal-metal oxide interface within the via. A second electrode is formed over the resistive element.Type: GrantFiled: June 30, 2016Date of Patent: April 25, 2017Assignee: Micron Technology, Inc.Inventors: Joseph N. Greeley, John A. Smythe, III
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Patent number: 9514976Abstract: Embodiments of the disclosure include a shallow trench isolation structure having a dielectric material with energetic species implanted to a predetermined depth of the dielectric material. Embodiments further include methods of fabricating the trench structures with the implant of energetic species to the predetermined depth. In various embodiments the implant of energetic species is used to densify the dielectric material to provide a uniform wet etch rate across the surface of the dielectric material. Embodiments also include memory devices, integrated circuits, and electronic systems that include shallow trench isolation structures having the dielectric material with the high flux of energetic species implanted to the predetermined depth of the dielectric material.Type: GrantFiled: February 26, 2014Date of Patent: December 6, 2016Assignee: Micron Technology, Inc.Inventors: Gurtej S. Sandhu, John A. Smythe, III
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Publication number: 20160315258Abstract: The present disclosure includes a high density resistive random access memory (RRAM) device, as well as methods of fabricating a high density RRAM device. One method of forming an RRAM device includes forming a resistive element having a metal-metal oxide interface. Forming the resistive element includes forming an insulative material over the first electrode, and forming a via in the insulative material. The via is conformally filled with a metal material, and the metal material is planarized to within the via. A portion of the metal material within the via is selectively treated to create a metal-metal oxide interface within the via. A second electrode is formed over the resistive element.Type: ApplicationFiled: June 30, 2016Publication date: October 27, 2016Inventors: Joseph N. Greeley, John A. Smythe, III
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Patent number: 9419219Abstract: The present disclosure includes a high density resistive random access memory (RRAM) device, as well as methods of fabricating a high density RRAM device. One method of forming an RRAM device includes forming a resistive element having a metal-metal oxide interface. Forming the resistive element includes forming an insulative material over the first electrode, and forming a via in the insulative material. The via is conformally filled with a metal material, and the metal material is planarized to within the via. A portion of the metal material within the via is selectively treated to create a metal-metal oxide interface within the via. A second electrode is formed over the resistive element.Type: GrantFiled: August 19, 2015Date of Patent: August 16, 2016Assignee: Micron Technology, Inc.Inventors: Joseph N. Greeley, John A. Smythe, III
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Publication number: 20160155619Abstract: Forming memory using high power impulse magnetron sputtering is described herein. One or more method embodiments include forming a resistive memory material on a structure using high power impulse magnetron sputtering (HIPIMS), wherein the resistive memory material is formed on the structure in an environment having a temperature of approximately 400 degrees Celsius or less.Type: ApplicationFiled: January 4, 2016Publication date: June 2, 2016Inventors: Yongjun Jeff Hu, Everett A. McTeer, John A. Smythe, III, Gurtej S. Sandhu
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Patent number: 9343677Abstract: The present disclosure includes GCIB-treated resistive devices, devices utilizing GCIB-treated resistive devices (e.g., as switches, memory cells), and methods for forming the GCIB-treated resistive devices. One method of forming a GCIB-treated resistive device includes forming a lower electrode, and forming an oxide material on the lower electrode. The oxide material is exposed to a gas cluster ion beam (GCIB) until a change in resistance of a first portion of the oxide material relative to the resistance of a second portion of the oxide material. An upper electrode is formed on the first portion.Type: GrantFiled: January 14, 2015Date of Patent: May 17, 2016Assignee: Micron Technology, Inc.Inventors: John A. Smythe, III, Gurtej S. Sandhu
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Patent number: 9249498Abstract: Forming memory using high power impulse magnetron sputtering is described herein. One or more method embodiments include forming a resistive memory material on a structure using high power impulse magnetron sputtering (HIPIMS), wherein the resistive memory material is formed on the structure in an environment having a temperature of approximately 400 degrees Celsius or less.Type: GrantFiled: June 28, 2010Date of Patent: February 2, 2016Assignee: Micron Technology, Inc.Inventors: Yongjun Jeff Hu, Everett A. McTeer, John A. Smythe, III, Gurtej S. Sandhu
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Publication number: 20150357568Abstract: The present disclosure includes a high density resistive random access memory (RRAM) device, as well as methods of fabricating a high density RRAM device. One method of forming an RRAM device includes forming a resistive element having a metal-metal oxide interface. Forming the resistive element includes forming an insulative material over the first electrode, and forming a via in the insulative material. The via is conformally filled with a metal material, and the metal material is planarized to within the via. A portion of the metal material within the via is selectively treated to create a metal-metal oxide interface within the via. A second electrode is formed over the resistive element.Type: ApplicationFiled: August 19, 2015Publication date: December 10, 2015Inventors: Joseph N. Greeley, John A. Smythe, III
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Patent number: 9142770Abstract: The present disclosure includes a high density resistive random access memory (RRAM) device, as well as methods of fabricating a high density RRAM device. One method of forming an RRAM device includes forming a resistive element having a metal-metal oxide interface. Forming the resistive element includes forming an insulative material over the first electrode, and forming a via in the insulative material. The via is conformally filled with a metal material, and the metal material is planarized to within the via. A portion of the metal material within the via is selectively treated to create a metal-metal oxide interface within the via. A second electrode is formed over the resistive element.Type: GrantFiled: April 28, 2014Date of Patent: September 22, 2015Assignee: Micron Technology, Inc.Inventors: Joseph N. Greeley, John A. Smythe, III
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Patent number: 9087989Abstract: The present disclosure includes GCIB-treated resistive devices, devices utilizing GCIB-treated resistive devices (e.g., as switches, memory cells), and methods for forming the GCIB-treated resistive devices. One method of forming a GCIB-treated resistive device includes forming a lower electrode, and forming an oxide material on the lower electrode. The oxide material is exposed to a gas cluster ion beam (GCIB) until a change in resistance of a first portion of the oxide material relative to the resistance of a second portion of the oxide material. An upper electrode is formed on the first portion.Type: GrantFiled: October 31, 2013Date of Patent: July 21, 2015Assignee: Micron Technology, Inc.Inventors: John A Smythe, III, Gurtej S Sandhu
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Publication number: 20150200360Abstract: The present disclosure includes GCIB-treated resistive devices, devices utilizing GCIB-treated resistive devices (e.g., as switches, memory cells), and methods for forming the GCIB-treated resistive devices. One method of forming a GCIB-treated resistive device includes forming a lower electrode, and forming an oxide material on the lower electrode. The oxide material is exposed to a gas cluster ion beam (GCIB) until a change in resistance of a first portion of the oxide material relative to the resistance of a second portion of the oxide material. An upper electrode is formed on the first portion.Type: ApplicationFiled: January 14, 2015Publication date: July 16, 2015Inventors: John A. Smythe, III, Gurtej S. Sandhu
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Publication number: 20140319446Abstract: The present disclosure includes a high density resistive random access memory (RRAM) device, as well as methods of fabricating a high density RRAM device. One method of forming an RRAM device includes forming a resistive element having a metal-metal oxide interface. Forming the resistive element includes forming an insulative material over the first electrode, and forming a via in the insulative material. The via is conformally filled with a metal material, and the metal material is planarized to within the via. A portion of the metal material within the via is selectively treated to create a metal-metal oxide interface within the via. A second electrode is formed over the resistive element.Type: ApplicationFiled: April 28, 2014Publication date: October 30, 2014Applicant: Micron Technology, Inc.Inventors: Joseph N. Greeley, John A. Smythe, III
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Publication number: 20140241053Abstract: Embodiments of the disclosure include a shallow trench isolation structure having a dielectric material with energetic species implanted to a predetermined depth of the dielectric material. Embodiments further include methods of fabricating the trench structures with the implant of energetic species to the predetermined depth. In various embodiments the implant of energetic species is used to densify the dielectric material to provide a uniform wet etch rate across the surface of the dielectric material. Embodiments also include memory devices, integrated circuits, and electronic systems that include shallow trench isolation structures having the dielectric material with the high flux of energetic species implanted to the predetermined depth of the dielectric material.Type: ApplicationFiled: February 26, 2014Publication date: August 28, 2014Applicant: Micron Technology, Inc.Inventors: Gurtej S. Sandhu, John A. Smythe, III
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Publication number: 20140141590Abstract: The present disclosure includes GCIB-treated resistive devices, devices utilizing GCIB-treated resistive devices (e.g., as switches, memory cells), and methods for forming the GCIB-treated resistive devices. One method of forming a GCIB-treated resistive device includes forming a lower electrode, and forming an oxide material on the lower electrode. The oxide material is exposed to a gas cluster ion beam (GCIB) until a change in resistance of a first portion of the oxide material relative to the resistance of a second portion of the oxide material. An upper electrode is formed on the first portion.Type: ApplicationFiled: October 31, 2013Publication date: May 22, 2014Applicant: Micron Technology, IncInventors: John A. Smythe, III, Gurtej S. Sandhu
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Patent number: 8686535Abstract: Embodiments of the disclosure include a shallow trench isolation structure having a dielectric material with energetic species implanted to a predetermined depth of the dielectric material. Embodiments further include methods of fabricating the trench structures with the implant of energetic species to the predetermined depth. In various embodiments the implant of energetic species is used to densify the dielectric material to provide a uniform wet etch rate across the surface of the dielectric material. Embodiments also include memory devices, integrated circuits, and electronic systems that include shallow trench isolation structures having the dielectric material with the high flux of energetic species implanted to the predetermined depth of the dielectric material.Type: GrantFiled: April 12, 2010Date of Patent: April 1, 2014Assignee: Micron Technology, Inc.Inventors: Gurtej S. Sandhu, John A. Smythe, III
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Patent number: 8617959Abstract: Resistive memory and methods of processing resistive memory are described herein. One or more method embodiments of processing resistive memory include conformally forming a cell material in an opening in an interlayer dielectric such that a seam is formed in the cell material, forming a conductive pathway by modifying the seam, and forming an electrode on the cell material and the seam.Type: GrantFiled: November 30, 2012Date of Patent: December 31, 2013Assignee: Micron Technology, Inc.Inventors: Gurtej S. Sandhu, John A. Smythe, III
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Patent number: 8575040Abstract: Semiconductor devices, structures and systems that utilize a polysilazane-based silicon oxide layer or fill, and methods of making the oxide layer are disclosed. In one embodiment, a polysilazane solution is deposited on a substrate and processed with ozone in a wet oxidation at low temperature to chemically modify the polysilazane material to a silicon oxide layer.Type: GrantFiled: July 6, 2009Date of Patent: November 5, 2013Assignee: Micron Technology, Inc.Inventors: Janos Fucsko, John A. Smythe, III, Li Li, Grady S. Waldo
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Patent number: 8324065Abstract: Resistive memory and methods of processing resistive memory are described herein. One or more method embodiments of processing resistive memory include conformally forming a cell material in an opening in an interlayer dielectric such that a seam is formed in the cell material, forming a conductive pathway by modifying the seam, and forming an electrode on the cell material and the seam.Type: GrantFiled: September 7, 2011Date of Patent: December 4, 2012Assignee: Micron Technology, Inc.Inventors: Gurtej S. Sandhu, John A. Smythe, III