Patents by Inventor John A. Smythe, III
John A. Smythe, III has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20120267599Abstract: The present disclosure includes a high density resistive random access memory (RRAM) device, as well as methods of fabricating a high density RRAM device. One method of forming an RRAM device includes forming a resistive element having a metal-metal oxide interface. Forming the resistive element includes forming an insulative material over the first electrode, and forming a via in the insulative material. The via is conformally filled with a metal material, and the metal material is planarized to within the via. A portion of the metal material within the via is selectively treated to create a metal-metal oxide interface within the via. A second electrode is formed over the resistive element.Type: ApplicationFiled: June 14, 2012Publication date: October 25, 2012Applicant: MICRON TECHNOLOGY, INC.Inventors: Joseph N. Greeley, John A. Smythe, III
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Publication number: 20120001144Abstract: The present disclosure includes a high density resistive random access memory (RRAM) device, as well as methods of fabricating a high density RRAM device. One method of forming an RRAM device includes forming a resistive element having a metal-metal oxide interface. Forming the resistive element includes forming an insulative material over the first electrode, and forming a via in the insulative material. The via is conformally filled with a metal material, and the metal material is planarized to within the via. A portion of the metal material within the via is selectively treated to create a metal-metal oxide interface within the via. A second electrode is formed over the resistive element.Type: ApplicationFiled: July 2, 2010Publication date: January 5, 2012Applicant: MICRON TECHNOLOGY, INC.Inventors: Joseph N. Greeley, John A. Smythe, III
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Publication number: 20110315543Abstract: Forming memory using high power impulse magnetron sputtering is described herein. One or more method embodiments include forming a resistive memory material on a structure using high power impulse magnetron sputtering (HIPIMS), wherein the resistive memory material is formed on the structure in an environment having a temperature of approximately 400 degrees Celsius or less.Type: ApplicationFiled: June 28, 2010Publication date: December 29, 2011Applicant: Micron Technology, Inc.Inventors: Yongjun Jeff Hu, Everett A. McTeer, John A. Smythe, III, Gurtej S. Sandhu
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Patent number: 7919829Abstract: A method of depositing dielectric material into sub-micron spaces and resultant structures is provided. After a trench is etched in the surface of a wafer, a silicon nitride barrier is deposited into the trench. The silicon nitride layer has a high nitrogen content near the trench walls to protect the walls. The silicon nitride layer further from the trench walls has a low nitrogen content and a high silicon content, to allow improved adhesion. The trench is then filled with a spin-on precursor. A densification or reaction process is then applied to convert the spin-on material into an insulator. The resulting trench has a well-adhered insulator which helps the insulating properties of the trench.Type: GrantFiled: August 28, 2007Date of Patent: April 5, 2011Assignee: Micron Technology, Inc.Inventors: Jigish D. Trivedi, Robert D. Patraw, Kevin L. Beaman, John A. Smythe, III
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Patent number: 7659181Abstract: A method of depositing dielectric material into sub-micron spaces and resultant structures is provided. After a trench is etched in the surface of a wafer, an oxygen barrier is deposited into the trench. An expandable, oxidizable liner, preferably amorphous silicon, is then deposited. The trench is then filled with a spin-on dielectric (SOD) material. A densification process is then applied, whereby the SOD material contracts and the oxidizable liner expands. Preferably, the temperature is ramped up while oxidizing during at least part of the densification process. The resulting trench has a negligible vertical wet etch rate gradient and a negligible recess at the top of the trench.Type: GrantFiled: November 6, 2006Date of Patent: February 9, 2010Assignee: Micron Technology, Inc.Inventors: John A. Smythe, III, Jigish D. Trivedi
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Patent number: 7622769Abstract: A method of depositing dielectric material into sub-micron spaces and resultant structures is provided. After a trench is etched in the surface of a wafer, an oxygen barrier is deposited into the trench. An expandable, oxidizable liner, preferably amorphous silicon, is then deposited. The trench is then filled with a spin-on dielectric (SOD) material. A densification process is then applied, whereby the SOD material contracts and the oxidizable liner expands. Preferably, the temperature is ramped up while oxidizing during at least part of the densification process. The resulting trench has a negligible vertical wet etch rate gradient and a negligible recess at the top of the trench.Type: GrantFiled: August 1, 2006Date of Patent: November 24, 2009Assignee: Micron Technologies, Inc.Inventors: John A. Smythe, III, Jigish D. Trivedi
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Publication number: 20090269569Abstract: Semiconductor devices, structures and systems that utilize a polysilazane-based silicon oxide layer or fill, and methods of making the oxide layer are disclosed. In one embodiment, a polysilazane solution is deposited on a substrate and processed with ozone in a wet oxidation at low temperature to chemically modify the polysilazane material to a silicon oxide layer.Type: ApplicationFiled: July 6, 2009Publication date: October 29, 2009Inventors: Janos Fucsko, John A. Smythe, III, Li Li, Grady S. Waldo
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Patent number: 7557420Abstract: Semiconductor devices, structures and systems that utilize a polysilazane-based silicon oxide layer or fill, and methods of making the oxide layer are disclosed. In one embodiment, a polysilazane solution is deposited on a substrate and processed with ozone in a wet oxidation at low temperature to chemically modify the polysilazane material to a silicon oxide layer.Type: GrantFiled: December 29, 2005Date of Patent: July 7, 2009Assignee: Micron Technology, Inc.Inventors: Janos Fucsko, John A Smythe, III, Li Li, Grady S Waldo
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Patent number: 7521378Abstract: Semiconductor devices, structures and systems that utilize a polysilazane-based silicon oxide layer or fill, and methods of making the oxide layer are disclosed. In one embodiment, a polysilazane solution is deposited on a substrate and processed with ozone in a wet oxidation at low temperature to chemically modify the polysilazane material to a silicon oxide layer.Type: GrantFiled: July 1, 2004Date of Patent: April 21, 2009Assignee: Micron Technology, Inc.Inventors: Janos Fucsko, John A Smythe, III, Li Li, Grady S Waldo
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Patent number: 7514366Abstract: A method of depositing dielectric material into sub-micron spaces and resultant structures is provided. After a trench is etched in the surface of a wafer, a silicon nitride barrier is deposited into the trench. The silicon nitride layer has a high nitrogen content near the trench walls to protect the walls. The silicon nitride layer further from the trench walls has a low nitrogen content and a high silicon content, to allow improved adhesion. The trench is then filled with a spin-on precursor. A densification or reaction process is then applied to convert the spin-on material into an insulator. The resulting trench has a well-adhered insulator which helps the insulating properties of the trench.Type: GrantFiled: September 5, 2006Date of Patent: April 7, 2009Assignee: Micron Technology, Inc.Inventors: Jigish D. Trivedi, Robert D. Patraw, Kevin L. Beaman, John A. Smythe, III
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Patent number: 7501691Abstract: A method of depositing dielectric material into sub-micron spaces and resultant structures is provided. After a trench is etched in the surface of a wafer, a liner layer preferably is deposited into the trench. An anisotropic plasma process is then performed on the trench. A silicon layer may be deposited on the base of the trench during the plasma process, or the plasma can treat the liner layer. The trench is then filled with a spin-on precursor. A densification or reaction process is then applied to convert the spin-on material into an insulator, and oxidizing the silicon rich layer on the base of the trench. The resulting trench has a consistent etch rate from top to bottom of the trench.Type: GrantFiled: August 28, 2007Date of Patent: March 10, 2009Assignee: Micron Technology, Inc.Inventors: John A. Smythe, III, William Budge
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Patent number: 7479440Abstract: A method of depositing dielectric material into sub-micron spaces and resultant structures is provided. After a trench is etched in the surface of a wafer, a liner layer preferably is deposited into the trench. An anisotropic plasma process is then performed on the trench. A silicon layer may be deposited on the base of the trench during the plasma process, or the plasma can treat the liner layer. The trench is then filled with a spin-on precursor. A densification or reaction process is then applied to convert the spin-on material into an insulator, and oxidizing the silicon rich layer on the base of the trench. The resulting trench has a consistent etch rate from top to bottom of the trench.Type: GrantFiled: January 11, 2007Date of Patent: January 20, 2009Assignee: Micron Technology, Inc.Inventors: John A. Smythe, III, William Budge
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Patent number: 7271463Abstract: A method of depositing dielectric material into sub-micron spaces and resultant structures is provided. After a trench is etched in the surface of a wafer, a liner layer preferably is deposited into the trench. An anisotropic plasma process is then performed on the trench. A silicon layer may be deposited on the base of the trench during the plasma process, or the plasma can treat the liner layer. The trench is then filled with a spin-on precursor. A densification or reaction process is then applied to convert the spin-on material into an insulator, and oxidizing the silicon rich layer on the base of the trench. The resulting trench has a consistent etch rate from top to bottom of the trench.Type: GrantFiled: December 10, 2004Date of Patent: September 18, 2007Assignee: Micron Technology, Inc.Inventors: John A. Smythe, III, William Budge
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Patent number: 7271464Abstract: A method of depositing dielectric material into sub-micron spaces and resultant structures is provided. After a trench is etched in the surface of a wafer, a silicon nitride barrier is deposited into the trench. The silicon nitride layer has a high nitrogen content near the trench walls to protect the walls. The silicon nitride layer further from the trench walls has a low nitrogen content and a high silicon content, to allow improved adhesion. The trench is then filled with a spin-on precursor. A densification or reaction process is then applied to convert the spin-on material into an insulator. The resulting trench has a well-adhered insulator which helps the insulating properties of the trench.Type: GrantFiled: August 24, 2004Date of Patent: September 18, 2007Assignee: Micron Technology, Inc.Inventors: Jigish D. Trivedi, Robert D. Patraw, Kevin L. Beaman, John A. Smythe, III
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Patent number: 7112513Abstract: A method of depositing dielectric material into sub-micron spaces and resultant structures is provided. After a trench is etched in the surface of a wafer, an oxygen barrier is deposited into the trench. An expandable, oxidizable liner, preferably amorphous silicon, is then deposited. The trench is then filled with a spin-on dielectric (SOD) material. A densification process is then applied, whereby the SOD material contracts and the oxidizable liner expands. Preferably, the temperature is ramped up while oxidizing during at least part of the densification process. The resulting trench has a negligible vertical wet etch rate gradient and a negligible recess at the top of the trench.Type: GrantFiled: February 19, 2004Date of Patent: September 26, 2006Assignee: Micron Technology, Inc.Inventors: John A. Smythe, III, Jigish D. Trivedi
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Patent number: 6573141Abstract: The present invention provides a method for improving the quality of thin oxides formed upon a semiconductor body. The etch and pre-clean processes are performed in situ, taking place in a single apparatus. This reduces the amount of handling of the wafers, their exposure to clean room air, and time delays between clean and oxidation. This results in both a higher yield and greater reliability. In addition, it reduces equipment requirements. The etch, employing a buffered oxide etchant, resist strip, and pre-clean, all occur in a single apparatus without transfer, yielding better results, despite the inherently dirty nature of the resist strip, than the traditional technique of transferring to a new apparatus for each of these steps. The improvements are particularly important for thin oxides such as the tunnel oxides of EEPROMs.Type: GrantFiled: March 12, 1999Date of Patent: June 3, 2003Assignee: ZiLOG, Inc.Inventors: Bernice L. Kickel, John A. Smythe, III
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Patent number: 6190973Abstract: The present invention provides a method of forming a high quality thin oxide on a semiconductor body. A sacrificial oxide is formed on the semiconductor and then etched to eliminate the surface contamination of the semiconductor body. Then, an EEPROM oxide is formed following by an arsenic implant. Next the EEPROM oxide on the semiconductor body is then prepared by thin oxide growth. The thin oxide is preferably formed in a steam ambient. Subsequently, the oxide is annealed under nitrous oxide ambient using a combination of in-situ and RTP annealing process.Type: GrantFiled: December 18, 1998Date of Patent: February 20, 2001Assignee: Zilog Inc.Inventors: John E. Berg, Bernice L. Kickel, John A. Smythe, III
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Patent number: 6165846Abstract: The improvement of thin tunnel oxides used in EEPROM and FLASH tecnologies using post-oxidation annealing in nitrogen causes defects in subsequent oxide films. These are manifested by oxide thinning at the bird's beak and result in high gate leakage. As the time and temperature to the post-oxidation annealing are increased for improved tunnel oxide performance, the number of defects increases rapidly. A method of realizing the improved tunnel oxide Q.sub.BD using higher post-oxidation time and temperature annealing while at the same time not degrading the quality of subsequent gate oxides is shown. The use of sacrificial oxidation and strip just prior to the transistor gate oxidation is described. This process removes the additional nitride which exists at the field edges, leading to the oxide thinning. As a result, improved tunnel oxide integrity can be achieved without degradation of high and low voltage transistors.Type: GrantFiled: March 2, 1999Date of Patent: December 26, 2000Assignee: Zilog, Inc.Inventors: Timothy K. Carns, John A. Smythe, III, John A. Ransom, Bernice L. Kickel, John E. Berg