Master image chip organization technique or method

A method for forming an improved integrated circuit chip structure having a surface from which regions of different conductivity type are arranged in a plurality of electrically isolated macro circuits, each macro circuit including interconnected components, a first X pattern of equally spaced parallel conductors overlying and electrically insulated from said chip structure surface, said first X pattern of conductors being selectively connected to at least certain ones of said plurality of macro circuits, a second Y pattern of equally spaced parallel conductors overlying and electrically insulated from said first pattern of parallel conductors, said second Y pattern of conductors being selectively connected to at least selected certain ones of said first pattern of electrical conductors, said spacing one from another of said first X pattern of conductors being equal to said spacing one from another of said second Y pattern of conductors, said first pattern of conductors being orthogonal of said second pattern of conductors, and each of said connections occurring exclusively at points in space corresponding to X-Y intersections of an X-Y coordinate system, where said X-Y coordinate system geometrically corresponds identically to said X-Y pattern of conductors.

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Description
Patent History
Patent number: T106201
Type: Grant
Filed: Jan 13, 1983
Date of Patent: Mar 4, 1986
Inventors: John Balyoz (Hopewell Junction, NY), Chi S. Chang (Wappingers Falls, NY), Barry C. Fox (Poughkeepsie, NY), John A. Palmieri (Wappingers Falls, NY), Majid Ghafghaichi (Poughkeepsie, NY), Teh-Sen Jen (Fishkill, NY), Donald B. Mooney (Poughkeepsie, NY)
Application Number: 6/457,786
Classifications
Current U.S. Class: 29/577C
International Classification: H01L 2188;