Patents by Inventor John David Porter

John David Porter has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190230740
    Abstract: A node (50) for a communications system comprising a network of a plurality of nodes is described. The node (50) communicates with other nodes (50) in the network using information formatted into superframes comprising a plurality of symbols in which part of the superframes are for payload data and part of the superframes are for synchronisation data and such that there is agreement amongst at least some nodes of the network of when a superframe starts and the duration of the symbols of the superframe. The node (50) synchronises its reference source (60,61) to a selected synchronisation source selected from external synchronisation sources and changes the selection of external synchronisation source from time to time such that the selected synchronisation source availability and reliability is above a predetermined level and communications data of a superframe is interpretable while the node (50) communicates with at least some of the other nodes (50) in the network.
    Type: Application
    Filed: September 6, 2017
    Publication date: July 25, 2019
    Inventors: John David Porter, Richard Mark Barden
  • Publication number: 20190207303
    Abstract: A node 100 for a communications system comprising a plurality of nodes is disclosed. The node 100 comprises a plurality of antennas each configured to transmit and/or receive a beam for communications with other nodes of a communications system. The at least one beam deflector is located in a housing 104,106 detachably attached to an external portion of the node 100. The or each beam deflector is located and arranged to deflect a beam transmitted and/or received at one of the plurality of antennas.
    Type: Application
    Filed: June 30, 2017
    Publication date: July 4, 2019
    Applicant: Cambridge Communication Systems Limited
    Inventors: John David Porter, Daiqing Li, Martin Prescott
  • Patent number: 9653143
    Abstract: Apparatuses, memory section control circuits, and methods of refreshing memory are disclosed. An example apparatus includes a plurality of memory sections and a plurality of memory section control circuits. Each memory section control circuit is coupled to a respective one of the plurality of memory sections and includes a plurality of access line drivers, each of which includes a plurality of transistors having common coupled gates. During an operation of the apparatus a first voltage is provided to the commonly coupled gates of the transistors of at least some of the access line drivers of the memory section control circuit coupled to an active memory section and a second voltage is provided to the commonly coupled gates of the transistors of the access line drivers of the memory section control circuit coupled to an inactive memory section control circuit, wherein the first voltage is greater than the second voltage.
    Type: Grant
    Filed: June 1, 2016
    Date of Patent: May 16, 2017
    Assignee: Micron Technology, Inc.
    Inventors: John David Porter, Gi-Hong Kim
  • Patent number: 9578684
    Abstract: A wireless node (10) comprises an RF modem (12), an RF switch array (14) connected to the RF modem (12), the RF switch array (14) comprising a layer of circuit board (18) sandwiched between layers of conductive material (20, 22) and a plurality of antennas (16) connected to the circuit board (18) of the RF switch array (14) via waveguides (36) present in the layers of conductive material (20, 22), a first subset of the antennas (16) arranged in a first horizontal plane H1 and a second subset of the antennas (16) arranged below the first horizontal plane H1 in a second horizontal plane H2.
    Type: Grant
    Filed: April 7, 2014
    Date of Patent: February 21, 2017
    Assignee: Cambridge Communication Systems Limited
    Inventors: John David Porter, Melvyn Noakes
  • Patent number: 9524759
    Abstract: Apparatuses and methods for capturing data using a divided clock are described. An example apparatus includes a clock divider configured to receive a DQS signal, and to provide divided clock signals. A divided clock signal of the divided clock signals has a frequency that is less than a frequency of the DQS signal. The example apparatus further includes a command circuit configured to receive a command, and to assert one of a plurality of flag signals based on the divided clock signals and on a defined latency from a time of receipt of the command. The example apparatus further includes a data capture circuit configured serially receive data associated with the command and to provide deserialized data responsive to the divided clock signals. The data capture circuit is further configured to sort the deserialized data based on the asserted one of the plurality of flag signals to provide sorted data.
    Type: Grant
    Filed: December 16, 2014
    Date of Patent: December 20, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Ki-Jun Nam, John David Porter
  • Patent number: 9490631
    Abstract: Apparatuses and methods for protecting a circuit from an over-limit electrical condition are disclosed. One example apparatus includes a protection circuit coupled to a circuit to be protected. The circuit to be protected is coupled to a pad node. The protection circuit is configured to conduct current from the pad node to a reference voltage node to protect the circuit from an over-limit electrical condition. The protection circuit has a trigger circuit coupled to the pad node and configured to trigger a shunt circuit to conduct current from the pad node to the reference voltage node responsive to a voltage provided to the pad node having a voltage exceeding a trigger voltage. In some embodiments, the trigger circuit is matched to the circuit being protected.
    Type: Grant
    Filed: May 12, 2014
    Date of Patent: November 8, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Xiaofeng Fan, Michael Chaine, John David Porter
  • Publication number: 20160276017
    Abstract: Apparatuses, memory section control circuits, and methods of refreshing memory are disclosed. An example apparatus includes a plurality of memory sections and a plurality of memory section control circuits. Each memory section control circuit is coupled to a respective one of the plurality of memory sections and includes a plurality of access line drivers, each of which includes a plurality of transistors having common coupled gates. During an operation of the apparatus a first voltage is provided to the commonly coupled gates of the transistors of at least some of the access line drivers of the memory section control circuit coupled to an active memory section and a second voltage is provided to the commonly coupled gates of the transistors of the access line drivers of the memory section control circuit coupled to an inactive memory section control circuit, wherein the first voltage is greater than the second voltage.
    Type: Application
    Filed: June 1, 2016
    Publication date: September 22, 2016
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: John David Porter, Gi-Hong Kim
  • Publication number: 20160172018
    Abstract: Apparatuses and methods for capturing data using a divided clock are described. An example apparatus includes a clock divider configured to receive a DQS signal, and to provide divided clock signals. A divided clock signal of the divided clock signals has a frequency that is less than a frequency of the DQS signal. The example apparatus further includes a command circuit configured to receive a command, and to assert one of a plurality of flag signals based on the divided clock signals and on a defined latency from a time of receipt of the command. The example apparatus further includes a data capture circuit configured serially receive data associated with the command and to provide deserialized data responsive to the divided clock signals. The data capture circuit is further configured to sort the deserialized data based on the asserted one of the plurality of flag signals to provide sorted data.
    Type: Application
    Filed: December 16, 2014
    Publication date: June 16, 2016
    Inventors: Ki-Jun Nam, John David Porter
  • Patent number: 9368184
    Abstract: Apparatuses, memory section control circuits, and methods of refreshing memory are disclosed. An example apparatus includes a plurality of memory sections and a plurality of memory section control circuits. Each memory section control circuit is coupled to a respective one of the plurality of memory sections and includes a plurality of access line drivers, each of which includes a plurality of transistors having common coupled gates. During an operation of the apparatus a first voltage is provided to the commonly coupled gates of the transistors of at least some of the access line drivers of the memory section control circuit coupled to an active memory section and a second voltage is provided to the commonly coupled gates of the transistors of the access line drivers of the memory section control circuit coupled to an inactive memory section control circuit, wherein the first voltage is greater than the second voltage.
    Type: Grant
    Filed: October 3, 2014
    Date of Patent: June 14, 2016
    Assignee: Micron Technology, Inc.
    Inventors: John David Porter, Gi-Hong Kim
  • Publication number: 20160057003
    Abstract: A set of wireless nodes is provided, in which a subset of the wireless nodes are also wired nodes. A method of processing the set comprises performing a node initialisation, thereby linking nodes in the set of wireless nodes, performing a link evaluation, thereby determining a quality characteristic of links between nodes, and segmenting the nodes into partitions, each partition comprising at least one wired node and each node in a partition having a link to another node in the same partition with the determined quality characteristic above a predetermined threshold.
    Type: Application
    Filed: March 14, 2014
    Publication date: February 25, 2016
    Inventors: John David Porter, Alexander John Zeffertt, Richard Mark Barden
  • Publication number: 20160050715
    Abstract: A wireless node (10) comprises an RF modem (12), an RF switch array (14) connected to the RF modem (12), the RF switch array (14) comprising a layer of circuit board (18) sandwiched between layers of conductive material (20, 22) and a plurality of antennas (16) connected to the circuit board (18) of the RF switch array (14) via waveguides (36) present in the layers of conductive material (20, 22), a first subset of the antennas (16) arranged in a first horizontal plane H1 and a second subset of the antennas (16) arranged below the first horizontal plane H1 in a second horizontal plane H2.
    Type: Application
    Filed: April 7, 2014
    Publication date: February 18, 2016
    Inventors: John David Porter, Melvyn Noakes
  • Publication number: 20150372387
    Abstract: A wireless node (10) comprises an RF modem (12), an RF switch array (14) connected to the RF modem, the RF switch array comprising a layer of circuit board sandwiched between layers of conductive material, and a plurality of antennas (16) arranged in a horizontal plane and connected to the circuit board of the RF switch array via waveguides present in the layers of conductive material. A method of operating the wireless node comprises generating radio signals at the RF modem (12), communicating the generated radio signals to the RF switch array (14), selecting an antenna (16) for transmitting the generated radio signals and transmitting the generated radio signals from the selected antenna.
    Type: Application
    Filed: January 31, 2014
    Publication date: December 24, 2015
    Inventors: John David Porter, Stephen David Greaves
  • Publication number: 20150365276
    Abstract: A wireless node comprises a central core (100) of interlocking horizontal layers of circuit boards and conductive material comprising, from bottom to top, an RF modem comprising a layer of circuit board (24) sandwiched between layers of conductive material (26, 28), a duplexer (30) connected to the RF modem, and an RF switch array connected to the duplexer (30), the RF switch array comprising a layer of circuit board (18) sandwiched between layers of conductive material (20, 22).
    Type: Application
    Filed: January 31, 2014
    Publication date: December 17, 2015
    Applicant: CAMBRIDGE COMMUNICATION SYSTEMS LIMITED
    Inventors: John David Porter, Stephen David Greaves
  • Publication number: 20150023121
    Abstract: Apparatuses, memory section control circuits, and methods of refreshing memory are disclosed. An example apparatus includes a plurality of memory sections and a plurality of memory section control circuits. Each memory section control circuit is coupled to a respective one of the plurality of memory sections and includes a plurality of access line drivers, each of which includes a plurality of transistors having common coupled gates. During an operation of the apparatus a first voltage is provided to the commonly coupled gates of the transistors of at least some of the access line drivers of the memory section control circuit coupled to an active memory section and a second voltage is provided to the commonly coupled gates of the transistors of the access line drivers of the memory section control circuit coupled to an inactive memory section control circuit, wherein the first voltage is greater than the second voltage.
    Type: Application
    Filed: October 3, 2014
    Publication date: January 22, 2015
    Inventors: John David Porter, Gi-Hong Kim
  • Patent number: 8861296
    Abstract: Apparatuses, memory section control circuits, and methods of refreshing memory are disclosed. An example apparatus includes a plurality of memory sections and a plurality of memory section control circuits. Each memory section control circuit is coupled to a respective one of the plurality of memory sections and includes a plurality of access line drivers, each of which includes a plurality of transistors having common coupled gates. During an operation of the apparatus a first voltage is provided to the commonly coupled gates of the transistors of at least some of the access line drivers of the memory section control circuit coupled to an active memory section and a second voltage is provided to the commonly coupled gates of the transistors of the access line drivers of the memory section control circuit coupled to an inactive memory section control circuit, wherein the first voltage is greater than the second voltage.
    Type: Grant
    Filed: November 19, 2013
    Date of Patent: October 14, 2014
    Assignee: Micron Technology, Inc.
    Inventors: John David Porter, Gi-Hong Kim
  • Publication number: 20140240883
    Abstract: Apparatuses and methods for protecting a circuit from an over-limit electrical condition are disclosed. One example apparatus includes a protection circuit coupled to a circuit to be protected. The circuit to be protected is coupled to a pad node. The protection circuit is configured to conduct current from the pad node to a reference voltage node to protect the circuit from an over-limit electrical condition. The protection circuit has a trigger circuit coupled to the pad node and configured to trigger a shunt circuit to conduct current from the pad node to the reference voltage node responsive to a voltage provided to the pad node having a voltage exceeding a trigger voltage. In some embodiments, the trigger circuit is matched to the circuit being protected.
    Type: Application
    Filed: May 12, 2014
    Publication date: August 28, 2014
    Applicant: Micron Technology, Inc.
    Inventors: Xiaofeng Fan, Michael Chaine, John David Porter
  • Patent number: 8724268
    Abstract: Apparatuses and methods for protecting a circuit from an over-limit electrical condition are disclosed. One example apparatus includes a protection circuit coupled to a circuit to be protected. The circuit to be protected is coupled to a pad node. The protection circuit is configured to conduct current from the pad node to a reference voltage node to protect the circuit from an over-limit electrical condition. The protection circuit has a trigger circuit coupled to the pad node and configured to trigger a shunt circuit to conduct current from the pad node to the reference voltage node responsive to a voltage provided to the pad node having a voltage exceeding a trigger voltage. In some embodiments, the trigger circuit is matched to the circuit being protected.
    Type: Grant
    Filed: August 30, 2011
    Date of Patent: May 13, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Xiaofeng Fan, Michael Chaine, John David Porter
  • Publication number: 20140078847
    Abstract: Apparatuses, memory section control circuits, and methods of refreshing memory are disclosed. An example apparatus includes a plurality of memory sections and a plurality of memory section control circuits. Each memory section control circuit is coupled to a respective one of the plurality of memory sections and includes a plurality of access line drivers, each of which includes a plurality of transistors having common coupled gates. During an operation of the apparatus a first voltage is provided to the commonly coupled gates of the transistors of at least some of the access line drivers of the memory section control circuit coupled to an active memory section an and a second voltage is provided to the commonly coupled gates of the transistors of the access line drivers of the memory section control circuit coupled to an inactive memory section control circuit, wherein the first voltage is greater than the second voltage.
    Type: Application
    Filed: November 19, 2013
    Publication date: March 20, 2014
    Applicant: Micron Technology, Inc.
    Inventors: John David Porter, Gi-Hong Kim
  • Patent number: 8588022
    Abstract: Apparatuses, memory section control circuits, and methods of refreshing memory are disclosed. An example apparatus includes a plurality of memory sections and a plurality of memory section control circuits. Each memory section control circuit is coupled to a respective one of the plurality of memory sections and includes a plurality of access line drivers, each of which includes a plurality of transistors having common coupled gates. During an operation of the apparatus a first voltage is provided to the commonly coupled gates of the transistors of at least some of the access line drivers of the memory section control circuit coupled to an active memory section and a second voltage is provided to the commonly coupled gates of the transistors of the access line drivers of the memory section control circuit coupled to an inactive memory section control circuit, wherein the first voltage is greater than the second voltage.
    Type: Grant
    Filed: August 24, 2011
    Date of Patent: November 19, 2013
    Assignee: Micron Technology, Inc.
    Inventors: John David Porter, Gi-Hong Kim
  • Patent number: D733107
    Type: Grant
    Filed: April 12, 2013
    Date of Patent: June 30, 2015
    Assignee: CAMBRIDGE COMMUNICATIONS SYSTEMS LIMITED
    Inventor: John David Porter