Abstract: A wireless node (10) comprises an RF modem (12), an RF switch array (14) connected to the RF modem (12), the RF switch array (14) comprising a layer of circuit board (18) sandwiched between layers of conductive material (20, 22) and a plurality of antennas (16) connected to the circuit board (18) of the RF switch array (14) via waveguides (36) present in the layers of conductive material (20, 22), a first subset of the antennas (16) arranged in a first horizontal plane H1 and a second subset of the antennas (16) arranged below the first horizontal plane H1 in a second horizontal plane H2.

Abstract: A wireless node (10) comprises an RF modem (12), an RF switch array (14) connected to the RF modem, the RF switch array comprising a layer of circuit board sandwiched between layers of conductive material, and a plurality of antennas (16) arranged in a horizontal plane and connected to the circuit board of the RF switch array via waveguides present in the layers of conductive material. A method of operating the wireless node comprises generating radio signals at the RF modem (12), communicating the generated radio signals to the RF switch array (14), selecting an antenna (16) for transmitting the generated radio signals and transmitting the generated radio signals from the selected antenna.

Abstract: A wireless node comprises a central core (100) of interlocking horizontal layers of circuit boards and conductive material comprising, from bottom to top, an RF modem comprising a layer of circuit board (24) sandwiched between layers of conductive material (26, 28), a duplexer (30) connected to the RF modem, and an RF switch array connected to the duplexer (30), the RF switch array comprising a layer of circuit board (18) sandwiched between layers of conductive material (20, 22).

Abstract: Apparatuses, memory section control circuits, and methods of refreshing memory are disclosed. An example apparatus includes a plurality of memory sections and a plurality of memory section control circuits. Each memory section control circuit is coupled to a respective one of the plurality of memory sections and includes a plurality of access line drivers, each of which includes a plurality of transistors having common coupled gates. During an operation of the apparatus a first voltage is provided to the commonly coupled gates of the transistors of at least some of the access line drivers of the memory section control circuit coupled to an active memory section and a second voltage is provided to the commonly coupled gates of the transistors of the access line drivers of the memory section control circuit coupled to an inactive memory section control circuit, wherein the first voltage is greater than the second voltage.

Abstract: Apparatuses, memory section control circuits, and methods of refreshing memory are disclosed. An example apparatus includes a plurality of memory sections and a plurality of memory section control circuits. Each memory section control circuit is coupled to a respective one of the plurality of memory sections and includes a plurality of access line drivers, each of which includes a plurality of transistors having common coupled gates. During an operation of the apparatus a first voltage is provided to the commonly coupled gates of the transistors of at least some of the access line drivers of the memory section control circuit coupled to an active memory section and a second voltage is provided to the commonly coupled gates of the transistors of the access line drivers of the memory section control circuit coupled to an inactive memory section control circuit, wherein the first voltage is greater than the second voltage.

Abstract: Apparatuses and methods for protecting a circuit from an over-limit electrical condition are disclosed. One example apparatus includes a protection circuit coupled to a circuit to be protected. The circuit to be protected is coupled to a pad node. The protection circuit is configured to conduct current from the pad node to a reference voltage node to protect the circuit from an over-limit electrical condition. The protection circuit has a trigger circuit coupled to the pad node and configured to trigger a shunt circuit to conduct current from the pad node to the reference voltage node responsive to a voltage provided to the pad node having a voltage exceeding a trigger voltage. In some embodiments, the trigger circuit is matched to the circuit being protected.

Abstract: Apparatuses and methods for protecting a circuit from an over-limit electrical condition are disclosed. One example apparatus includes a protection circuit coupled to a circuit to be protected. The circuit to be protected is coupled to a pad node. The protection circuit is configured to conduct current from the pad node to a reference voltage node to protect the circuit from an over-limit electrical condition. The protection circuit has a trigger circuit coupled to the pad node and configured to trigger a shunt circuit to conduct current from the pad node to the reference voltage node responsive to a voltage provided to the pad node having a voltage exceeding a trigger voltage. In some embodiments, the trigger circuit is matched to the circuit being protected.

Abstract: Apparatuses, memory section control circuits, and methods of refreshing memory are disclosed. An example apparatus includes a plurality of memory sections and a plurality of memory section control circuits. Each memory section control circuit is coupled to a respective one of the plurality of memory sections and includes a plurality of access line drivers, each of which includes a plurality of transistors having common coupled gates. During an operation of the apparatus a first voltage is provided to the commonly coupled gates of the transistors of at least some of the access line drivers of the memory section control circuit coupled to an active memory section an and a second voltage is provided to the commonly coupled gates of the transistors of the access line drivers of the memory section control circuit coupled to an inactive memory section control circuit, wherein the first voltage is greater than the second voltage.

Abstract: Apparatuses, memory section control circuits, and methods of refreshing memory are disclosed. An example apparatus includes a plurality of memory sections and a plurality of memory section control circuits. Each memory section control circuit is coupled to a respective one of the plurality of memory sections and includes a plurality of access line drivers, each of which includes a plurality of transistors having common coupled gates. During an operation of the apparatus a first voltage is provided to the commonly coupled gates of the transistors of at least some of the access line drivers of the memory section control circuit coupled to an active memory section and a second voltage is provided to the commonly coupled gates of the transistors of the access line drivers of the memory section control circuit coupled to an inactive memory section control circuit, wherein the first voltage is greater than the second voltage.

Abstract: Apparatuses, memory section control circuits, and methods of refreshing memory are disclosed. An example apparatus includes a plurality of memory sections and a plurality of memory section control circuits. Each memory section control circuit is coupled to a respective one of the plurality of memory sections and includes a plurality of access line drivers, each of which includes a plurality of transistors having common coupled gates. During an operation of the apparatus a first voltage is provided to the commonly coupled gates of the transistors of at least some of the access line drivers of the memory section control circuit coupled to an active memory section and a second voltage is provided to the commonly coupled gates of the transistors of the access line drivers of the memory section control circuit coupled to an inactive memory section control circuit, wherein the first voltage is greater than the second voltage.

Abstract: Apparatuses and methods for protecting a circuit from an over-limit electrical condition are disclosed. One example apparatus includes a protection circuit coupled to a circuit to be protected. The circuit to be protected is coupled to a pad node. The protection circuit is configured to conduct current from the pad node to a reference voltage node to protect the circuit from an over-limit electrical condition. The protection circuit has a trigger circuit coupled to the pad node and configured to trigger a shunt circuit to conduct current from the pad node to the reference voltage node responsive to a voltage provided to the pad node having a voltage exceeding a trigger voltage. In some embodiments, the trigger circuit is matched to the circuit being protected.

Abstract: The present disclosure includes devices, methods, and systems for sensing memory, such as resistance variable memory, among other types of memory. One or more embodiments can include a method for generating currents to be used in sensing a memory cell, the method including providing a number of initial currents, and generating a number of reference currents by summing particular combinations of the initial currents.

Abstract: In a communications system a transmitter is arranged to transmit asynchronous transfer mode (ATM) cells in which synchronous transfer mode (STM) channels are assembled. In order to minimize the bandwidth required at lease some of the ATM cells include one or more switch command(s) (12) that indicate a change in the activation state of one or more STM channels (11-0 to 11-n). The switch commands (12) and STM channels (11) fill the ATM cell from opposite ends of the cell. Activate switch commands comprise two bytes, a high byte including a pointer (18) pointing to the start of a block of STM channels (11) and a low byte that includes a pointer (19) that points to the channel within a block of STM channels (11) to which the switch command applies.

Abstract: Devices, methods, and systems for temperature compensation in memory devices, such as resistance variable memory, among other types of memory are included. A memory device can include a table with an output that is used to create a multiplication factor for a current to compensate for temperature changes in the memory device, where the output depends on an operating temperature of the memory device and a difference in the current between a highest specified operating temperature and a lowest specified operating temperature of the memory device.

Abstract: In a fixed wireless access (FWA) communications system comprising an Access Point (501) and a plurality of Subscriber Units (502-1, 502-2 502-N) each Subscriber Unit transmits a concentration word when it wishes to obtain access to transmit data. Each Subscriber Unit (502) includes a linear precoder (517) which predistorts the contention word to compensate for the impulse response of the transmission channel between it and Access Point (501). The precoder (517) is optimized specifically for the contention word to be transmitted instead of for general data.

Abstract: The present disclosure includes devices and methods for operating phase change memory cells. One or more embodiments include applying a programming signal to a phase change material of a memory cell, and decreasing a magnitude of a trailing portion of the applied programming signal successively according to a number of particular decrements. The magnitude and the duration of the number of particular decrements correspond to particular programmed values.

Abstract: The present disclosure includes devices and methods for sensing resistance variable memory cells. One device embodiment includes at least one resistance variable memory cell, and a capacitive divider configured to generate multiple reference levels in association with the at least one resistance variable memory cell.

Abstract: The present disclosure includes devices, methods, and systems for programming memory, such as resistance variable memory. One embodiment can include an array of resistance variable memory cells, wherein the resistance variable memory cells are coupled to one or more data lines, a row decoder connected to a first side of the array, a column decoder connected to a second side of the array, wherein the second side is adjacent to the first side, a gap located adjacent to the row decoder and the column decoder, and clamp circuitry configured to control a reverse bias voltage associated with one or more unselected memory cells during a programming operation, wherein the clamp circuitry is located in the gap and is selectively coupled to the one or more data lines.

Abstract: A packet switched communications system and method for transmitting synchronous data from a source module (4) to a terminating module (8) over a network comprising plurality of modules (4, 5, 7, 8) interconnected via transmission links (2, 6, 9). Each module operates with a clock of nominal frequency that is not synchronized with the clocks of the other module(s) and has a single input and one or more outputs. The method includes determining the phase difference between the input clock and the output clock of each module, and transmitting the phase difference to the terminating module (8) in the network. The received accumulated phase difference at the terminating module (8) is used to lock the output clock at the terminating module to the input clock at the source module.