Abstract: Techniques for configurable link interfaces for a memory device are described. In some examples, memory devices may require periodic link training to support data transfer with a host device at relatively fast rates. However, in some managed memory applications, memory dies of a memory device may have integrated controllers that do not support such link training, and accordingly may not support some clock rates or data rates. To support data transfers between a host device and a memory device at relatively fast clock rates or data rates without link training, a memory die may be fabricated with a configurable link interface that can support different mappings between components and operation according to different clock rates or data rates. In some examples, a memory die may be fabricated in a manner that supports configurable mappings between an array and a data channel interface that are operable according to different multiplexing and serialization.

Abstract: Methods, systems, and devices are described for adjusting parameters of channel drivers based on temperature when a calibration component is unavailable. A memory device may determine whether a calibration component is available for use by the memory device. If not, the memory device may select an impedance setting for the driver that is based on an operating temperature of the memory device. A device or system may identify a temperature of a memory device, identify that a calibration component is unavailable to adjust a parameter of a driver of a data channel, select a value of the parameter based on the temperature and on identifying that the calibration component is unavailable, adjust the parameter of the driver of the data channel to the selected value, and transmit, by the driver operating using the selected value of the parameter, a signal over the channel.

Abstract: Methods, systems, and devices for error correction on a memory device are described. Examples may include a memory die having an array of memory cells including a plurality of banks. The memory die may further include a first error correcting code (ECC) circuit coupled with a first bank of memory cells, where the first ECC circuit is configured to perform operations associated with a first access operation (e.g., write operation) of the first bank of memory cells. The memory die may further include a second ECC circuit coupled with the first bank of memory cells, where the second ECC circuit is configured to perform ECC operations associated with a second access operation (e.g., read operation) of the first bank. In some cases, the first ECC circuit may be located under the footprint of the array and the second ECC circuit may be located outside the footprint of the array.

Abstract: Some instances of a memory device include a memory die having an array of memory cells including a plurality of banks. In some cases, the memory die further includes a first error correcting code (ECC) circuit coupled with a first bank of memory cells, where the first ECC circuit is configured to perform operations associated with a first access operation (e.g., write operation) of the first bank of memory cells. In some examples, the memory die further includes a second ECC circuit coupled with the first bank of memory cells, where the second ECC circuit is configured to perform ECC operations associated with a second access operation (e.g., read operation) of the first bank. In some cases, the first ECC circuit is located under the footprint of the array and the second ECC circuit is located outside the footprint of the array.

Abstract: A regulator includes an operational amplifier, a programmable offset voltage, and a circuit. The operational amplifier includes a non-inverting input, an inverting input, and an output. The programmable offset voltage is configured to cancel a built-in offset voltage of the regulator based on a code. The circuit is configured to set the code based on a sensed built-in offset voltage of the regulator in response to an offset cancellation calibration mode enable signal.

Abstract: Methods, systems, and devices for leakage current reduction in electronic devices are described. Electronic devices may be susceptible to leakage currents when operating in a first mode, such as an inactive (e.g., a standby) mode. To mitigate leakage current, an electronic device may include transistors coupled in cascode configuration where a gate of a drain-side transistor in the cascode configuration is configured to be biased by an adjustable (e.g., a dynamic) control signal. When the transistors are inactive (e.g., “off”), the control signal may be adjusted to prevent leakage associated with the inactive transistors. Further, a source-side transistor in the cascode configuration may be configured to have a high threshold voltage (e.g., relative to the drain-side transistor).

Abstract: A regulator includes an operational amplifier, a programmable offset voltage, and a circuit. The operational amplifier includes a non-inverting input, an inverting input, and an output. The programmable offset voltage is configured to cancel a built-in offset voltage of the regulator based on a code. The circuit is configured to set the code based on a sensed built-in offset voltage of the regulator in response to an offset cancellation calibration mode enable signal.

Abstract: Methods, systems, and devices for leakage current reduction in electronic devices are described. Electronic devices may be susceptible to leakage currents when operating in a first mode, such as an inactive (e.g., a standby) mode. To mitigate leakage current, an electronic device may include transistors coupled in cascode configuration where a gate of a drain-side transistor in the cascode configuration is configured to be biased by an adjustable (e.g., a dynamic) control signal. When the transistors are inactive (e.g., “off”), the control signal may be adjusted to prevent leakage associated with the inactive transistors. Further, a source-side transistor in the cascode configuration may be configured to have a high threshold voltage (e.g., relative to the drain-side transistor).

Abstract: Methods, systems, and devices for error correction on a memory device are described. Examples may include a memory die having an array of memory cells including a plurality of banks. The memory die may further include a first error correcting code (ECC) circuit coupled with a first bank of memory cells, where the first ECC circuit is configured to perform operations associated with a first access operation (e.g., write operation) of the first bank of memory cells. The memory die may further include a second ECC circuit coupled with the first bank of memory cells, where the second ECC circuit is configured to perform ECC operations associated with a second access operation (e.g., read operation) of the first bank. In some cases, the first ECC circuit may be located under the footprint of the array and the second ECC circuit may be located outside the footprint of the array.

Abstract: Methods, systems, and devices for leakage current reduction in electronic devices are described. Electronic devices may be susceptible to leakage currents when operating in a first mode, such as an inactive (e.g., a standby) mode. To mitigate leakage current, an electronic device may include transistors coupled in cascode configuration where a gate of a drain-side transistor in the cascode configuration is configured to be biased by an adjustable (e.g., a dynamic) control signal. When the transistors are inactive (e.g., “off”), the control signal may be adjusted to prevent leakage associated with the inactive transistors. Further, a source-side transistor in the cascode configuration may be configured to have a high threshold voltage (e.g., relative to the drain-side transistor).

Abstract: A node (50) for a communications system comprising a network of a plurality of nodes is described. The node (50) communicates with other nodes (50) in the network using information formatted into superframes comprising a plurality of symbols in which part of the superframes are for payload data and part of the superframes are for synchronisation data and such that there is agreement amongst at least some nodes of the network of when a superframe starts and the duration of the symbols of the superframe. The node (50) synchronises its reference source (60,61) to a selected synchronisation source selected from external synchronisation sources and changes the selection of external synchronisation source from time to time such that the selected synchronisation source availability and reliability is above a predetermined level and communications data of a superframe is interpretable while the node (50) communicates with at least some of the other nodes (50) in the network.

Abstract: A node 100 for a communications system comprising a plurality of nodes is disclosed. The node 100 comprises a plurality of antennas each configured to transmit and/or receive a beam for communications with other nodes of a communications system. The at least one beam deflector is located in a housing 104,106 detachably attached to an external portion of the node 100. The or each beam deflector is located and arranged to deflect a beam transmitted and/or received at one of the plurality of antennas.

Abstract: Apparatuses, memory section control circuits, and methods of refreshing memory are disclosed. An example apparatus includes a plurality of memory sections and a plurality of memory section control circuits. Each memory section control circuit is coupled to a respective one of the plurality of memory sections and includes a plurality of access line drivers, each of which includes a plurality of transistors having common coupled gates. During an operation of the apparatus a first voltage is provided to the commonly coupled gates of the transistors of at least some of the access line drivers of the memory section control circuit coupled to an active memory section and a second voltage is provided to the commonly coupled gates of the transistors of the access line drivers of the memory section control circuit coupled to an inactive memory section control circuit, wherein the first voltage is greater than the second voltage.

Abstract: A wireless node (10) comprises an RF modem (12), an RF switch array (14) connected to the RF modem (12), the RF switch array (14) comprising a layer of circuit board (18) sandwiched between layers of conductive material (20, 22) and a plurality of antennas (16) connected to the circuit board (18) of the RF switch array (14) via waveguides (36) present in the layers of conductive material (20, 22), a first subset of the antennas (16) arranged in a first horizontal plane H1 and a second subset of the antennas (16) arranged below the first horizontal plane H1 in a second horizontal plane H2.

Abstract: Apparatuses and methods for capturing data using a divided clock are described. An example apparatus includes a clock divider configured to receive a DQS signal, and to provide divided clock signals. A divided clock signal of the divided clock signals has a frequency that is less than a frequency of the DQS signal. The example apparatus further includes a command circuit configured to receive a command, and to assert one of a plurality of flag signals based on the divided clock signals and on a defined latency from a time of receipt of the command. The example apparatus further includes a data capture circuit configured serially receive data associated with the command and to provide deserialized data responsive to the divided clock signals. The data capture circuit is further configured to sort the deserialized data based on the asserted one of the plurality of flag signals to provide sorted data.

Abstract: Apparatuses and methods for protecting a circuit from an over-limit electrical condition are disclosed. One example apparatus includes a protection circuit coupled to a circuit to be protected. The circuit to be protected is coupled to a pad node. The protection circuit is configured to conduct current from the pad node to a reference voltage node to protect the circuit from an over-limit electrical condition. The protection circuit has a trigger circuit coupled to the pad node and configured to trigger a shunt circuit to conduct current from the pad node to the reference voltage node responsive to a voltage provided to the pad node having a voltage exceeding a trigger voltage. In some embodiments, the trigger circuit is matched to the circuit being protected.

Abstract: Apparatuses, memory section control circuits, and methods of refreshing memory are disclosed. An example apparatus includes a plurality of memory sections and a plurality of memory section control circuits. Each memory section control circuit is coupled to a respective one of the plurality of memory sections and includes a plurality of access line drivers, each of which includes a plurality of transistors having common coupled gates. During an operation of the apparatus a first voltage is provided to the commonly coupled gates of the transistors of at least some of the access line drivers of the memory section control circuit coupled to an active memory section and a second voltage is provided to the commonly coupled gates of the transistors of the access line drivers of the memory section control circuit coupled to an inactive memory section control circuit, wherein the first voltage is greater than the second voltage.

Abstract: Apparatuses and methods for capturing data using a divided clock are described. An example apparatus includes a clock divider configured to receive a DQS signal, and to provide divided clock signals. A divided clock signal of the divided clock signals has a frequency that is less than a frequency of the DQS signal. The example apparatus further includes a command circuit configured to receive a command, and to assert one of a plurality of flag signals based on the divided clock signals and on a defined latency from a time of receipt of the command. The example apparatus further includes a data capture circuit configured serially receive data associated with the command and to provide deserialized data responsive to the divided clock signals. The data capture circuit is further configured to sort the deserialized data based on the asserted one of the plurality of flag signals to provide sorted data.

Abstract: Apparatuses, memory section control circuits, and methods of refreshing memory are disclosed. An example apparatus includes a plurality of memory sections and a plurality of memory section control circuits. Each memory section control circuit is coupled to a respective one of the plurality of memory sections and includes a plurality of access line drivers, each of which includes a plurality of transistors having common coupled gates. During an operation of the apparatus a first voltage is provided to the commonly coupled gates of the transistors of at least some of the access line drivers of the memory section control circuit coupled to an active memory section and a second voltage is provided to the commonly coupled gates of the transistors of the access line drivers of the memory section control circuit coupled to an inactive memory section control circuit, wherein the first voltage is greater than the second voltage.

Abstract: A set of wireless nodes is provided, in which a subset of the wireless nodes are also wired nodes. A method of processing the set comprises performing a node initialisation, thereby linking nodes in the set of wireless nodes, performing a link evaluation, thereby determining a quality characteristic of links between nodes, and segmenting the nodes into partitions, each partition comprising at least one wired node and each node in a partition having a link to another node in the same partition with the determined quality characteristic above a predetermined threshold.