Patents by Inventor John E. Barth, Jr.

John E. Barth, Jr. has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160163712
    Abstract: Systems and methods of forming semiconductor devices. A trench capacitor comprising deep trenches is formed in an n+ type substrate. The deep trenches have a lower portion partially filled with a trench conductor surrounded by a storage dielectric. A polysilicon growth is formed in an upper portion of the deep trenches. The semiconductor device includes a single-crystal semiconductor having an angled seam separating a portion of the polysilicon growth from an exposed edge of the deep trenches. A word-line is wrapped around the single-crystal semiconductor. A bit-line overlays the single-crystal semiconductor.
    Type: Application
    Filed: December 5, 2014
    Publication date: June 9, 2016
    Inventors: Brent A. Anderson, John E. Barth, JR., Edward J. Nowak
  • Patent number: 9363137
    Abstract: Embodiments of the invention relate to faulty recovery mechanisms for a three-dimensional (3-D) network on a processor array. One embodiment comprises a multidimensional switch network for a processor array. The switch network comprises multiple switches for routing packets between multiple core circuits of the processor array. The switches are organized into multiple planes. The switch network further comprises a redundant plane including multiple redundant switches. Multiple data paths interconnect the switches. The redundant plane is used to facilitate full operation of the processor array in the event of one or more component failures.
    Type: Grant
    Filed: August 6, 2015
    Date of Patent: June 7, 2016
    Assignee: International Business Machines Corporation
    Inventors: Rodrigo Alvarez-Icaza Rivera, John V. Arthur, John E. Barth, Jr., Andrew S. Cassidy, Subramanian Iyer, Paul A. Merolla, Dharmendra S. Modha
  • Publication number: 20160154717
    Abstract: Embodiments of the invention relate to faulty recovery mechanisms for a three-dimensional (3-D) network on a processor array. One embodiment comprises a multidimensional switch network for a processor array. The switch network comprises multiple switches for routing packets between multiple core circuits of the processor array. The switches are organized into multiple planes. The switch network further comprises a redundant plane including multiple redundant switches. Multiple data paths interconnect the switches. The redundant plane is used to facilitate full operation of the processor array in the event of one or more component failures.
    Type: Application
    Filed: August 6, 2015
    Publication date: June 2, 2016
    Inventors: Rodrigo Alvarez-Icaza Rivera, John V. Arthur, John E. Barth, JR., Andrew S. Cassidy, Subramanian Iyer, Paul A. Merolla, Dharmendra S. Modha
  • Patent number: 9343185
    Abstract: A memory having variable size blocks of failed memory addresses is connected to a TCAM storing data values of ranges of addresses in the memory. The ranges of addresses correspond to virtual addresses that, in combination with an offset, point away from failed memory addresses. A reduction circuit connected to the TCAM produces an output for each programmed range of addresses based on a virtual address. A priority encoder, connected to the reduction circuit, selects a first range from the reduction circuit and passes the first range to a random-access memory (RAM). Responsive to the virtual address bring an address in one of the ranges of addresses, the priority encoder passes the first range containing the virtual address to the RAM, which passes a corresponding offset value to the Adder based on the first range. The Adder calculates a physical memory address directing the virtual address to a functional memory location.
    Type: Grant
    Filed: September 26, 2013
    Date of Patent: May 17, 2016
    Assignee: International Business Machines Corporation
    Inventors: John E. Barth, Jr., Srivatsan Chellappa, Dean L. Lewis
  • Publication number: 20160099054
    Abstract: An array organization and architecture for a content addressable memory (CAM) system. More specifically, a circuit is provided for that includes a first portion of the CAM configured to perform a first inequality operation implemented between 1 to n CAM entries. The circuit further includes a second portion of the CAM configured to perform a second inequality operation implemented between the 1 to n CAM entries. The first portion and the second portion are triangularly arranged side by side such that the first inequality operation and the second inequality operation are implemented between the 1 to n CAM entries using the same n wordlines.
    Type: Application
    Filed: December 8, 2015
    Publication date: April 7, 2016
    Inventors: John E. BARTH, JR., Dean L. LEWIS
  • Patent number: 9299769
    Abstract: Semiconductor-on-oxide structures and related methods of forming such structures are disclosed. In one case, a method includes: forming a first dielectric layer over a substrate; forming a first conductive layer over the first dielectric layer, the first conductive layer including one of a metal or a silicide; forming a second dielectric layer over the first conductive layer; bonding a donor wafer to the second dielectric layer, the donor wafer including a donor dielectric and a semiconductor layer; cleaving the donor wafer to remove a portion of the donor semiconductor layer; forming at least one semiconductor isolation region from an unremoved portion of the donor semiconductor layer; and forming a contact to the first conductive layer through donor dielectric and the second dielectric layer.
    Type: Grant
    Filed: January 9, 2014
    Date of Patent: March 29, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: John E. Barth, Jr., Herbert L. Ho, Babar A. Khan, Kirk D. Peterson
  • Patent number: 9275735
    Abstract: An array organization and architecture for a content addressable memory (CAM) system. More specifically, a circuit is provided for that includes a first portion of the CAM configured to perform a first inequality operation implemented between 1 to n CAM entries. The circuit further includes a second portion of the CAM configured to perform a second inequality operation implemented between the 1 to n CAM entries. The first portion and the second portion are triangularly arranged side by side such that the first inequality operation and the second inequality operation are implemented between the 1 to n CAM entries using the same n wordlines.
    Type: Grant
    Filed: January 6, 2014
    Date of Patent: March 1, 2016
    Assignee: International Business Machines Corporation
    Inventors: John E. Barth, Jr., Dean L. Lewis
  • Publication number: 20160027789
    Abstract: Trench capacitors can be formed between lengthwise sidewalls of semiconductor fins, and source and drain regions of access transistors are formed in the semiconductor fins. A dummy gate structure is formed between end walls of a neighboring pair of semiconductor fins, and limits the lateral extent of raised source and drain regions that are formed by selective epitaxy. The dummy gate structure prevents electrical shorts between neighboring semiconductor fins. Gate spacers can be formed around gate structures and the dummy gate structures. The dummy gate structures can be replaced with dummy replacement gate structures or dielectric material portions, or can remain the same without substitution of any material. The dummy gate structures may consist of at least one dielectric material, or may include electrically floating conductive material portions.
    Type: Application
    Filed: October 3, 2015
    Publication date: January 28, 2016
    Inventors: John E. Barth, JR., Kangguo Cheng, Bruce B. Doris, Herbert L. Ho, Ali Khakifirooz, Babar A. Khan, Shom Ponoth, Kern Rim, Kehan Tian, Reinaldo A. Vega
  • Publication number: 20160027788
    Abstract: After formation of trench capacitors and source and drain regions and gate structures for access transistors, a dielectric spacer is formed on a first sidewall of each source region, while a second sidewall of each source region and sidewalls of drain regions are physically exposed. Each dielectric spacer can be employed as an etch mask during removal of trench top dielectric portions to form strap cavities for forming strap structures. Optionally, selective deposition of a semiconductor material can be performed to form raised source and drain regions. In this case, the raised source regions grow only from the first sidewalls and do not grow from the second sidewalls. The raised source regions can be employed as a part of an etch mask during formation of the strap cavities. The strap structures are formed as self-aligned structures that are electrically isolated from adjacent access transistors by the dielectric spacers.
    Type: Application
    Filed: October 3, 2015
    Publication date: January 28, 2016
    Inventors: John E. Barth, JR., Kangguo Cheng, Herbert L. Ho, Ali Khakifirooz, Ravikumar Ramachandran, Kern Rim, Reinaldo A. Vega
  • Publication number: 20150379396
    Abstract: Embodiments of the invention relate to providing transposable access to a synapse array using a recursive array layout. One embodiment comprises maintaining synaptic weights for multiple synapses connecting multiple axons and multiple neurons, wherein the synaptic weights are maintained based on a recursive array layout. The recursive array layout facilitates transposable access to the synaptic weights. A neuronal spike event between an axon and a neuron is communicated via a corresponding connecting synapse by accessing the synaptic weight of the corresponding connecting synapse in the recursive array layout.
    Type: Application
    Filed: September 4, 2015
    Publication date: December 31, 2015
    Inventors: John V. Arthur, John E. Barth, JR., Paul A. Merolla, Dharmendra S. Modha
  • Patent number: 9224437
    Abstract: A single-ended input sense amplifier uses a pass device to couple the input local bit-line to a global bit-line evaluation node. The sense amplifier also includes a pair of cross-coupled inverters, a first inverter of which has an input that coupled directly to the global bit-line evaluation node. The output of the second inverter is selectively coupled to the global bit-line evaluation node in response to a control signal, so that when the pass device is active, the local bit line charges or discharges the global bit-line evaluation node without being affected substantially by a state of the output of the second inverter. When the control signal is in the other state, the cross-coupled inverter forms a latch. An internal output control circuit of the second inverter interrupts the feedback provided by the second inverter in response to the control signal.
    Type: Grant
    Filed: October 31, 2013
    Date of Patent: December 29, 2015
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: John E. Barth, Jr., Abraham Mathews, Donald W. Plass, Kenneth J. Reyer
  • Patent number: 9224797
    Abstract: A structure forming a metal-insulator-metal (MIM) trench capacitor is disclosed. The structure comprises a multi-layer substrate having a metal layer and at least one dielectric layer. A trench is etched into the substrate, passing through the metal layer. The trench is lined with a metal material that is in contact with the metal layer, which comprises a first node of a capacitor. A dielectric material lines the metal material in the trench. The trench is filled with a conductor. The dielectric material that lines the metal material separates the conductor from the metal layer and the metal material lining the trench. The conductor comprises a second node of the capacitor.
    Type: Grant
    Filed: October 7, 2014
    Date of Patent: December 29, 2015
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: John E. Barth, Jr., Herbert L. Ho, Babar A. Khan, Kirk D. Peterson
  • Patent number: 9218564
    Abstract: Embodiments of the invention relate to providing transposable access to a synapse array using a recursive array layout. One embodiment comprises maintaining synaptic weights for multiple synapses connecting multiple axons and multiple neurons, wherein the synaptic weights are maintained based on a recursive array layout. The recursive array layout facilitates transposable access to the synaptic weights. A neuronal spike event between an axon and a neuron is communicated via a corresponding connecting synapse by accessing the synaptic weight of the corresponding connecting synapse in the recursive array layout.
    Type: Grant
    Filed: July 30, 2012
    Date of Patent: December 22, 2015
    Assignee: International Business Machines Corporation
    Inventors: John V. Arthur, John E. Barth, Jr., Paul A. Merolla, Dharmendra S. Modha
  • Publication number: 20150348977
    Abstract: A vertically integrated memory cell including a deep trench extending into a substrate, a trench capacitor located within the deep trench, and a vertical transistor at least partially embedded within the deep trench above the trench capacitor, the vertical transistor is in direct contact with and electrically coupled to the trench capacitor.
    Type: Application
    Filed: May 29, 2014
    Publication date: December 3, 2015
    Applicant: International Business Machines Corporation
    Inventors: John E. Barth, JR., Babar A. Khan
  • Patent number: 9160617
    Abstract: Embodiments of the invention relate to faulty recovery mechanisms for a three-dimensional (3-D) network on a processor array. One embodiment comprises a multidimensional switch network for a processor array. The switch network comprises multiple switches for routing packets between multiple core circuits of the processor array. The switches are organized into multiple planes. The switch network further comprises a redundant plane including multiple redundant switches. Multiple data paths interconnect the switches. The redundant plane is used to facilitate full operation of the processor array in the event of one or more component failures.
    Type: Grant
    Filed: September 28, 2012
    Date of Patent: October 13, 2015
    Assignee: International Business Machines Corporation
    Inventors: Rodrigo Alvarez-Icaza Rivera, John V. Arthur, John E. Barth, Jr., Andrew S. Cassidy, Subramanian Iyer, Paul A. Merolla, Dharmendra S. Modha
  • Publication number: 20150286923
    Abstract: Embodiments of the invention relate to providing transposable access to a synapse array using a recursive array layout. One embodiment comprises maintaining synaptic weights for multiple synapses connecting multiple axons and multiple neurons, wherein the synaptic weights are maintained based on a recursive array layout. The recursive array layout facilitates transposable access to the synaptic weights. A neuronal spike event between an axon and a neuron is communicated via a corresponding connecting synapse by accessing the synaptic weight of the corresponding connecting synapse in the recursive array layout.
    Type: Application
    Filed: July 30, 2012
    Publication date: October 8, 2015
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: John V. Arthur, John E. Barth, JR., Paul A. Merolla, Dharmendra S. Modha
  • Patent number: 9117547
    Abstract: Exemplary embodiments of the present invention disclose a method and system for asserting a voltage transition from a low voltage to a high voltage with a voltage difference between the low and high voltages on a word line with a word line driver logic that is composed of thin-oxide MOS transistors, wherein the thin-oxide MOS transistors experience less than the voltage difference on the word line between any two of a source, a drain, and a gate. In a step, charging the word line from the low voltage to an intermediate voltage level. In another step, charging the word line to the high voltage from the intermediate voltage level.
    Type: Grant
    Filed: May 6, 2013
    Date of Patent: August 25, 2015
    Assignee: International Business Machines Corporation
    Inventor: John E. Barth, Jr.
  • Patent number: 9093175
    Abstract: Apparatus and methods for signal margin centering for single-ended eDRAM sense amplifier. A plurality of DRAM cells is connected to an input side of a multiplexer by a first bitline. A single-ended sense amplifier is connected to an output side of the multiplexer by a second bitline. The single-ended sense amplifier has a switch voltage. The second bitline is precharged to a selected voltage level. The multiplexer passes a signal voltage from a selected one of the plurality of DRAM cells to the second bitline. The selected voltage level is selected such that reception of the signal voltage of a first type adjusts a voltage of the second bitline in a first direction and reception of the signal voltage of a second type adjusts the voltage of the second bitline in a second direction opposite from the first direction, centering the signal voltage around the switch voltage.
    Type: Grant
    Filed: March 27, 2013
    Date of Patent: July 28, 2015
    Assignee: International Business Machines Corporation
    Inventors: John E. Barth, Jr., John A. Fifield, Mark D. Jacunski
  • Publication number: 20150206885
    Abstract: Trench capacitors can be formed between lengthwise sidewalls of semiconductor fins, and source and drain regions of access transistors are formed in the semiconductor fins. A dummy gate structure is formed between end walls of a neighboring pair of semiconductor fins, and limits the lateral extent of raised source and drain regions that are formed by selective epitaxy. The dummy gate structure prevents electrical shorts between neighboring semiconductor fins. Gate spacers can be formed around gate structures and the dummy gate structures. The dummy gate structures can be replaced with dummy replacement gate structures or dielectric material portions, or can remain the same without substitution of any material. The dummy gate structures may consist of at least one dielectric material, or may include electrically floating conductive material portions.
    Type: Application
    Filed: January 20, 2014
    Publication date: July 23, 2015
    Applicant: International Business Machines Corporation
    Inventors: John E. Barth, Jr., Kangguo Cheng, Bruce B. Doris, Herbert L. Ho, Ali Khakifirooz, Babar A. Khan, Shom Ponoth, Kern Rim, Kehan Tian, Reinaldo A. Vega
  • Publication number: 20150206884
    Abstract: After formation of trench capacitors and source and drain regions and gate structures for access transistors, a dielectric spacer is formed on a first sidewall of each source region, while a second sidewall of each source region and sidewalls of drain regions are physically exposed. Each dielectric spacer can be employed as an etch mask during removal of trench top dielectric portions to form strap cavities for forming strap structures. Optionally, selective deposition of a semiconductor material can be performed to form raised source and drain regions. In this case, the raised source regions grow only from the first sidewalls and do not grow from the second sidewalls. The raised source regions can be employed as a part of an etch mask during formation of the strap cavities. The strap structures are formed as self-aligned structures that are electrically isolated from adjacent access transistors by the dielectric spacers.
    Type: Application
    Filed: January 20, 2014
    Publication date: July 23, 2015
    Applicant: International Business Machines Corporation
    Inventors: John E. Barth, Jr., Kangguo Cheng, Herbert L. Ho, Ali Khakifirooz, Ravikumar Ramachandran, Kern Rim, Reinaldo A. Vega