Abstract: Apparatus and methods for signal margin centering for single-ended eDRAM sense amplifier. A plurality of DRAM cells is connected to an input side of a multiplexer by a first bitline. A single-ended sense amplifier is connected to an output side of the multiplexer by a second bitline. The single-ended sense amplifier has a switch voltage. The second bitline is precharged to a selected voltage level. The multiplexer passes a signal voltage from a selected one of the plurality of DRAM cells to the second bitline. The selected voltage level is selected such that reception of the signal voltage of a first type adjusts a voltage of the second bitline in a first direction and reception of the signal voltage of a second type adjusts the voltage of the second bitline in a second direction opposite from the first direction, centering the signal voltage around the switch voltage.

Abstract: After formation of trench capacitors and source and drain regions and gate structures for access transistors, a dielectric spacer is formed on a first sidewall of each source region, while a second sidewall of each source region and sidewalls of drain regions are physically exposed. Each dielectric spacer can be employed as an etch mask during removal of trench top dielectric portions to form strap cavities for forming strap structures. Optionally, selective deposition of a semiconductor material can be performed to form raised source and drain regions. In this case, the raised source regions grow only from the first sidewalls and do not grow from the second sidewalls. The raised source regions can be employed as a part of an etch mask during formation of the strap cavities. The strap structures are formed as self-aligned structures that are electrically isolated from adjacent access transistors by the dielectric spacers.

Abstract: Trench capacitors can be formed between lengthwise sidewalls of semiconductor fins, and source and drain regions of access transistors are formed in the semiconductor fins. A dummy gate structure is formed between end walls of a neighboring pair of semiconductor fins, and limits the lateral extent of raised source and drain regions that are formed by selective epitaxy. The dummy gate structure prevents electrical shorts between neighboring semiconductor fins. Gate spacers can be formed around gate structures and the dummy gate structures. The dummy gate structures can be replaced with dummy replacement gate structures or dielectric material portions, or can remain the same without substitution of any material. The dummy gate structures may consist of at least one dielectric material, or may include electrically floating conductive material portions.

Abstract: An array organization and architecture for a content addressable memory (CAM) system. More specifically, a circuit is provided for that includes a first portion of the CAM configured to perform a first inequality operation implemented between 1 to n CAM entries. The circuit further includes a second portion of the CAM configured to perform a second inequality operation implemented between the 1 to n CAM entries. The first portion and the second portion are triangularly arranged side by side such that the first inequality operation and the second inequality operation are implemented between the 1 to n CAM entries using the same n wordlines.

Abstract: Embodiments of the invention provide an integrated circuit for an embedded dynamic random access memory (eDRAM), a semiconductor-on-insulator (SOI) wafer in which such an integrated circuit may be formed, and a method of forming an eDRAM in such an SOI wafer.

Abstract: Aspects of the present invention relate to a semiconductor-on-insulator (SOI) deep trench capacitor. One embodiment includes a method of forming a deep trench capacitor structure. The method includes: providing a SOI structure including a first and second trench opening in a semiconductor layer of the SOI structure, forming a doped semiconductor layer covering the semiconductor layer, forming a first dielectric layer covering the doped semiconductor layer, forming a node metal layer over the first dielectric layer, forming a second dielectric layer covering the node metal layer, filling a remaining portion of each trench opening with a metal layer to form an inner node in each of the trench openings, the metal layer including a plate coupling each of the inner nodes, and forming a node connection structure to conductively connect the node metal layer in the first trench opening with the node metal layer in the second trench opening.

Abstract: A single-ended input sense amplifier uses a pass device to couple the input local bit-line to a global bit-line evaluation node. The sense amplifier also includes a pair of cross-coupled inverters, a first inverter of which has an input that coupled directly to the global bit-line evaluation node. The output of the second inverter is selectively coupled to the global bit-line evaluation node in response to a control signal, so that when the pass device is active, the local bit line charges or discharges the global bit-line evaluation node without being affected substantially by a state of the output of the second inverter. When the control signal is in the other state, the cross-coupled inverter forms a latch. An internal output control circuit of the second inverter interrupts the feedback provided by the second inverter in response to the control signal.

Abstract: A memory having variable size blocks of failed memory addresses is connected to a TCAM storing data values of ranges of addresses in the memory. The ranges of addresses correspond to virtual addresses that, in combination with an offset, point away from failed memory addresses. A reduction circuit connected to the TCAM produces an output for each programmed range of addresses based on a virtual address. A priority encoder, connected to the reduction circuit, selects a first range from the reduction circuit and passes the first range to a random-access memory (RAM). Responsive to the virtual address bring an address in one of the ranges of addresses, the priority encoder passes the first range containing the virtual address to the RAM, which passes a corresponding offset value to the Adder based on the first range. The Adder calculates a physical memory address directing the virtual address to a functional memory location.

Abstract: Embodiments of the invention relate to faulty recovery mechanisms for a two-dimensional (2-D) network on a processor array. One embodiment comprises a processor array including multiple processors core circuits, and a redundant routing system for routing packets between the core circuits. The redundant routing system comprises multiple switches, wherein each switch corresponds to one or more core circuits of the processor array. The redundant routing system further comprises multiple data paths interconnecting the switches, and a controller for selecting one or more data paths. Each selected data path is used to bypass at least one component failure of the processor array to facilitate full operation of the processor array.

Abstract: A structure forming a metal-insulator-metal (MIM) trench capacitor is disclosed. The structure comprises a multi-layer substrate having a metal layer and at least one dielectric layer. A trench is etched into the substrate, passing through the metal layer. The trench is lined with a metal material that is in contact with the metal layer, which comprises a first node of a capacitor. A dielectric material lines the metal material in the trench. The trench is filled with a conductor. The dielectric material that lines the metal material separates the conductor from the metal layer and the metal material lining the trench. The conductor comprises a second node of the capacitor.

Abstract: A structure forming a metal-insulator-metal (MIM) trench capacitor is disclosed. The structure comprises a multi-layer substrate having a metal layer and at least one dielectric layer. A trench is etched into the substrate, passing through the metal layer. The trench is lined with a metal material that is in contact with the metal layer, which comprises a first node of a capacitor. A dielectric material lines the metal material in the trench. The trench is filled with a conductor. The dielectric material that lines the metal material separates the conductor from the metal layer and the metal material lining the trench. The conductor comprises a second node of the capacitor.

Abstract: An integrated circuit includes an active transistor laterally adjacent to a trench capacitor formed in a semiconductor substrate, the active transistor comprising a source junction and a drain junction, wherein a barrier layer is disposed along a periphery of the trench capacitor for isolating the trench capacitor; a passive transistor laterally spaced from the active transistor, wherein at least a portion of the trench capacitor is interposed between the active and passive transistors; an interlevel dielectric disposed upon the active and passive transistors; and a first conductive contact extending through the interlevel dielectric to the drain junction of the active transistor and the at least a portion of the trench capacitor between the active and passive transistors, wherein the first conductive contact electrically connects the trench capacitor to the drain junction of the active transistor.

Abstract: A complementary metal-oxide-semiconductor (CMOS) dynamic random access memory (DRAM) cell with sense amplifier is described. In one embodiment, the DRAM cell includes an n-type field-effect transistor (NFET), a p-type field-effect transistor (PFET), and a storage capacitor accessed through both the NFET and the PFET. A pair of bit lines is coupled to the DRAM cell. A sense amplifier with a single-ended read path reads data in the DRAM cell through only one of the bit lines and a data-dependent write-back path writes back data to the DRAM cell through either one of the bit lines. The bit line used by the sense amplifier to write back the data to the DRAM cell depends on the logical value of the data.

Abstract: Embodiments of the invention relate to providing transposable access to a synapse array using column aggregation. One embodiment comprises a neural network including a plurality of electronic axons, a plurality of electronic neurons, and a crossbar for interconnecting the axons with the neurons. The crossbar comprises a plurality of electronic synapses. Each synapse interconnects an axon with a neuron. The neural network further comprises a column aggregation module for transposable access to one or more synapses of the crossbar using column aggregation.

Abstract: Embodiments of the invention relate to providing transposable access to a synapse array using column aggregation. One embodiment comprises a neural network including a plurality of electronic axons, a plurality of electronic neurons, and a crossbar for interconnecting the axons with the neurons. The crossbar comprises a plurality of electronic synapses. Each synapse interconnects an axon with a neuron. The neural network further comprises a column aggregation module for transposable access to one or more synapses of the crossbar using column aggregation.

Abstract: Exemplary embodiments of the present invention disclose a method and system for asserting a voltage transition from a low voltage to a high voltage with a voltage difference between the low and high voltages on a word line with a word line driver logic that is composed of thin-oxide MOS transistors, wherein the thin-oxide MOS transistors experience less than the voltage difference on the word line between any two of a source, a drain, and a gate. In a step, charging the word line from the low voltage to an intermediate voltage level. In another step, charging the word line to the high voltage from the intermediate voltage level.

Abstract: Semiconductor-on-oxide structures and related methods of forming such structures are disclosed. In one case, a method includes: forming a first dielectric layer over a substrate; forming a first conductive layer over the first dielectric layer, the first conductive layer including one of a metal or a silicide; forming a second dielectric layer over the first conductive layer; bonding a donor wafer to the second dielectric layer, the donor wafer including a donor dielectric and a semiconductor layer; cleaving the donor wafer to remove a portion of the donor semiconductor layer; forming at least one semiconductor isolation region from an unremoved portion of the donor semiconductor layer; and forming a contact to the first conductive layer through donor dielectric and the second dielectric layer.

Abstract: A memory under repair having variable size blocks of failed memory addresses is connected to a TCAM comprising cells storing data values of ranges of the failed memory addresses in the memory under repair. The TCAM is connected to a virtual address line. Matchlines in the TCAM drive wordlines in a RAM connected to the TCAM. Each entry in the TCAM corresponds to one entry in the RAM and represents a single block of failed memory addresses. A first input of an XOR gate in an integrated circuit device is operatively connected to the RAM and a second input is operatively connected to the virtual address line. Responsive to a virtual address being an address in one of the ranges of failed memory addresses, the XOR gate calculates a physical memory address redirecting the virtual address to an unused good memory location in place of the failed memory address.

Abstract: Apparatus and methods for signal margin centering for single-ended eDRAM sense amplifier. A plurality of DRAM cells is connected to an input side of a multiplexer by a first bitline. A single-ended sense amplifier is connected to an output side of the multiplexer by a second bitline. The single-ended sense amplifier has a switch voltage. The second bitline is precharged to a selected voltage level. The multiplexer passes a signal voltage from a selected one of the plurality of DRAM cells to the second bitline. The selected voltage level is selected such that reception of the signal voltage of a first type adjusts a voltage of the second bitline in a first direction and reception of the signal voltage of a second type adjusts the voltage of the second bitline in a second direction opposite from the first direction, centering the signal voltage around the switch voltage.

Abstract: A complementary metal-oxide-semiconductor (CMOS) dynamic random access memory (DRAM) cell with sense amplifier is described. In one embodiment, the DRAM cell includes an n-type field-effect transistor (NFET), a p-type field-effect transistor (PFET), and a storage capacitor accessed through both the NFET and the PFET. A pair of bit lines is coupled to the DRAM cell. A sense amplifier with a single-ended read path reads data in the DRAM cell through only one of the bit lines and a data-dependent write-back path writes back data to the DRAM cell through either one of the bit lines. The bit line used by the sense amplifier to write back the data to the DRAM cell depends on the logical value of the data.