Patents by Inventor John E. Barth, Jr.

John E. Barth, Jr. has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8586444
    Abstract: A semiconductor structure and method of fabricating the same are disclosed. In an embodiment, the structure includes a first substrate having a buried plate or plates in the substrate. Each buried plate includes at least one buried plate contact, and a plurality of deep trench capacitors disposed about the at least one buried plate contact. A first oxide layer is disposed over the first substrate. The deep trench capacitors and buried plate contacts in the first substrate may be accessed for use in a variety of memory and decoupling applications.
    Type: Grant
    Filed: March 23, 2012
    Date of Patent: November 19, 2013
    Assignee: International Business Machines Corporation
    Inventors: Jennifer E. Appleyard, John E. Barth, Jr., John B. DeForge, Herbert L. Ho, Babar A. Khan, Kirk D. Peterson, Andrew A. Turner
  • Publication number: 20130285193
    Abstract: A structure forming a metal-insulator-metal (MIM) trench capacitor is disclosed. The structure comprises a multi-layer substrate having a metal layer and at least one dielectric layer. A trench is etched into the substrate, passing through the metal layer. The trench is lined with a metal material that is in contact with the metal layer, which comprises a first node of a capacitor. A dielectric material lines the metal material in the trench. The trench is filled with a conductor. The dielectric material that lines the metal material separates the conductor from the metal layer and the metal material lining the trench. The conductor comprises a second node of the capacitor.
    Type: Application
    Filed: April 27, 2012
    Publication date: October 31, 2013
    Applicant: International Business Machines Corporation
    Inventors: John E. Barth, JR., Herbert L. Ho, Babar A. Khan, Kirk D. Peterson
  • Publication number: 20130256830
    Abstract: Semiconductor-on-oxide structures and related methods of forming such structures are disclosed. In one case, a method includes: forming a first dielectric layer over a substrate; forming a first conductive layer over the first dielectric layer, the first conductive layer including one of a metal or a silicide; forming a second dielectric layer over the first conductive layer; bonding a donor wafer to the second dielectric layer, the donor wafer including a donor dielectric and a semiconductor layer; cleaving the donor wafer to remove a portion of the donor semiconductor layer; forming at least one semiconductor isolation region from an unremoved portion of the donor semiconductor layer; and forming a contact to the first conductive layer through donor dielectric and the second dielectric layer.
    Type: Application
    Filed: March 30, 2012
    Publication date: October 3, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: John E. Barth, JR., Herbert L. Ho, Babar A. Khan, Kirk D. Peterson
  • Publication number: 20130262792
    Abstract: An embodiment is a method includes writing a first set of memory device parameters to a first mode register in a memory device, wherein the first set of memory device parameters correspond to a first frequency, monitoring selected parameters for the memory system while the memory device operates at the first frequency and predicting a second frequency that the memory device will operate at subsequent to the first frequency, the predicting being based on the monitored selected parameters. The method further includes writing a second set of memory device parameters to second mode register in the memory device, receiving a frequency change request at a memory controller associated with the memory device, the frequency change request to operate at a new frequency and updating the first mode register with the second set of memory device parameters from the second mode register responsive to the new frequency being equal to the second frequency.
    Type: Application
    Filed: March 27, 2012
    Publication date: October 3, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: John E. Barth, JR., Joab D. Henderson, Ryan J. Pennington, Anuwat Saetow, Robert B. Tremaine, Kenneth L. Wright
  • Publication number: 20130249052
    Abstract: A semiconductor structure and method of fabricating the same are disclosed. In an embodiment, the structure includes a first substrate having a buried plate or plates in the substrate. Each buried plate includes at least one buried plate contact, and a plurality of deep trench capacitors disposed about the at least one buried plate contact. A first oxide layer is disposed over the first substrate. The deep trench capacitors and buried plate contacts in the first substrate may be accessed for use in a variety of memory and decoupling applications.
    Type: Application
    Filed: March 23, 2012
    Publication date: September 26, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jennifer E. Appleyard, John E. Barth, JR., John B. DeForge, Herbert L. Ho, Babar A. Khan, Kirk D. Peterson, Andrew A. Turner
  • Patent number: 8492819
    Abstract: A structure and method of making a field effect transistor (FET) embedded dynamic random access memory (eDRAM) cell array, which includes: a buried silicon strap extending into a buried oxide (BOX) layer of a silicon-on-insulator (SOI) substrate; a recessed trench capacitor extending down into the substrate layer of the SOI substrate; a lateral surface of a conductive top plate formed on the recessed trench capacitor that contacts a first lateral surface of the buried silicon strap; a dielectric cap disposed above the conductive top plate; a first FET formed from the silicon layer of the SOI substrate, in which a source/drain region of the first FET contacts a second lateral surface of the buried silicon strap; and a passing wordline disposed on a portion of the dielectric cap opposite to and separate from the buried silicon strap and connected to a gate of a second FET in an adjacent row of the FET eDRAM cell array.
    Type: Grant
    Filed: July 14, 2011
    Date of Patent: July 23, 2013
    Assignee: International Business Machines Corporation
    Inventors: Brent A. Anderson, John E. Barth, Jr., Edward J. Nowak, Jed H. Rankin
  • Publication number: 20130114361
    Abstract: Disclosed are a sense amplifier and a memory circuit that incorporates it. The amplifier comprises cross-coupled inverters, each with a pull-down transistor and a pull-up transistor connected in series. One inverter has a voltage-controlled switch controlling the electrical connection between drain nodes of the transistors. During a read operation, the pull-up transistor drain node is pre-charged high and the pull-down transistor drain node receives an input signal. The switch is tripped, thereby making the electrical connection only when the voltage at the pull-down transistor drain node is less than the switch's trip voltage. In this case, the sense node discharges to the same level as the input signal. Otherwise, the switch prevents the electrical connection and the sense node remains high. The trip voltage depends on a reference voltage, which can be variable, thereby allowing the sensitivity of the sense amplifier to be selectively adjusted. Also disclosed are associated methods.
    Type: Application
    Filed: November 3, 2011
    Publication date: May 9, 2013
    Applicant: International Business Machines Corporation
    Inventors: John E. Barth, JR., Donald W. Plass, Adis Vehabovic
  • Publication number: 20130015515
    Abstract: A structure and method of making a field effect transistor (FET) embedded dynamic random access memory (eDRAM) cell array, which includes: a buried silicon strap extending into a buried oxide (BOX) layer of a silicon-on-insulator (SOI) substrate; a recessed trench capacitor extending down into the substrate layer of the SOI substrate; a lateral surface of a conductive top plate formed on the recessed trench capacitor that contacts a first lateral surface of the buried silicon strap; a dielectric cap disposed above the conductive top plate; a first FET formed from the silicon layer of the SOI substrate, in which a source/drain region of the first FET contacts a second lateral surface of the buried silicon strap; and a passing wordline disposed on a portion of the dielectric cap opposite to and separate from the buried silicon strap and connected to a gate of a second FET in an adjacent row of the FET eDRAM cell array.
    Type: Application
    Filed: July 14, 2011
    Publication date: January 17, 2013
    Applicant: International Business Machines Corporation
    Inventors: Brent A. Anderson, John E. Barth, JR., Edward J. Nowak, Jed H. Rankin
  • Patent number: 8263472
    Abstract: A semiconductor includes a bulk substrate of a first polarity type, a buried insulator layer disposed on the bulk substrate, an active semiconductor layer disposed on top of the buried insulator layer including a shallow trench isolation region and a diffusion region of the first polarity type, a band region of a second polarity type disposed directly beneath the buried insulator layer and forming a conductive path, a well region of the second polarity type disposed in the bulk substrate and in contact with the band region, a deep trench filled with a conductive material of the first polarity type disposed within the well region, and an electrostatic discharge (ESD) protect diode defined by a junction between a lower portion of the deep trench and the well region.
    Type: Grant
    Filed: December 13, 2011
    Date of Patent: September 11, 2012
    Assignee: International Business Machines Corporation
    Inventors: John E. Barth, Jr., Kerry Bernstein
  • Publication number: 20120205732
    Abstract: An integrated circuit includes an active transistor laterally adjacent to a trench capacitor formed in a semiconductor substrate, the active transistor comprising a source junction and a drain junction, wherein a barrier layer is disposed along a periphery of the trench capacitor for isolating the trench capacitor; a passive transistor laterally spaced from the active transistor, wherein at least a portion of the trench capacitor is interposed between the active and passive transistors; an interlevel dielectric disposed upon the active and passive transistors; and a first conductive contact extending through the interlevel dielectric to the drain junction of the active transistor and the at least a portion of the trench capacitor between the active and passive transistors, wherein the first conductive contact electrically connects the trench capacitor to the drain junction of the active transistor.
    Type: Application
    Filed: April 24, 2012
    Publication date: August 16, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: John E. Barth, JR., Kangguo Cheng, Michael Sperling, Geng Wang
  • Patent number: 8238168
    Abstract: A direct sense memory array architecture and method of operation includes a plurality of memory cells where a bit-line restore voltage level is optimized to reduce memory cell leakage during a first inactive period, and a bit-line preset voltage level is optimized for signal sensing during a second active period. The architecture includes a sense head having of a pair of cross coupled gated inverters. Each of the gated inverters is responsive to a first and second gate control signal which can independently gate a power supply to the inverter circuit within each gated inverter. During the second active period, a first gated inverter senses the data state on the first bit-line, and a second gated inverter performs a preset and write-back function on the first bit-line.
    Type: Grant
    Filed: April 30, 2010
    Date of Patent: August 7, 2012
    Assignee: International Business Machines Corporation
    Inventor: John E. Barth, Jr.
  • Patent number: 8227310
    Abstract: A method of forming an integrated circuit comprises: providing a semiconductor topography comprising an active transistor laterally adjacent to a trench capacitor formed in a semiconductor substrate, the active transistor comprising a source junction and a drain junction, wherein a barrier layer is disposed along a periphery of the trench capacitor for isolating the trench capacitor; forming an interlevel dielectric across the semiconductor topography; concurrently etching (i) a first opening through the interlevel dielectric to the drain junction of the active transistor and the trench capacitor, and (ii) a second opening through the interlevel dielectric to the source junction of the active transistor; and filling the first opening and the second opening with a conductive material to form a strap for electrically connecting the trench capacitor to the drain junction of the active transistor and to also form a contact for electrically connecting the source junction to an overlying level of the integrated cir
    Type: Grant
    Filed: August 6, 2008
    Date of Patent: July 24, 2012
    Assignee: International Business Machines Corporation
    Inventors: John E. Barth, Jr., Kangguo Cheng, Michael Sperling, Geng Wang
  • Publication number: 20120083091
    Abstract: A semiconductor includes a bulk substrate of a first polarity type, a buried insulator layer disposed on the bulk substrate, an active semiconductor layer disposed on top of the buried insulator layer including a shallow trench isolation region and a diffusion region of the first polarity type, a band region of a second polarity type disposed directly beneath the buried insulator layer and forming a conductive path, a well region of the second polarity type disposed in the bulk substrate and in contact with the band region, a deep trench filled with a conductive material of the first polarity type disposed within the well region, and an electrostatic discharge (ESD) protect diode defined by a junction between a lower portion of the deep trench and the well region.
    Type: Application
    Filed: December 13, 2011
    Publication date: April 5, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: John E. Barth, JR., Kerry Bernstein
  • Patent number: 8133772
    Abstract: A semiconductor structure is disclosed. The semiconductor structure includes an active semiconductor layer, a semiconductor device having a gate disposed on top of the active semiconductor layer, and source and drain regions and a body/channel region disposed within the active semiconductor layer, an insulator layer having a first and second side, the first side being adjacent to the active semiconductor layer, a substrate disposed adjacent to the second side of the insulator layer, a deep trench capacitor disposed under the body/channel region of the semiconductor device. The deep trench capacitor electrically connects with and contacts the body/channel region of the semiconductor device, and is located adjacent to the gate of the semiconductor device. The semiconductor structure increases a critical charge Qcrit, thereby reducing a soft error rate (SER) of the semiconductor device.
    Type: Grant
    Filed: March 30, 2011
    Date of Patent: March 13, 2012
    Assignee: International Business Machines Corporation
    Inventors: John E. Barth, Jr., Kerry Bernstein, Ethan H. Cannon, Francis R. White
  • Patent number: 8132131
    Abstract: Disclosed is design structure including an integrated circuit having a system for moving a failing address into a new FAR by utilizing the functional compare circuitry during BIST of redundant memory elements. Disclosed is an any-for-any scheme that eliminates the tri-state address bus. The design structure allows for easy, discrete scaling with the addition of more FARs, while also allowing larger addresses with no additional control circuit overhead.
    Type: Grant
    Filed: May 28, 2008
    Date of Patent: March 6, 2012
    Assignee: International Business Machines Corporation
    Inventors: John E. Barth, Jr., Stephen F. Sliva
  • Patent number: 8125840
    Abstract: An approach that provides reference level generation with offset compensation for a sense amplifier is described. In one embodiment, an arbitrary reference level is generated to provide an offset that compensates for device mismatch and voltage threshold of a sense amplifier.
    Type: Grant
    Filed: August 31, 2009
    Date of Patent: February 28, 2012
    Assignee: International Business Machines Corporation
    Inventors: John E. Barth, Jr., Erik A. Nelson
  • Patent number: 8097525
    Abstract: A semiconductor structure includes at least one silicon substrate having first and second planar surfaces, and at least one through silicon via filled with a conductive material and extending vertically through the first planar surface of the at least one silicon substrate to the second planar surface thereof. The through silicon via forms a vertical interconnection between a plurality of electronic circuits and an amount of dielectric insulation surrounding the through silicon via is varied based on a defined function of the through silicon via.
    Type: Grant
    Filed: August 29, 2008
    Date of Patent: January 17, 2012
    Assignee: International Business Machines Corporation
    Inventors: John E. Barth, Jr., Kerry Bernstein
  • Patent number: 8080851
    Abstract: A semiconductor structure is disclosed. The semiconductor structure includes a bulk substrate of a first polarity type, a buried insulator layer disposed on the bulk substrate, an active semiconductor layer disposed on top of the buried insulator layer including a shallow trench isolation region and a diffusion region of the first polarity type, a band region of a second polarity type disposed directly beneath the buried insulator layer and forming a conductive path, a well region of the second polarity type disposed in the bulk substrate and in contact with the band region, a deep trench filled with a conductive material of the first polarity type disposed within the well region, and an electrostatic discharge (ESD) protect diode defined by a junction between a lower portion of the deep trench and the well region.
    Type: Grant
    Filed: August 29, 2008
    Date of Patent: December 20, 2011
    Assignee: International Business Machines Corporation
    Inventors: John E. Barth, Jr., Kerry Bernstein
  • Patent number: 8053303
    Abstract: A semiconductor structure is disclosed. The semiconductor structure includes an active semiconductor layer, a semiconductor device having a gate disposed on top of the active semiconductor layer, and source and drain regions and a body/channel region disposed within the active semiconductor layer, an insulator layer having a first and second side, the first side being adjacent to the active semiconductor layer, a substrate disposed adjacent to the second side of the insulator layer, a body contact disposed under the body/channel region and in the insulator layer. The body contact electrically connects with and contacts with the body/channel region of the semiconductor device and the substrate, to thereby form an ohmic contact and to eliminate floating body effects.
    Type: Grant
    Filed: March 30, 2011
    Date of Patent: November 8, 2011
    Assignee: International Business Machines Corporation
    Inventors: John E. Barth, Jr., Kerry Bernstein, Francis R. White
  • Publication number: 20110267916
    Abstract: A direct sense memory array architecture and method of operation includes a plurality of memory cells where a bit-line restore voltage level is optimized to reduce memory cell leakage during a first inactive period, and a bit-line preset voltage level is optimized for signal sensing during a second active period. The architecture includes a sense head having of a pair of cross coupled gated inverters. Each of the gated inverters is responsive to a first and second gate control signal which can independently gate a power supply to the inverter circuit within each gated inverter. During the second active period, a first gated inverter senses the data state on the first bit-line, and a second gated inverter performs a preset and write-back function on the first bit-line.
    Type: Application
    Filed: April 30, 2010
    Publication date: November 3, 2011
    Applicant: International Business Machines Corporation
    Inventor: John E. Barth, JR.