Abstract: An electrical fuse circuit design for reducing the testing time for a semiconductor device manufactured with redundant eFuse circuitry. A two-to-one multiplexer (MUX) is provided at each eFuse circuit in addition to the fuse latch and pattern latch. Information on which fuse is to be blown is stored in the fuse's pattern latch. The output of the pattern latch is ANDed with a program input to provide a select signal for the MUX. Based on the select signal, the MUX allows the shifted “1” to either go to the next latch in the shift chain or bypass the next latch or latches in the shift chain when the next fuse(s) is not to be blown. Accordingly, the invention enables only those fuse latches associated with fuses that are to be blown to hold up the propagation of the shifted “1” to the next eFuse circuits.

Abstract: An ECC based system and method within an integrated circuit memory for self-repair of a failed memory element is disclosed. The method includes processing, within the integrated circuit, data and check bits retrieved from addressed memory locations therein. The locations of memory failures are automatically recorded within the integrated circuit. Logic circuits within the integrated circuit automatically identify failure patterns based on the locations. Based on the identified failure patterns, logic circuits within the integrated circuit then permanently replace a failed memory element with an appropriate redundancy element, using devices such as electronic fuse or antifuse. In this manner, the integrated circuit automatically identifies and effects self repair of a failed memory element therein.

Abstract: A method for small signal sensing during a read operation of a static random access memory (SRAM) cell includes coupling a pair of complementary sense amplifier data lines to a corresponding pair of complementary bit lines associated with the SRAM cell, and setting a sense amplifier so as to amplify a signal developed on the sense amplifier data lines, wherein the bit line pair remains coupled to the sense amplifier data lines at the time the sense amplifier is set.

Abstract: An electronic memory system includes a memory array of a number of pair of bitlines comprising a true bitline and a complementary bitline. A first normal cell connects to the true bitline (BT0) and a second normal cell connects to the complementary bitline (BC0). A first reference cell connects to the true bitline and a second reference cell connects to the complementary bitline. A clock generates timing pulses including short circuiting-equalization pulses and selectively provides reference potential pulses in a reference potential mode of operation. A sense amplifier has a true terminal connected to the true bitline and a complementary terminal connected to the complementary bitline. An equalization short circuiting circuit connects to the clock and to the true bitline and the complementary bitline for short circuiting the true bitline and the complementary bitline together in response to the short circuiting pulses to equalize the electric potential thereon as a function of short circuiting-equalization.

Abstract: A bitline structure for a memory array includes a first pair of complementary bitlines and a second pair of complementary bitlines. Both the first and second pair of complementary bitlines have a twist at a location corresponding to about ¼ of the total length of the bitline structure. The second pair of complementary bitlines further have a twist at a location corresponding to about ½ of the total length of the bitline structure, and both the first and second pair of complementary bitlines have a twist at a location corresponding to about ¾ the total length of the bitline structure.

Abstract: A self-timed data transmission system includes a data bit group defined by at least two data bits to be transmitted from a corresponding plurality of transmitting storage elements. A corresponding plurality of data receiving storage elements receives the data transmitted from said transmitting storage elements. Encoding logic is used for encoding the transmitted data from the transmitting storage elements, wherein the encoded transmitted data is coupled to a plurality of data lines. The encoding logic is further configured so as to result in only one of the plurality of data lines being activated during a given data transmission cycle.

Abstract: A concurrent refresh mode is realized by allowing a memory array to be refreshed by way of a refresh bank select signal, while concurrently enabling a memory access operation in another array. The refresh address management is greatly simplified by the insertion of row address counter integrated within each array. In the preferred embodiment, any combination of a plurality of the memory arrays is refreshed simultaneously while enabling a memory access operation. This concurrent mode also supports a multi-bank operation.

Abstract: A control circuit for a memory array device having one or more memory storage cells associated therewith includes a true bit-line and a complementary bit-line coupled to the one or more memory storage cells. A sense amplifier is coupled to the true and complementary bit-lines, the sense amplifier being configured to amplify a small voltage difference between the true bit-line and the complementary bit-line to a full level signal at predetermined high and low logic voltage levels. A bit-switch pair selectively couples the bit-lines and said sense amplifier to fan-in circuitry, and is further configured so as to couple the fan-in circuitry to the true and complementary bit-lines prior to the activation of a wordline associated with a selected cell for a write operation thereto. Thereby, the write operation to the selected cell is commenced prior to the completion of time associated with signal development on the true and complementary bit-lines.

Abstract: A method of memory BIST (Built-In Self Test) and memory repair that stores a redundancy calculation on-chip, as opposed to scanning this data off-chip for later use. This method no longer requires level-sensitive scan design (LSSD) scanning of memory redundancy data off-chip to the tester, and therefore does not require re-contacting of the chip for electrical fuse blow.

Abstract: A sensing circuit for performing a direct read of a DRAM memory cell by using a high transfer ratio and a single ended read of a single bitline, wherein a limited number of memory cells are connected to the single bitline to limit the capacitance thereof to provide the high transfer ration. The direct read circuit includes four transistor devices, with three devices preferentially being nFETs. The direct read circuit provides a self-timed write back of data to a memory cell after the data is destructively read from the memory cell in a read operation, provides significant electrical power savings relative to prior art read circuits, as a read operation of a data 0 does not utilize any significant electrical power, and in a folded bitline architecture provides improved noise immunity as each non-active bitline shields an adjacent active bitline.

Abstract: A growable multibank DRAM macro is achieved with a flexible multibank interface which can be grown without redesign and without change of appearance/behavior to the customer. The interface is preferably characterized by the presence of bank select inputs (pins) which permit selection of one or more banks of the macro. The banks preferably each have respective row decode circuitry and respective limited repair redundancy.

Abstract: A method and circuit for a self timed DRAM. The circuit includes interlock circuits coupled to an extension of the DRAM. The extension does not store “real” data but mimics the operations of the DRAM. The interlock circuits, in conjunction with the extension monitor and control read and write timings of the DRAM and self adjust these timings via feedback. To properly track DRAM cell timings, the interlock circuits and extension use the same cell design and load conditions as the DRAM. The method includes: activating a wordline and reference wordline, interlocking the sense amplifiers, column select and write back functions of the primary DRAM array by monitoring the identical reference cells and the state of the bitline in the extension DRAM array.

Abstract: A column redundancy system is disclosed for a memory array having a page structure organized into columns and data lines. In an exemplary embodiment of the invention, the system includes a steering logic network for coupling a memory input/output (I/O) device to the memory array. A storage register is in communication with the steering logic network, the storage register for storing location information for defective data lines in the memory array. During a memory operation, the location information stored in the storage register is transmitted to the steering logic network, the storage register further having the location information loaded therein prior to the memory operation. Thereby, the steering logic network prevents any of the defective data lines from being coupled to the I/O device.

Abstract: Addition of capacitance to the storage nodes of static random access memory cells and other types of integrated circuits substantially increases Qcrit and substantially eliminates soft errors due to alpha particles; susceptibility to which would otherwise increase as integrated circuits are scaled to smaller sizes and manufactured at increased integration densities. Formation of the added capacitance as deep trench capacitors avoids any constraint on circuit or memory cell layout. Degradation of performance is avoided and performance potentially improved by permitting alteration of proportions of pull-down and pass gate transistors in view of the increased stability imparted by the added capacitors. One of the capacitor electrodes is preferably shorted to the supply voltage through an impurity well. Thus, the memory cell size can be reduced while greatly reducing susceptibility to soft errors; contrary to the effects of scaling at current and foreseeable feature size regimes.

Abstract: A system and method is disclosed for writing early within a memory cycle by injecting a small voltage difference signal prior to setting a sense amplifier, and thereafter setting the sense amplifier which amplifies the small voltage signal to predetermined high and low voltage logic levels for writing to the memory cell. In this way, writing can complete in about the same time as reading, without risking corruption of data on adjacent bitlines in the memory. Local bitswitches apply first and second write voltages having a small voltage difference to a true bitline and a reference bitline prior to setting the sense amplifier.

Abstract: A system and method is disclosed for writing early within a memory cycle by holding only one of a true bitline and a reference bitline at a fixed potential, e.g. ground, when the sense amplifier is set. The sense amplifier amplifies a small voltage difference between the true bitline and the reference bitline to predetermined high and low voltage logic levels to write a datum to the memory cell. In this way, writing can complete in about the same time as reading, without risking corruption of data on adjacent bitlines in the memory. The bitlines are precharged to a fixed potential in a conduction path through the bitswitches, rather than using local precharge devices at the sense amplifier. To write, bitswitches and write path transistors apply the fixed potential to one of the true bitline and the reference bitline.

Abstract: A twin cell memory array which includes shielded bitlines is provided. The twin cell memory array includes a plurality of bitlines arranged in one direction in parallel with each other, with every other bitline constituting a bitline pair; a plurality of sense amplifiers being arranged in a line, wherein each sense amplifier is interconnected to two adjacent bitline pairs; a plurality of wordlines arranged in a direction intersecting said plurality of bitlines, wherein a single wordline is coupled to every other bitline; and isolation means located on said plurality of bitlines, said isolation means being arranged such that when every other bitline of said plurality of bitlines is being sensed, the adjacent bitlines of said plurality of bitlines are held at a predetermined potential by a clamping means.

Abstract: A method is provided for flash writing to multiple cells of a memory array. Initially, a first set of word lines, each of which controls connection of a memory cell of a first set of memory cells to a first bit line of a bit line pair, is turned on. The voltage between the two bit lines of the bit line pair is then equalized so that the charge on the first bit line of the bit line pair is higher than the charge on the second bit line of the bit line pair. Next, a sense amplifier attached to the bit line pair is turned on to sense a difference in charge between the bit line pair and to charge the first set of memory cells. Then a second set of word lines, each of which controls connection of a memory cell of a second set of memory cells to the second bit line is turned on. Finally, the word lines previously turned on are shut off and then the sense amplifier is shut off.

Abstract: A DRAM having on-chip ECC and both bit and word redundancy that have been optimized to support the on-chip ECC. The bit line redundancy features a switching network that provides an any-for-any substitution for the bit lines in the associated memory array. The word line redundancy is provided in a separate array section, and has been optimized to maximize signal while reducing soft errors. The array stores data in the form of error correction words (ECWs) on each word line. A first set of data lines (formed in a zig-zag pattern to minimize unequal capacitive loading on the underlying bit lines) are coupled to read out an ECW as well as the redundant bit lines. A second set of data lines receive the ECW as corrected by bit line redundancy, and a third set of data lines receive the ECW as corrected by the word line redundancy. The third set of data lines are coupled to the ECC block, which corrects errors encountered in the ECW.

Abstract: Low power addressing systems are provided which include a given number of memory segments, each having word and bit/sense lines, a given number of decoders coupled to the given number of memory segments for selecting one word line in each of the memory segments, a first plurality of transmission gate systems, each having first and second transmission gates, with each of the gates being coupled to a different one of the decoders, a second decoder having the first plurality of outputs, each of the outputs being coupled to a respective one of the transmission gate systems, first control circuits for selectively activating the first and second gates in each of the first plurality of transmission gate systems, a second given number of decoders coupled to the given number of memory segments for selecting one bit/sense line in each of the memory segments, a second plurality of transmission gate systems, each having first and second transmission gates, with each of the gates of the second plurality of transmission ga