Patents by Inventor John J. Browne

John J. Browne has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10601738
    Abstract: Technologies for buffering received network packet data include a compute device with a network interface controller (NIC) configured to determine a packet size of a network packet received by the NIC and identify a preferred buffer size between a small buffer and a large buffer. The NIC is further configured to select, from the descriptor, a buffer pointer based on the preferred buffer size, wherein the buffer pointer comprises one of a small buffer pointer corresponding to a first physical address in memory allocated to the small buffer or a large buffer pointer corresponding to a second physical address in memory allocated to the large buffer. Additionally, the NIC is configured to store at least a portion of the network packet in the memory based on the selected buffer pointer. Other embodiments are described herein.
    Type: Grant
    Filed: June 30, 2018
    Date of Patent: March 24, 2020
    Assignee: Intel Corporation
    Inventors: Bruce Richardson, Chris MacNamara, Patrick Fleming, Tomasz Kantecki, Ciara Loftus, John J. Browne, Patrick Connor
  • Patent number: 10592383
    Abstract: A method for monitoring health of processes includes a compute device having a performance monitoring parameter manager and an analytics engine. The compute device accesses performance monitoring parameters associated with a monitored process of the compute device. The compute device samples one or more hardware counters associated with the monitored process and applies a performance monitor filter to the sampled one or more hardware counters to generate hardware counter values. The compute device performs a process fault check on the monitored process based on the hardware counter values and the performance monitoring parameters.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: March 17, 2020
    Assignee: Intel Corporation
    Inventors: John J. Browne, Tomasz Kantecki, Wojciech Andralojc, Timothy Verrall, Maryam Tahhan, Eoin Walsh, Damien Power, Chris MacNamara
  • Publication number: 20200084202
    Abstract: Various approaches for implementing attestation using an attestation token are described. In an edge computing system deployment, an edge computing device includes an attestable feature (e.g., resource, service, entity, property, etc.) which is accessible from use of an attestation token, by the operations of: obtaining a first instance of a token that provides proof of attestation for an accessible feature of the edge computing device, with the token including data to indicate trust level designations for the feature as attested by an attestation provider; receiving, from a prospective user of the feature, a request to use the feature and a second instance of the token, with the second instance of the token originating from the attestation provider; and providing access to the feature based on a verification of the instances of the token, by using the verification to confirm attestation of the trust level designations for the feature.
    Type: Application
    Filed: November 14, 2019
    Publication date: March 12, 2020
    Inventors: Ned M. Smith, John J. Browne, Kapil Sood, Francesc Guim Bernat, Kshitij Arun Doshi, Rajesh Poornachandran, Tarun Viswanathan, Manish Dave
  • Patent number: 10567263
    Abstract: Technologies for simulating service degradation in telemetry data include a simulator device. The simulator device is to identify a telemetry data stream from a production system to a first management system. The simulator device is also to fork a copy of the telemetry data stream for transmission to a second management system, determine perturbations associated with a determined service degradation type, and apply the perturbations to the forked telemetry data stream. Other embodiments are also described and claimed.
    Type: Grant
    Filed: August 19, 2016
    Date of Patent: February 18, 2020
    Assignee: Intel Corporation
    Inventors: Michael Hingston McLaughlin Bursell, Stephen T. Palermo, John J. Browne, Chris MacNamara, Pierre Laurent
  • Patent number: 10540196
    Abstract: Embodiments may be generally directed to techniques to receive an indication to perform a migration of a virtual environment and services from a first host system to a second host system, initiate the migration of the virtual environment and services by communicating information associated with the virtual environment and services from the first host system to a second host system, and communicate a data structure having a value to a peer system, the value set to cause the peer system to halt communication of information for the virtual environment to the first host system.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: January 21, 2020
    Assignee: INTEL CORPORATION
    Inventors: Chris MacNamara, John J. Browne
  • Publication number: 20190384348
    Abstract: A processing device includes a plurality of processing cores, a control register, associated with a first processing core of the plurality of processing cores, to store a first base clock frequency value at which the first processing core is to run, and a power management circuit to receive a base clock frequency request comprising a second base clock frequency value, store the second base clock frequency value in the control register to cause the first processing core to run at the second base clock frequency value, and expose the second base clock frequency value on a hardware interface associated with the power management circuit.
    Type: Application
    Filed: February 24, 2017
    Publication date: December 19, 2019
    Inventors: Vasudevan SRINIVASAN, Krishnakanth V. SISTLA, Corey D. GOUGH, Ian M. STEINER, Nikhil GUPTA, Vivek GARG, Ankush VARMA, Sujal A. VORA, David P. LERNER, Joseph M. SULLIVAN, Nagasubramanian GURUMOORTHY, William J. BOWHILL, Venkatesh RAMAMURTHY, Chris MACNAMARA, John J. BROWNE, Ripan DAS
  • Publication number: 20190327190
    Abstract: Technologies for scalable packet reception and transmission include a network device. The network device is to establish a ring that is defined as a circular buffer and includes a plurality of slots to store entries representative of packets. The network device is also to generate and assign receive descriptors to the slots in the ring. Each receive descriptor includes a pointer to a corresponding memory buffer to store packet data. The network device is further to determine whether the NIC has received one or more packets and copy, with direct memory access (DMA) and in response to a determination that the NIC has received one or more packets, packet data of the received one or more packets from the NIC to the memory buffers associated with the receive descriptors assigned to the slots in the ring.
    Type: Application
    Filed: July 2, 2019
    Publication date: October 24, 2019
    Inventors: John J. Browne, Tomasz Kantecki, Chris MacNamara, Pierre Laurent, Sean Harte
  • Patent number: 10433035
    Abstract: An apparatus includes telemetry registers, a memory, and a virtualized telemetry controller. The memory may store a set of telemetry profiles, including a first telemetry profile specifying a collection trigger, a set of telemetry registers, and a telemetry data destination. The virtualized telemetry controller may be to: detect a condition satisfying the collection trigger specified in the first telemetry profile; in response to a detection of the condition, read telemetry values from the set of telemetry registers specified in the first telemetry profile; generate a telemetry container including the telemetry values; and send the telemetry container to the telemetry data destination specified in the first telemetry profile.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: October 1, 2019
    Assignee: Intel Corporation
    Inventors: Ronen Chayat, Andrey Chilikin, John J. Browne, Chris MacNamara, Tomasz Kantecki
  • Publication number: 20190280991
    Abstract: At a network interface, received packets are classified according to priority level or traffic class. Based on an assigned priority level, a received packet can be allocated to use a descriptor queue associated with the assigned priority level. The descriptor queue can have an associated buffer region in which portions of received packets are stored. The length of the descriptor queue can be dependent on the priority level such that a highest priority descriptor queue can be longer than a lowest priority descriptor queue. The size of the buffer can be dependent on the priority level such that a highest priority level can be assigned a separate buffer space of different size than that assigned to a lower priority level. A polling rate for a descriptor queue can be configured based on a priority level such that a highest priority level descriptor queue can be polled more frequently than a polling of a lower priority level descriptor queue.
    Type: Application
    Filed: May 16, 2019
    Publication date: September 12, 2019
    Inventors: Jasvinder SINGH, Pablo DE LARA GUARCH, Kevin LAATZ, CIARA POWER, Greg CURRAN, John J. BROWNE
  • Publication number: 20190268269
    Abstract: A computing device includes an appliance status table to store at least one of reliability and performance data for one or more network functions virtualization (NFV) appliances and one or more legacy network appliances. The computing device includes a load controller to configure an Internet Protocol (IP) filter rule to select a packet for which processing of the packet is to be migrated from a selected one of the one or more legacy network appliances to a selected one of the one or more NFV appliances, and to update the appliance status table with received at least one of reliability and performance data for the one or more legacy network appliances and the one or more NFV appliances. The computing device includes a packet distributor to receive the packet, to select one of the one or more NFV appliances based at least in part on the appliance status table, and to send the packet to the selected NFV appliance. Other embodiments are described herein.
    Type: Application
    Filed: April 26, 2019
    Publication date: August 29, 2019
    Inventors: Patrick CONNOR, Andrey CHILIKIN, Brendan RYAN, Chris MACNAMARA, John J. BROWNE, Krishnamurthy JAMBUR SATHYANARAYANA, Stephen DOYLE, Tomasz KANTECKI, Anthony KELLY, Ciara LOFTUS, Fiona TRAHE
  • Publication number: 20190229897
    Abstract: Technologies for accelerated key caching in an edge hierarchy include multiple edge appliance devices organized in tiers. An edge appliance device receives a request for a key, such as a private key. The edge appliance device determines whether the key is included in a local key cache and, if not, requests the key from an edge appliance device included in an inner tier of the edge hierarchy. The edge appliance device may request the key from an edge appliance device included in a peer tier of the edge hierarchy. The edge appliance device may activate per-tenant accelerated logic to identify one or more keys in the key cache for eviction. The edge appliance device may activate per-tenant accelerated logic to identify one or more keys for pre-fetching. Those functions of the edge appliance device may be performed by an accelerator such as an FPGA. Other embodiments are described and claimed.
    Type: Application
    Filed: March 29, 2019
    Publication date: July 25, 2019
    Inventors: Timothy Verrall, Thomas Willhalm, Francesc Guim Bernat, Karthik Kumar, Ned M. Smith, Rajesh Poornachandran, Kapil Sood, Tarun Viswanathan, John J. Browne, Patrick Kutch
  • Publication number: 20190215272
    Abstract: Examples include a method of determining a first traffic overload protection policy for a first service provided by a first virtual network function in a network of virtual network functions in a computing system and determining a second traffic overload protection policy for a second service provided by a second virtual network function in the network of virtual network functions. The method includes applying the first traffic overload protection policy to the first virtual network function and the second traffic overload protection policy to the second virtual network function, wherein the first traffic overload protection policy and the second traffic overload protection policy are different.
    Type: Application
    Filed: March 14, 2019
    Publication date: July 11, 2019
    Inventors: Jasvinder SINGH, John J. BROWNE, Shobhi JAIN, Sunku RANGANATH, John O'LOUGHLIN, Emma L. FOLEY
  • Publication number: 20190207853
    Abstract: A hash calculation is performed using a portion or portions of a packet that is to be transmitted or is received. The calculated hash value can be used to select an entry that defines how the packet is to be handled. The performance of the lookup operation can be monitored and if the hash calculation is resulting in excessive collisions or extra processing steps are needed in connection with the lookup operation, then the inputs to the hash calculation can be modified to attempt to improve the performance of the lookup operation. For example, if performance of the lookup operation meets a threshold level to trigger a change in inputs, then different inputs can be selected and specified for use.
    Type: Application
    Filed: March 7, 2019
    Publication date: July 4, 2019
    Inventors: Cian FERRITER, Fei Z. WANG, Richard WALSH, John J. BROWNE
  • Patent number: 10341264
    Abstract: Technologies for scalable packet reception and transmission include a network device. The network device is to establish a ring that is defined as a circular buffer and includes a plurality of slots to store entries representative of packets. The network device is also to generate and assign receive descriptors to the slots in the ring. Each receive descriptor includes a pointer to a corresponding memory buffer to store packet data. The network device is further to determine whether the NIC has received one or more packets and copy, with direct memory access (DMA) and in response to a determination that the NIC has received one or more packets, packet data of the received one or more packets from the NIC to the memory buffers associated with the receive descriptors assigned to the slots in the ring.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: July 2, 2019
    Assignee: Intel Corporation
    Inventors: John J. Browne, Tomasz Kantecki, Chris MacNamara, Pierre Laurent, Sean Harte
  • Publication number: 20190199646
    Abstract: Packets are differentiated based on their traffic class. A traffic class is allocated bandwidth for transmission. One or more core or thread can be allocated to process packets of a traffic class for transmission based on allocated bandwidth for that traffic class. If multiple traffic classes are allocated bandwidth, and a traffic class underutilizes allocated bandwidth or a traffic class is allocated insufficient bandwidth, then allocated bandwidth can be adjusted for a future transmission time slot. For example, a higher priority traffic class with excess bandwidth can share the excess bandwidth with a next highest priority traffic class for use to allocate packets for transmission for the same time slot.
    Type: Application
    Filed: February 27, 2019
    Publication date: June 27, 2019
    Inventors: Jasvinder SINGH, John J. BROWNE, Tomasz KANTECKI, Chris MACNAMARA
  • Patent number: 10331590
    Abstract: Discloses is an apparatus including a network interface controller (NIC), memory, and an accelerator. The accelerator can include a direct memory access (DMA) controller configured to receive data packets from the NIC and to provide the data packets to the memory. The accelerator can also include processing circuitry to generate processed data packets by implementing packet processing functions on the data packets received from the NIC, and to provide the processed data packets to at least one processing core. Other methods, apparatuses, articles and systems are also described.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: June 25, 2019
    Assignee: Intel Corporation
    Inventors: Chris MacNamara, Tomasz Kantecki, John J. Browne
  • Publication number: 20190190822
    Abstract: There is disclosed in one example a computing apparatus, including: a hardware platform including at least a processor; and one or more memories having encoded thereon instructions to instruct the hardware platform to: receive a request to generate a receive descriptor profile (RDP) for the requestor's network flow; receive at least one parameter for the RDP; generate the RDP from the at least one parameter; and send the RDP to a network interface controller for the requestor.
    Type: Application
    Filed: February 13, 2019
    Publication date: June 20, 2019
    Applicant: Intel Corporation
    Inventors: Ronen Chayat, Andrey Chilikin, John J. Browne
  • Publication number: 20190155645
    Abstract: Packets received at an input port can be sub-divided into timeslots. A core or thread can process packets associated with a timeslot. The timeslot size can be increased or decreased based on utilization of a core that is allocated to process packets associated with a timeslot. A timeslot number can be assigned to each received packet. For transmission of the received packets, the timeslot number can be used to maintain an order of transmission to attempt to reduce out-of-order packet transmission.
    Type: Application
    Filed: January 23, 2019
    Publication date: May 23, 2019
    Inventors: John J. BROWNE, Chris MACNAMARA, Tomasz KANTECKI
  • Publication number: 20190141536
    Abstract: A service coordinating entity device includes communications circuitry to communicate with a first access network, processing circuitry, and a memory device. The processing circuitry is to perform operations to, in response to a request for establishing a connection with a user equipment (UE) in a second access network, retrieve a first Trusted Level Agreement (TLA) including trust attributes associated with the first access network. One or more exchanges of the trust attributes of the first TLA and trust attributes of a second TLA associated with the second access network are performed using a computing service executing on the service coordinating entity. A common TLA with trust attributes associated with communications between the first and second access networks is generated based on the exchanges. Data traffic is routed from the first access network to the UE in the second access network based on the trust attributes of the common TLA.
    Type: Application
    Filed: December 28, 2018
    Publication date: May 9, 2019
    Inventors: Alexander Bachmutsky, Dario Sabella, Francesc Guim Bernat, John J. Browne, Kapil Sood, Kshitij Arun Doshi, Mats Gustav Agerstam, Ned M. Smith, Rajesh Poornachandran, Tarun Viswanathan
  • Publication number: 20190138294
    Abstract: Various systems and methods for enabling derivation and distribution of an attestation manifest for a software update image are described. In an example, these systems and methods include orchestration functions and communications, providing functionality and components for a software update process which also provides verification and attestation among multiple devices and operators.
    Type: Application
    Filed: December 28, 2018
    Publication date: May 9, 2019
    Inventors: Ned M. Smith, Kshitij Arun Doshi, John J. Browne, Vincent J. Zimmer, Francesc Guim Bernat, Kapil Sood