Patents by Inventor John J. Ellis-Monaghan

John J. Ellis-Monaghan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200176589
    Abstract: Structures with altered crystallinity beneath semiconductor devices and methods associated with forming such structures. A semiconductor layer is implanted over a first depth range of an inert gas species to modify the crystal structure of a semiconductor material of the semiconductor layer and form a first modified region. The semiconductor layer is annealed with a first annealing process to convert the semiconductor material within the first modified region to a non-single-crystal layer. The semiconductor layer is also implanted with ions of an element over a second depth range to modify the crystal structure of the semiconductor material of the semiconductor layer and form a second modified region containing a concentration of the element. The semiconductor layer is annealed with a second annealing process to convert the semiconductor material within the second modified region to an insulator layer containing the element.
    Type: Application
    Filed: December 3, 2018
    Publication date: June 4, 2020
    Inventors: Siva P. Adusumilli, John J. Ellis-Monaghan, Anthony K. Stamper, Ian McCallum-Cook, Mark Goldstein
  • Publication number: 20200176304
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to oxidized cavity structures within and under semiconductor devices and methods of manufacture. The structure includes: a substrate material; active devices over the substrate material; an oxidized trench structure extending into the substrate and surrounding the active devices; and one or more oxidized cavity structures extending from the oxidized trench structure and formed in the substrate material under the active devices.
    Type: Application
    Filed: November 30, 2018
    Publication date: June 4, 2020
    Inventors: Siva P. ADUSUMILLI, Steven M. SHANK, John J. ELLIS-MONAGHAN, Anthony K. STAMPER
  • Patent number: 10665667
    Abstract: The present disclosure relates to a semiconductor device, and more particularly, to a junctionless/accumulation mode transistor with dynamic control and method of manufacturing. The circuit includes a channel region and a threshold voltage control on at least one side of the channel region, the threshold voltage control being configured to provide dynamic control of a voltage threshold, leakage current, and breakdown voltage of the circuit, wherein the threshold voltage control is a different dopant or material of a source region and a drain region of the circuit.
    Type: Grant
    Filed: August 14, 2018
    Date of Patent: May 26, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Anupam Dutta, John J. Ellis-Monaghan
  • Publication number: 20200150348
    Abstract: A wafer structure includes a diffractive lens disposed on a backside of a wafer and coupled to a front side waveguide, the diffractive lens being configured to receive light and focus the light to the front side waveguide.
    Type: Application
    Filed: January 10, 2020
    Publication date: May 14, 2020
    Inventors: Yoba AMOAH, Brennan J. BROWN, John J. ELLIS-MONAGHAN, Ashleigh R. KREIDER
  • Patent number: 10651281
    Abstract: Structures with altered crystallinity beneath semiconductor devices and methods associated with forming such structures. A semiconductor layer is implanted over a first depth range of an inert gas species to modify the crystal structure of a semiconductor material of the semiconductor layer and form a first modified region. The semiconductor layer is annealed with a first annealing process to convert the semiconductor material within the first modified region to a non-single-crystal layer. The semiconductor layer is also implanted with ions of an element over a second depth range to modify the crystal structure of the semiconductor material of the semiconductor layer and form a second modified region containing a concentration of the element. The semiconductor layer is annealed with a second annealing process to convert the semiconductor material within the second modified region to an insulator layer containing the element.
    Type: Grant
    Filed: December 3, 2018
    Date of Patent: May 12, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Siva P. Adusumilli, John J. Ellis-Monaghan, Anthony K. Stamper, Ian McCallum-Cook, Mark Goldstein
  • Patent number: 10642125
    Abstract: Structures providing optical beam steering and methods of fabricating such structures. A first grating coupler has a first plurality of grating structures spaced with a first pitch along a first axis. A second grating coupler has a second plurality of grating structures spaced with a second pitch along a second axis. An optical switch is coupled to the first grating coupler and to the second grating coupler. The optical switch is configured to select between the first grating coupler and the second grating coupler for optical signal routing. The second axis of the second grating coupler is aligned nonparallel to the first axis of the first grating coupler.
    Type: Grant
    Filed: July 29, 2019
    Date of Patent: May 5, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: John J. Ellis-Monaghan, Steven M. Shank, Vibhor Jain, Anthony K. Stamper, John J. Pekarik
  • Patent number: 10622506
    Abstract: Photodiode structures and methods of manufacture are disclosed. The method includes forming a waveguide structure in a dielectric layer. The method further includes forming a Ge material in proximity to the waveguide structure in a back end of the line (BEOL) metal layer. The method further includes crystallizing the Ge material into a crystalline Ge structure by a low temperature annealing process with a metal layer in contact with the Ge material.
    Type: Grant
    Filed: May 4, 2018
    Date of Patent: April 14, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: John J. Ellis-Monaghan, Jeffrey P. Gambino, Mark D. Jaffe, Kirk D. Peterson
  • Patent number: 10615302
    Abstract: Photodiode structures and methods of manufacture are disclosed. The method includes forming a waveguide structure in a dielectric layer. The method further includes forming a Ge material in proximity to the waveguide structure in a back end of the line (BEOL) metal layer. The method further includes crystallizing the Ge material into a crystalline Ge structure by a low temperature annealing process with a metal layer in contact with the Ge material.
    Type: Grant
    Filed: September 20, 2018
    Date of Patent: April 7, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: John J. Ellis-Monaghan, Jeffrey P. Gambino, Mark D. Jaffe, Kirk D. Peterson
  • Patent number: 10605992
    Abstract: A wafer structure includes a diffractive lens disposed on a backside of a wafer and coupled to a front side waveguide, the diffractive lens being configured to receive light and focus the light to the front side waveguide.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: March 31, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Yoba Amoah, Brennan J. Brown, John J. Ellis-Monaghan, Ashleigh R. Kreider
  • Patent number: 10580893
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to sealed cavity structures having a non-planar surface features and methods of manufacture. The structure includes a cavity formed in a substrate material. The cavity is covered with epitaxial material that has a non-planar surface topography which imparts a stress component on a transistor.
    Type: Grant
    Filed: April 6, 2018
    Date of Patent: March 3, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Siva P. Adusumilli, Steven M. Shank, Anthony K. Stamper, John J. Ellis-Monaghan
  • Publication number: 20200058734
    Abstract: The present disclosure relates to a semiconductor device, and more particularly, to a junctionless/accumulation mode transistor with dynamic control and method of manufacturing. The circuit includes a channel region and a threshold voltage control on at least one side of the channel region, the threshold voltage control being configured to provide dynamic control of a voltage threshold, leakage current, and breakdown voltage of the circuit, wherein the threshold voltage control is a different dopant or material of a source region and a drain region of the circuit.
    Type: Application
    Filed: August 14, 2018
    Publication date: February 20, 2020
    Inventors: Anupam DUTTA, John J. Ellis-Monaghan
  • Publication number: 20200013855
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to radio frequency (RF) switches with airgap structures and methods of manufacture. The structure includes a substrate with at least one airgap structure formed in a well region under at least one gate structure, and which extends to a junction formed by a source/drain region of the at least one gate structure.
    Type: Application
    Filed: September 19, 2019
    Publication date: January 9, 2020
    Inventors: Anthony K. STAMPER, Steven M. SHANK, John J. ELLIS-MONAGHAN, Siva P. ADUSUMILLI
  • Publication number: 20190386168
    Abstract: Photodiode structures and methods of manufacture are disclosed. The method includes forming a waveguide structure in a dielectric layer. The method further includes forming a Ge material in proximity to the waveguide structure in a back end of the line (BEOL) metal layer. The method further includes crystallizing the Ge material into a crystalline Ge structure by a low temperature annealing process with a metal layer in contact with the Ge material.
    Type: Application
    Filed: August 27, 2019
    Publication date: December 19, 2019
    Inventors: John J. ELLIS-MONAGHAN, Jeffrey P. GAMBINO, Mark D. JAFFE, Kirk D. PETERSON
  • Patent number: 10511143
    Abstract: Structures for integrated lasers, systems including integrated lasers, and associated fabrication methods. A ring waveguide and a seed region are arranged interior of the ring waveguide. A laser strip extends across a portion of the ring waveguide. The laser strip has an end contacting the seed region and another opposing end. The laser strip includes a laser medium and a p-n junction capable of generating electromagnetic radiation. The p-n junction of the laser strip is aligned with a portion of the ring waveguide.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: December 17, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: John J. Ellis-Monaghan, Sebastian Ventrone, Vibhor Jain, Yves Ngu
  • Patent number: 10509244
    Abstract: Structures for an optical switch, structures for an optical router, and methods of fabricating a structure for an optical switch. A phase change layer is arranged proximate to a waveguide core, and a heater is formed proximate to the phase change layer. The phase change layer is composed of a phase change material having a first state with a first refractive index at a first temperature and a second state with a second refractive index at a second temperature. The heater is configured to selectively transfer heat to the phase change layer for transitioning between the first state and the second state.
    Type: Grant
    Filed: December 11, 2018
    Date of Patent: December 17, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Steven M. Shank, Anthony K. Stamper, John J. Ellis-Monaghan, Vibhor Jain, John J. Pekarik
  • Publication number: 20190355865
    Abstract: Photodiode structures and methods of manufacture are disclosed. The method includes forming a waveguide structure in a dielectric layer. The method further includes forming a Ge material in proximity to the waveguide structure in a back end of the line (BEOL) metal layer. The method further includes crystallizing the Ge material into a crystalline Ge structure by a low temperature annealing process with a metal layer in contact with the Ge material.
    Type: Application
    Filed: August 5, 2019
    Publication date: November 21, 2019
    Inventors: John J. ELLIS-MONAGHAN, Jeffrey P. GAMBINO, Mark D. JAFFE, Kirk D. PETERSON
  • Publication number: 20190348514
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to poly gate extension source to body contact structures and methods of manufacture. The structure includes: a substrate having a doped region; a gate structure over the doped region, the gate structure having a main body and a gate extension region; and a body contact region straddling over the gate extension region and remote from the main body of the gate structure.
    Type: Application
    Filed: July 24, 2019
    Publication date: November 14, 2019
    Inventor: John J. ELLIS-MONAGHAN
  • Patent number: 10461152
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to radio frequency (RF) switches with airgap structures and methods of manufacture. The structure includes a substrate with at least one airgap structure formed in a well region under at least one gate structure, and which extends to a junction formed by a source/drain region of the at least one gate structure.
    Type: Grant
    Filed: July 10, 2017
    Date of Patent: October 29, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Anthony K. Stamper, Steven M. Shank, John J. Ellis-Monaghan, Siva P. Adusumilli
  • Patent number: 10453987
    Abstract: Photodiode structures and methods of manufacture are disclosed. The method includes forming a waveguide structure in a dielectric layer. The method further includes forming a Ge material in proximity to the waveguide structure in a back end of the line (BEOL) metal layer. The method further includes crystallizing the Ge material into a crystalline Ge structure by a low temperature annealing process with a metal layer in contact with the Ge material.
    Type: Grant
    Filed: November 8, 2017
    Date of Patent: October 22, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: John J. Ellis-Monaghan, Jeffrey P. Gambino, Mark D. Jaffe, Kirk D. Peterson
  • Publication number: 20190312142
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to sealed cavity structures having a non-planar surface features and methods of manufacture. The structure includes a cavity formed in a substrate material. The cavity is covered with epitaxial material that has a non-planar surface topography which imparts a stress component on a transistor.
    Type: Application
    Filed: April 6, 2018
    Publication date: October 10, 2019
    Inventors: Siva P. ADUSUMILLI, Steven M. SHANK, Anthony K. STAMPER, John J. ELLIS-MONAGHAN