Abstract: Embodiments are directed to a self-reference STT-MRAM sensing scheme that uses offset-cancellation to reduce the impact of FET mismatch and thereby allow the sensing of lower read voltages. In some embodiments, the sensing scheme includes a differential amplifier having a first input connected to a memory cell. In some embodiments, a second input of the differential amplifier may be connected to ground, a common mode voltage of the system or a mid-level supply voltage. The present disclosure provides flexibility with respect to the voltage level at which the sensing is performed (e.g., ground, Voc, Vmid, etc.). The present disclosure provides further flexibility with respect to the sense voltage polarity.

Abstract: A technique for sensing a data state of a data cell. A comparator has a first input at a node A and a second input at a node B. A first n-channel transistor is connected to a first p-channel transistor at the node A. A second n-channel transistor is connected to a second p-channel transistor at the node B. A multiplexer is configured to selectively connect a first reference cell or the data cell to the first n-channel transistor and configured to selectively connect the data cell or a second reference cell to the second re-channel transistor. The comparator outputs the data state of the data cell based on input of a node A voltage at the node A and a node B voltage at the node B.

Abstract: A technique relates magnetoresistive random access memory (MRAM). A dielectric layer is disposed on a transistor, and the transistor is formed in a uniform crystalline substrate. A hole is formed through the dielectric layer to reach the transistor. A polycrystalline material is disposed in the hole by using selective epitaxial growth (SEG), and the polycrystalline material is annealed to create an epitaxial stud. A magnetic tunnel junction (MTJ) is disposed on the epitaxial stud (SEG).

Abstract: Embodiments are directed to detecting a state of a memory element in a memory device, comprising: applying a pulse of a predetermined magnitude and duration to the memory element to induce a transition in the state of the memory element when a polarity of the pulse is opposite to the state, monitoring, by a device, a signal associated with the memory element to detect a presence or absence of a transition in the signal in an amount greater than a threshold, and determining the state of the memory element based on said monitoring.

Abstract: A technique for sensing a data state of a data cell. A comparator has a first input at a node A and a second input at a node B. A first n-channel transistor is connected to a first p-channel transistor at the node A. A second n-channel transistor is connected to a second p-channel transistor at the node B. A multiplexer is configured to selectively connect a first reference cell or the data cell to the first n-channel transistor and configured to selectively connect the data cell or a second reference cell to the second n-channel transistor. The comparator outputs the data state of the data cell based on input of a node A voltage at the node A and a node B voltage at the node B.

Abstract: According to one aspect, a method for adaptive error correction in a memory system includes reading data from a memory array of a non-volatile memory device in the memory system. Error correcting logic checks the data for at least one error condition stored in the memory array. Based on determining that the at least one error condition exists, a write-back indicator is asserted by the error correcting logic to request correction of the at least one error condition. Based on determining that the at least one error condition does not exist, accesses of the memory array continue without asserting the write-back indicator.

Abstract: According to one aspect, a method for adaptive error correction in a memory system includes reading data from a memory array of a non-volatile memory device in the memory system. Error correcting logic checks the data for at least one error condition stored in the memory array. Based on determining that the at least one error condition exists, a write-back indicator is asserted by the error correcting logic to request correction of the at least one error condition. Based on determining that the at least one error condition does not exist, accesses of the memory array continue without asserting the write-back indicator.

Abstract: Embodiments are directed to a self-reference STT-MRAM sensing scheme that uses offset-cancellation to reduce the impact of FET mismatch and thereby allow the sensing of lower read voltages. In some embodiments, the sensing scheme includes a differential amplifier having a first input connected to a memory cell. In some embodiments, a second input of the differential amplifier may be connected to ground, a common mode voltage of the system or a mid-level supply voltage. The present disclosure provides flexibility with respect to the voltage level at which the sensing is performed (e.g., ground, Voc, Vmid, etc.). The present disclosure provides further flexibility with respect to the sense voltage polarity.

Abstract: Embodiments are directed to detecting a state of a memory element in a memory device, comprising: applying a pulse of a predetermined magnitude and duration to the memory element to induce a transition in the state of the memory element when a polarity of the pulse is opposite to the state, monitoring, by a device, a signal associated with the memory element to detect a presence or absence of a transition in the signal in an amount greater than a threshold, and determining the state of the memory element based on said monitoring.

Abstract: A thermally assisted magnetoresistive random access memory cell, a corresponding array, and a method for fabricating the array. An example cell includes a first metal layer, a second metal layer, an interlayer, a first magnetic stack, and a first non-magnetic via. The first metal layer includes a pad and a first metal line, with the pad not in direct contact with the first metal line. The second metal layer includes a second metal line and a metal strap. The second metal line is perpendicular to the first metal line and not in contact with the metal strap. The interlayer is located between the first and second metal layers. The first metal line is not in direct contact with the interlayer. The first magnetic stack is in direct contact with the interlayer and the metal strap. The first non-magnetic via is in direct contact with the pad and the metal strap.

Abstract: Embodiments are directed to detecting a state of a memory element in a memory device, comprising: applying a pulse of a predetermined magnitude and duration to the memory element to induce a transition in the state of the memory element when a polarity of the pulse is opposite to the state, monitoring, by a device, a signal associated with the memory element to detect a presence or absence of a transition in the signal in an amount greater than a threshold, and determining the state of the memory element based on said monitoring.

Abstract: A thermally assisted magnetoresistive random access memory cell, a corresponding array, and a method for fabricating the array. An example cell includes a first metal layer, a second metal layer, an interlayer, a first magnetic stack, and a first non-magnetic via. The first metal layer includes a pad and a first metal line, with the pad not in direct contact with the first metal line. The second metal layer includes a second metal line and a metal strap. The second metal line is perpendicular to the first metal line and not in contact with the metal strap. The interlayer is located between the first and second metal layers. The first metal line is not in direct contact with the interlayer. The first magnetic stack is in direct contact with the interlayer and the metal strap. The first non-magnetic via is in direct contact with the pad and the metal strap.

Abstract: A system and method for fabricating a memory array device. An example memory array device includes a plurality of memory cells, each including a FET over a substrate and a memory element over the FET. Each memory element includes a plurality of epitaxially grown memory element layers. The memory array device includes a plurality of gate conductors configured a first axis, in parallel. Each gate conductor laterally surrounds a plurality of FETs of the memory cells along the first axis. The memory array device includes a plurality of bit lines configured along a second axis, in parallel, and electrically coupled to a plurality of memory elements along the second axis. Embodiments of the memory array preserve alignment of crystal lattices beginning from the bottom layers in the FET up to the top active layers in memory element, thus preserving crystal lattice alignment between transistor and memory element.

Abstract: A thermally assisted magnetoresistive random access memory cell, a corresponding array, and a method for fabricating the array. An example cell includes a first metal layer, a second metal layer, an interlayer, a first magnetic stack, and a first non-magnetic via. The first metal layer includes a pad and a first metal line, with the pad not in direct contact with the first metal line. The second metal layer includes a second metal line and a metal strap. The second metal line is perpendicular to the first metal line and not in contact with the metal strap. The interlayer is located between the first and second metal layers. The first metal line is not in direct contact with the interlayer. The first magnetic stack is in direct contact with the interlayer and the metal strap. The first non-magnetic via is in direct contact with the pad and the metal strap.

Abstract: A system and method for fabricating a memory array device. An example memory array device includes a plurality of memory cells, each including a FET over a substrate and a memory element over the FET. Each memory element includes a plurality of epitaxially grown memory element layers. The memory elements formed utilizing two etches through all epitaxially grown layers. Each of these etches can be split to two separate processes specific to CMOS transistor etch and to memory element etch. The memory array device includes a plurality of gate conductors configured along a first axis, in parallel. Each FET of the memory cells adjacent to two gate conductors. The memory array device includes a plurality of bit lines configured along a second axis, in parallel, and electrically coupled to a plurality of memory elements along the second axis.

Abstract: A system and method for fabricating a memory array device. An example memory array device includes a plurality of memory cells, each including a FET over a substrate and a memory element over the FET. Each memory element includes a plurality of epitaxially grown memory element layers. The memory array device includes a plurality of gate conductors configured a first axis, in parallel. Each gate conductor laterally surrounds a plurality of FETs of the memory cells along the first axis. The memory array device includes a plurality of bit lines configured along a second axis, in parallel, and electrically coupled to a plurality of memory elements along the second axis. Embodiments of the memory array preserve alignment of crystal lattices beginning from the bottom layers in the FET up to the top active layers in memory element, thus preserving crystal lattice alignment between transistor and memory element.

Abstract: A system and method for fabricating a memory array device. An example memory array device includes a plurality of memory cells, each including a FET over a substrate and a memory element over the FET. Each memory element includes a plurality of epitaxially grown memory element layers. The memory elements formed utilizing two etches through all epitaxially grown layers. Each of these etches can be split to two separate processes specific to CMOS transistor etch and to memory element etch. The memory array device includes a plurality of gate conductors configured along a first axis, in parallel. Each FET of the memory cells adjacent to two gate conductors. The memory array device includes a plurality of bit lines configured along a second axis, in parallel, and electrically coupled to a plurality of memory elements along the second axis.

Abstract: A system and method for fabricating a memory array device. An example memory array device includes a plurality of memory cells, each including a FET over a substrate and a memory element over the FET. Each memory element includes a plurality of epitaxially grown memory element layers. The memory array device includes a plurality of gate conductors configured a first axis, in parallel. Each gate conductor laterally surrounds a plurality of FETs of the memory cells along the first axis. The memory array device includes a plurality of bit lines configured along a second axis, in parallel, and electrically coupled to a plurality of memory elements along the second axis. Embodiments of the memory array preserve alignment of crystal lattices beginning from the bottom layers in the FET up to the top active layers in memory element, thus preserving crystal lattice alignment between transistor and memory element.

Abstract: A system and method for fabricating a memory array device. An example memory array device includes a plurality of memory cells, each including a FET over a substrate and a memory element over the FET. Each memory element includes a plurality of epitaxially grown memory element layers. The memory array device includes a plurality of gate conductors configured a first axis, in parallel. Each gate conductor laterally surrounds a plurality of FETs of the memory cells along the first axis. The memory array device includes a plurality of bit lines configured along a second axis, in parallel, and electrically coupled to a plurality of memory elements along the second axis. Embodiments of the memory array preserve alignment of crystal lattices beginning from the bottom layers in the FET up to the top active layers in memory element, thus preserving crystal lattice alignment between transistor and memory element.

Abstract: A system and method for fabricating a memory array device. An example memory array device includes a plurality of memory cells, each including a FET over a substrate and a memory element over the FET. Each memory element includes a plurality of epitaxially grown memory element layers. The memory elements formed utilizing two etches through all epitaxially grown layers. Each of these etches can be split to two separate processes specific to CMOS transistor etch and to memory element etch. The memory array device includes a plurality of gate conductors configured along a first axis, in parallel. Each FET of the memory cells adjacent to two gate conductors. The memory array device includes a plurality of bit lines configured along a second axis, in parallel, and electrically coupled to a plurality of memory elements along the second axis.